The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


[ source navigation ] [ diff markup ] [ identifier search ] [ freetext search ] [ file search ] [ list types ] [ track identifier ]

FreeBSD/Linux Kernel Cross Reference
sys/mips/malta/gtreg.h

Version: -  FREEBSD  -  FREEBSD-12-STABLE  -  FREEBSD-12-0  -  FREEBSD-11-STABLE  -  FREEBSD-11-2  -  FREEBSD-11-1  -  FREEBSD-11-0  -  FREEBSD-10-STABLE  -  FREEBSD-10-4  -  FREEBSD-10-3  -  FREEBSD-10-2  -  FREEBSD-10-1  -  FREEBSD-10-0  -  FREEBSD-9-STABLE  -  FREEBSD-9-3  -  FREEBSD-9-2  -  FREEBSD-9-1  -  FREEBSD-9-0  -  FREEBSD-8-STABLE  -  FREEBSD-8-4  -  FREEBSD-8-3  -  FREEBSD-8-2  -  FREEBSD-8-1  -  FREEBSD-8-0  -  FREEBSD-7-STABLE  -  FREEBSD-7-4  -  FREEBSD-7-3  -  FREEBSD-7-2  -  FREEBSD-7-1  -  FREEBSD-7-0  -  FREEBSD-6-STABLE  -  FREEBSD-6-4  -  FREEBSD-6-3  -  FREEBSD-6-2  -  FREEBSD-6-1  -  FREEBSD-6-0  -  FREEBSD-5-STABLE  -  FREEBSD-5-5  -  FREEBSD-5-4  -  FREEBSD-5-3  -  FREEBSD-5-2  -  FREEBSD-5-1  -  FREEBSD-5-0  -  FREEBSD-4-STABLE  -  FREEBSD-3-STABLE  -  FREEBSD22  -  linux-2.6  -  linux-2.4.22  -  MK83  -  MK84  -  PLAN9  -  DFBSD  -  NETBSD  -  NETBSD5  -  NETBSD4  -  NETBSD3  -  NETBSD20  -  OPENBSD  -  xnu-517  -  xnu-792  -  xnu-792.6.70  -  xnu-1228  -  xnu-1456.1.26  -  xnu-1699.24.8  -  xnu-2050.18.24  -  OPENSOLARIS  -  minix-3-1-1 
SearchContext: -  none  -  3  -  10 

    1 /*      $NetBSD: gtreg.h,v 1.2 2005/12/24 20:07:03 perry Exp $  */
    2 
    3 /*-
    4  * Copyright (c) 1997, 1998, 2001 The NetBSD Foundation, Inc.
    5  * All rights reserved.
    6  *
    7  * This code is derived from software contributed to The NetBSD Foundation
    8  * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
    9  * NASA Ames Research Center.
   10  *
   11  * Redistribution and use in source and binary forms, with or without
   12  * modification, are permitted provided that the following conditions
   13  * are met:
   14  * 1. Redistributions of source code must retain the above copyright
   15  *    notice, this list of conditions and the following disclaimer.
   16  * 2. Redistributions in binary form must reproduce the above copyright
   17  *    notice, this list of conditions and the following disclaimer in the
   18  *    documentation and/or other materials provided with the distribution.
   19  *
   20  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
   21  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
   22  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
   23  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
   24  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
   25  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
   26  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
   27  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
   28  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
   29  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
   30  * POSSIBILITY OF SUCH DAMAGE.
   31  *
   32  * $FreeBSD: releng/8.4/sys/mips/malta/gtreg.h 215938 2010-11-27 12:26:40Z jchandra $
   33  */
   34 
   35 
   36 
   37 #define GT_REGVAL(x)    *((volatile u_int32_t *) \
   38                             (MIPS_PHYS_TO_KSEG1(MALTA_CORECTRL_BASE + (x))))
   39 
   40 /* CPU Configuration Register Map */
   41 #define GT_CPU_INT      0x000
   42 #define GT_MULTIGT      0x120
   43 
   44 /* CPU Address Decode Register Map */
   45 
   46 /* CPU Error Report Register Map */
   47 
   48 /* CPU Sync Barrier Register Map */
   49 
   50 /* SDRAM and Device Address Decode Register Map */
   51 
   52 /* SDRAM Configuration Register Map */
   53 
   54 /* SDRAM Parameters Register Map */
   55 
   56 /* ECC Register Map */
   57 
   58 /* Device Parameters Register Map */
   59 
   60 /* DMA Record Register Map */
   61 
   62 /* DMA Arbiter Register Map */
   63 
   64 /* Timer/Counter Register Map */
   65 //#define       GT_TC_0         0x850
   66 //#define       GT_TC_1         0x854
   67 //#define       GT_TC_2         0x858
   68 //#define       GT_TC_3         0x85c
   69 //#define       GT_TC_CONTROL   0x864
   70 
   71 /* PCI Internal Register Map */
   72 #define GT_PCI0_CFG_ADDR        0xcf8
   73 #define GT_PCI0_CFG_DATA        0xcfc
   74 #define GT_PCI0_INTR_ACK        0xc34
   75 
   76 /* Interrupts Register Map */
   77 #define GT_INTR_CAUSE   0xc18
   78 #define  GTIC_INTSUM     0x00000001
   79 #define  GTIC_MEMOUT     0x00000002
   80 #define  GTIC_DMAOUT     0x00000004
   81 #define  GTIC_CPUOUT     0x00000008
   82 #define  GTIC_DMA0COMP   0x00000010
   83 #define  GTIC_DMA1COMP   0x00000020
   84 #define  GTIC_DMA2COMP   0x00000040
   85 #define  GTIC_DMA3COMP   0x00000080
   86 #define  GTIC_T0EXP      0x00000100
   87 #define  GTIC_T1EXP      0x00000200
   88 #define  GTIC_T2EXP      0x00000400
   89 #define  GTIC_T3EXP      0x00000800
   90 #define  GTIC_MASRDERR0  0x00001000
   91 #define  GTIC_SLVWRERR0  0x00002000
   92 #define  GTIC_MASWRERR0  0x00004000
   93 #define  GTIC_SLVRDERR0  0x00008000
   94 #define  GTIC_ADDRERR0   0x00010000
   95 #define  GTIC_MEMERR     0x00020000
   96 #define  GTIC_MASABORT0  0x00040000
   97 #define  GTIC_TARABORT0  0x00080000
   98 #define  GTIC_RETRYCNT0  0x00100000
   99 #define  GTIC_PMCINT_0   0x00200000
  100 #define  GTIC_CPUINT     0x0c300000
  101 #define  GTIC_PCINT      0xc3000000
  102 #define  GTIC_CPUINTSUM  0x40000000
  103 #define  GTIC_PCIINTSUM  0x80000000
  104 
  105 /* PCI Configuration Register Map */
  106 //#define       GT_PCICONFIGBASE        0
  107 //#define       GT_PCIDID               BONITO(GT_PCICONFIGBASE + 0x00)
  108 //#define       GT_PCICMD               BONITO(GT_PCICONFIGBASE + 0x04)
  109 //#define       GT_PCICLASS             BONITO(GT_PCICONFIGBASE + 0x08)
  110 //#define       GT_PCILTIMER            BONITO(GT_PCICONFIGBASE + 0x0c)
  111 //#define       GT_PCIBASE0             BONITO(GT_PCICONFIGBASE + 0x10)
  112 //#define       GT_PCIBASE1             BONITO(GT_PCICONFIGBASE + 0x14)
  113 //#define       GT_PCIBASE2             BONITO(GT_PCICONFIGBASE + 0x18)
  114 //#define       GT_PCIEXPRBASE          BONITO(GT_PCICONFIGBASE + 0x30)
  115 //#define       GT_PCIINT               BONITO(GT_PCICONFIGBASE + 0x3c)
  116 
  117 /* PCI Configuration, Function 1, Register Map */
  118 
  119 /* I2O Support Register Map */

Cache object: 7c69c362cdfa423355ec72be7d605964


[ source navigation ] [ diff markup ] [ identifier search ] [ freetext search ] [ file search ] [ list types ] [ track identifier ]


This page is part of the FreeBSD/Linux Linux Kernel Cross-Reference, and was automatically generated using a modified version of the LXR engine.