The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


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FreeBSD/Linux Kernel Cross Reference
sys/mips/malta/maltareg.h

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    1 /*      $NetBSD: maltareg.h,v 1.1 2002/03/07 14:44:04 simonb Exp $      */
    2 
    3 /*
    4  * Copyright 2002 Wasabi Systems, Inc.
    5  * All rights reserved.
    6  *
    7  * Written by Simon Burge for Wasabi Systems, Inc.
    8  *
    9  * Redistribution and use in source and binary forms, with or without
   10  * modification, are permitted provided that the following conditions
   11  * are met:
   12  * 1. Redistributions of source code must retain the above copyright
   13  *    notice, this list of conditions and the following disclaimer.
   14  * 2. Redistributions in binary form must reproduce the above copyright
   15  *    notice, this list of conditions and the following disclaimer in the
   16  *    documentation and/or other materials provided with the distribution.
   17  * 3. All advertising materials mentioning features or use of this software
   18  *    must display the following acknowledgement:
   19  *      This product includes software developed for the NetBSD Project by
   20  *      Wasabi Systems, Inc.
   21  * 4. The name of Wasabi Systems, Inc. may not be used to endorse
   22  *    or promote products derived from this software without specific prior
   23  *    written permission.
   24  *
   25  * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
   26  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
   27  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
   28  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL WASABI SYSTEMS, INC
   29  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
   30  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
   31  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
   32  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
   33  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
   34  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
   35  * POSSIBILITY OF SUCH DAMAGE.
   36  *
   37  * $FreeBSD: stable/10/sys/mips/malta/maltareg.h 202175 2010-01-12 21:36:08Z imp $
   38  */
   39 
   40 /*
   41         Memory Map
   42 
   43         0000.0000 *     128MB   Typically SDRAM (on Core Board)
   44         0800.0000 *     256MB   Typically PCI
   45         1800.0000 *      62MB   Typically PCI
   46         1be0.0000 *       2MB   Typically System controller's internal registers
   47         1c00.0000 *      32MB   Typically not used
   48         1e00.0000         4MB   Monitor Flash
   49         1e40.0000        12MB   reserved
   50         1f00.0000        12MB   Switches
   51                                 LEDs
   52                                 ASCII display
   53                                 Soft reset
   54                                 FPGA revision number
   55                                 CBUS UART (tty2)
   56                                 General Purpose I/O
   57                                 I2C controller
   58         1f10.0000 *      11MB   Typically System Controller specific
   59         1fc0.0000         4MB   Maps to Monitor Flash
   60         1fd0.0000 *       3MB   Typically System Controller specific
   61 
   62                   * depends on implementation of the Core Board and of software
   63  */
   64 
   65 /*
   66         CPU interrupts
   67 
   68                 NMI     South Bridge or NMI button
   69                  0      South Bridge INTR
   70                  1      South Bridge SMI
   71                  2      CBUS UART (tty2)
   72                  3      COREHI (Core Card)
   73                  4      CORELO (Core Card)
   74                  5      Not used, driven inactive (typically CPU internal timer interrupt
   75 
   76         IRQ mapping (as used by YAMON)
   77 
   78                 0       Timer           South Bridge
   79                 1       Keyboard        SuperIO
   80                 2                       Reserved by South Bridge (for cascading)
   81                 3       UART (tty1)     SuperIO
   82                 4       UART (tty0)     SuperIO
   83                 5                       Not used
   84                 6       Floppy Disk     SuperIO
   85                 7       Parallel Port   SuperIO
   86                 8       Real Time Clock South Bridge
   87                 9       I2C bus         South Bridge
   88                 10      PCI A,B,eth     PCI slot 1..4, Ethernet
   89                 11      PCI C,audio     PCI slot 1..4, Audio, USB (South Bridge)
   90                         PCI D,USB
   91                 12      Mouse           SuperIO
   92                 13                      Reserved by South Bridge
   93                 14      Primary IDE     Primary IDE slot
   94                 15      Secondary IDE   Secondary IDE slot/Compact flash connector
   95  */
   96 
   97 #define MALTA_SYSTEMRAM_BASE    0x00000000ul  /* System RAM:    */
   98 #define MALTA_SYSTEMRAM_SIZE    0x08000000  /*   128 MByte      */
   99 
  100 #define MALTA_PCIMEM1_BASE      0x08000000ul  /* PCI 1 memory:  */
  101 #define MALTA_PCIMEM1_SIZE      0x08000000  /*   128 MByte      */
  102 
  103 #define MALTA_PCIMEM2_BASE      0x10000000ul  /* PCI 2 memory:  */
  104 #define MALTA_PCIMEM2_SIZE      0x08000000  /*   128 MByte      */
  105 
  106 #define MALTA_PCIMEM3_BASE      0x18000000ul  /* PCI 3 memory   */
  107 #define MALTA_PCIMEM3_SIZE      0x03e00000  /*    62 MByte      */
  108 
  109 #define MALTA_CORECTRL_BASE     0x1be00000ul  /* Core control:  */
  110 #define MALTA_CORECTRL_SIZE     0x00200000  /*     2 MByte      */
  111 
  112 #define MALTA_RESERVED_BASE1    0x1c000000ul  /* Reserved:      */
  113 #define MALTA_RESERVED_SIZE1    0x02000000  /*    32 MByte      */
  114 
  115 #define MALTA_MONITORFLASH_BASE 0x1e000000ul  /* Monitor Flash: */
  116 #define MALTA_MONITORFLASH_SIZE 0x003e0000  /*     4 MByte      */
  117 #define MALTA_MONITORFLASH_SECTORSIZE 0x00010000 /* Sect. = 64 KB */
  118 
  119 #define MALTA_FILEFLASH_BASE    0x1e3e0000ul /* File Flash (for monitor): */
  120 #define MALTA_FILEFLASH_SIZE    0x00020000 /*   128 KByte       */
  121 
  122 #define MALTA_FILEFLASH_SECTORSIZE 0x00010000 /* Sect. = 64 KB  */
  123 
  124 #define MALTA_RESERVED_BASE2    0x1e400000ul  /* Reserved:      */
  125 #define MALTA_RESERVED_SIZE2    0x00c00000  /*    12 MByte      */
  126 
  127 #define MALTA_FPGA_BASE         0x1f000000ul  /* FPGA:          */
  128 #define MALTA_FPGA_SIZE         0x00c00000  /*    12 MByte      */
  129 
  130 #define MALTA_NMISTATUS         (MALTA_FPGA_BASE + 0x24)
  131 #define  MALTA_NMI_SB            0x2    /* Pending NMI from the South Bridge */
  132 #define  MALTA_NMI_ONNMI         0x1    /* Pending NMI from the ON/NMI push button */
  133 
  134 #define MALTA_NMIACK            (MALTA_FPGA_BASE + 0x104)
  135 #define  MALTA_NMIACK_ONNMI      0x1    /* Write 1 to acknowledge ON/NMI */
  136 
  137 #define MALTA_SWITCH            (MALTA_FPGA_BASE + 0x200)
  138 #define  MALTA_SWITCH_MASK       0xff   /* settings of DIP switch S2 */
  139 
  140 #define MALTA_STATUS            (MALTA_FPGA_BASE + 0x208)
  141 #define  MALTA_ST_MFWR           0x10   /* Monitor Flash is write protected (JP1) */
  142 #define  MALTA_S54               0x08   /* switch S5-4 - set YAMON factory default mode */
  143 #define  MALTA_S53               0x04   /* switch S5-3 */
  144 #define  MALTA_BIGEND            0x02   /* switch S5-2 - big endian mode */
  145 
  146 #define MALTA_JMPRS             (MALTA_FPGA_BASE + 0x210)
  147 #define  MALTA_JMPRS_PCICLK      0x1c   /* PCI clock frequency */
  148 #define  MALTA_JMPRS_EELOCK      0x02   /* I2C EEPROM is write protected */
  149 
  150 #define MALTA_LEDBAR            (MALTA_FPGA_BASE + 0x408)
  151 #define MALTA_ASCIIWORD         (MALTA_FPGA_BASE + 0x410)
  152 #define MALTA_ASCII_BASE        (MALTA_FPGA_BASE + 0x418)
  153 #define MALTA_ASCIIPOS0         0x00
  154 #define MALTA_ASCIIPOS1         0x08
  155 #define MALTA_ASCIIPOS2         0x10
  156 #define MALTA_ASCIIPOS3         0x18
  157 #define MALTA_ASCIIPOS4         0x20
  158 #define MALTA_ASCIIPOS5         0x28
  159 #define MALTA_ASCIIPOS6         0x30
  160 #define MALTA_ASCIIPOS7         0x38
  161 
  162 #define MALTA_SOFTRES           (MALTA_FPGA_BASE + 0x500)
  163 #define  MALTA_GORESET           0x42   /* write this to MALTA_SOFTRES for board reset */
  164 
  165 /*
  166  * BRKRES is the number of milliseconds before a "break" on tty will
  167  * trigger a reset.  A value of 0 will disable the reset.
  168  */
  169 #define MALTA_BRKRES            (MALTA_FPGA_BASE + 0x508)
  170 #define  MALTA_BRKRES_MASK       0xff
  171 
  172 #define MALTA_CBUSUART          (MALTA_FPGA_BASE + 0x900)
  173 /* 16C550C UART, 8 bit registers on 8 byte boundaries */
  174 /* RXTX    0x00 */
  175 /* INTEN   0x08 */
  176 /* IIFIFO  0x10 */
  177 /* LCTRL   0x18 */
  178 /* MCTRL   0x20 */
  179 /* LSTAT   0x28 */
  180 /* MSTAT   0x30 */
  181 /* SCRATCH 0x38 */
  182 #define MALTA_CBUSUART_INTR     2
  183 
  184 #define MALTA_GPIO_BASE         (MALTA_FPGA_BASE + 0xa00)
  185 #define MALTA_GPOUT             0x0
  186 #define MALTA_GPINP             0x8
  187 
  188 #define MALTA_I2C_BASE          (MALTA_FPGA_BASE + 0xb00)
  189 #define MALTA_I2CINP            0x00
  190 #define MALTA_I2COE             0x08
  191 #define MALTA_I2COUT            0x10
  192 #define MALTA_I2CSEL            0x18
  193 
  194 #define MALTA_BOOTROM_BASE      0x1fc00000ul  /* Boot ROM:      */
  195 #define MALTA_BOOTROM_SIZE      0x00400000  /*     4 MByte      */
  196 
  197 #define MALTA_REVISION          0x1fc00010ul
  198 #define  MALTA_REV_FPGRV         0xff0000       /* CBUS FPGA revision */
  199 #define  MALTA_REV_CORID         0x00fc00       /* Core Board ID */
  200 #define  MALTA_REV_CORRV         0x000300       /* Core Board Revision */
  201 #define  MALTA_REV_PROID         0x0000f0       /* Product ID */
  202 #define  MALTA_REV_PRORV         0x00000f       /* Product Revision */
  203 
  204 /* PCI definitions */
  205 #define MALTA_SOUTHBRIDGE_INTR     0
  206 
  207 #define MALTA_PCI0_IO_BASE         MALTA_PCIMEM3_BASE
  208 #define MALTA_PCI0_ADDR( addr )    (MALTA_PCI0_IO_BASE + (addr))
  209 
  210 #define MALTA_RTCADR               0x70 // MALTA_PCI_IO_ADDR8(0x70)
  211 #define MALTA_RTCDAT               0x71 // MALTA_PCI_IO_ADDR8(0x71)
  212 
  213 #define MALTA_SMSC_COM1_ADR        0x3f8
  214 #define MALTA_SMSC_COM2_ADR        0x2f8
  215 #define MALTA_UART0ADR             MALTA_PCI0_ADDR(MALTA_SMSC_COM1_ADR)
  216 #define MALTA_UART1ADR             MALTA_SMSC_COM2_ADR // MALTA_PCI0_ADDR(MALTA_SMSC_COM2_ADR)
  217 
  218 #define MALTA_SMSC_1284_ADR        0x378
  219 #define MALTA_1284ADR              MALTA_SMSC_1284_ADR // MALTA_PCI0_ADDR(MALTA_SMSC_1284_ADR)
  220 
  221 #define MALTA_SMSC_FDD_ADR         0x3f0
  222 #define MALTA_FDDADR               MALTA_SMSC_FDD_ADR // MALTA_PCI0_ADDR(MALTA_SMSC_FDD_ADR)
  223 
  224 #define MALTA_SMSC_KYBD_ADR        0x60  /* Fixed 0x60, 0x64 */
  225 #define MALTA_KYBDADR              MALTA_SMSC_KYBD_ADR // MALTA_PCI0_ADDR(MALTA_SMSC_KYBD_ADR)
  226 #define MALTA_SMSC_MOUSE_ADR       MALTA_SMSC_KYBD_ADR
  227 #define MALTA_MOUSEADR             MALTA_KYBDADR
  228 
  229 
  230 #define MALTA_DMA_PCI_PCIBASE   0x00000000UL
  231 #define MALTA_DMA_PCI_PHYSBASE  0x00000000UL
  232 #define MALTA_DMA_PCI_SIZE      (256 * 1024 * 1024)
  233 
  234 #define MALTA_DMA_ISA_PCIBASE   0x00800000UL
  235 #define MALTA_DMA_ISA_PHYSBASE  0x00000000UL
  236 #define MALTA_DMA_ISA_SIZE      (8 * 1024 * 1024)
  237 
  238 #ifndef _LOCORE
  239 void    led_bar(uint8_t);
  240 void    led_display_word(uint32_t);
  241 void    led_display_str(const char *);
  242 void    led_display_char(int, uint8_t);
  243 #endif

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