The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


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FreeBSD/Linux Kernel Cross Reference
sys/mips/mediatek/mtk_pcie.h

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    1 /*-
    2  * Copyright (c) 2016 Stanislav Galabov.
    3  * All rights reserved.
    4  *
    5  * Redistribution and use in source and binary forms, with or without
    6  * modification, are permitted provided that the following conditions
    7  * are met:
    8  * 1. Redistributions of source code must retain the above copyright
    9  *    notice, this list of conditions and the following disclaimer.
   10  * 2. Redistributions in binary form must reproduce the above copyright
   11  *    notice, this list of conditions and the following disclaimer in the
   12  *    documentation and/or other materials provided with the distribution.
   13  *
   14  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
   15  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   16  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   17  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
   18  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
   19  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
   20  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
   21  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
   22  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   23  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   24  * SUCH DAMAGE.
   25  *
   26  * $FreeBSD: stable/12/sys/mips/mediatek/mtk_pcie.h 297850 2016-04-12 07:21:22Z sgalabov $
   27  */
   28 #ifndef __MTK_PCIE_H__
   29 #define __MTK_PCIE_H__
   30 
   31 #define MTK_PCI_NIRQS                   3
   32 #define MTK_PCI_BASESLOT                0
   33 
   34 struct mtk_pci_softc {
   35         device_t                sc_dev;
   36 
   37         struct resource *       pci_res[MTK_PCI_NIRQS + 1];
   38         void *                  pci_intrhand[MTK_PCI_NIRQS];
   39 
   40         int                     sc_busno;
   41         int                     sc_cur_secbus;
   42 
   43         struct rman             sc_mem_rman;
   44         struct rman             sc_io_rman;
   45         struct rman             sc_irq_rman;
   46 
   47         uint32_t                sc_num_irq;
   48         uint32_t                sc_irq_start;
   49         uint32_t                sc_irq_end;
   50 
   51         bus_addr_t              sc_mem_base;
   52         bus_addr_t              sc_mem_size;
   53 
   54         bus_addr_t              sc_io_base;
   55         bus_addr_t              sc_io_size;
   56 
   57         struct intr_event       *sc_eventstab[MTK_PCI_NIRQS];
   58 
   59         uint32_t                pcie_link_status;
   60         uint32_t                num_slots;
   61         uint32_t                socid;
   62         uint32_t                addr_mask;
   63 };
   64 
   65 #define MTK_PCI_PCICFG                  0x0000
   66 #define    MTK_PCI_RESET                        (1<<1)
   67 #define MTK_PCI_PCIINT                  0x0008
   68 #define MTK_PCI_PCIENA                  0x000C
   69 #define MTK_PCI_CFGADDR                 0x0020
   70 #define MTK_PCI_CFGDATA                 0x0024
   71 #define MTK_PCI_MEMBASE                 0x0028
   72 #define MTK_PCI_IOBASE                  0x002C
   73 #define MTK_PCI_ARBCTL                  0x0080
   74 #define MTK_PCI_PHY0_CFG                0x0090
   75 
   76 #define MTK_PCI_PCIE0_BAR0SETUP         0x2010
   77 #define MTK_PCI_PCIE0_BAR1SETUP         0x2014
   78 #define MTK_PCI_PCIE0_IMBASEBAR0        0x2018
   79 #define MTK_PCI_PCIE0_ID                0x2030
   80 #define MTK_PCI_PCIE0_CLASS             0x2034
   81 #define MTK_PCI_PCIE0_SUBID             0x2038
   82 #define MTK_PCI_PCIE0_STATUS            0x2050
   83 #define MTK_PCI_PCIE0_DLECR             0x2060
   84 #define MTK_PCI_PCIE0_ECRC              0x2064
   85 
   86 #define MTK_PCIE_BAR0SETUP(_s)          (MTK_PCI_PCIE0_BAR0SETUP + (_s)*0x1000)
   87 #define MTK_PCIE_BAR1SETUP(_s)          (MTK_PCI_PCIE0_BAR1SETUP + (_s)*0x1000)
   88 #define MTK_PCIE_IMBASEBAR0(_s)         (MTK_PCI_PCIE0_IMBASEBAR0 + (_s)*0x1000)
   89 #define MTK_PCIE_ID(_s)                 (MTK_PCI_PCIE0_ID + (_s)*0x1000)
   90 #define MTK_PCIE_CLASS(_s)              (MTK_PCI_PCIE0_CLASS + (_s)*0x1000)
   91 #define MTK_PCIE_SUBID(_s)              (MTK_PCI_PCIE0_SUBID + (_s)*0x1000)
   92 #define MTK_PCIE_STATUS(_s)             (MTK_PCI_PCIE0_STATUS + (_s)*0x1000)
   93 
   94 #define MTK_PCIE0_IRQ                   20
   95 #define MTK_PCIE1_IRQ                   21
   96 #define MTK_PCIE2_IRQ                   22
   97 
   98 #define MTK_PCI_INTR_PIN                2
   99 
  100 /* Chip specific defines */
  101 #define MT7620_MAX_RETRIES      10
  102 #define MT7620_PCIE_PHY_CFG     0x90
  103 #define    PHY_BUSY                     (1<<31)
  104 #define    PHY_MODE_WRITE               (1<<23)
  105 #define    PHY_ADDR_OFFSET              8
  106 #define MT7620_PPLL_CFG0        0x98
  107 #define    PPLL_SW_SET                  (1<<31)
  108 #define MT7620_PPLL_CFG1        0x9c
  109 #define    PPLL_PD                      (1<<26)
  110 #define    PPLL_LOCKED                  (1<<23)
  111 #define MT7620_PPLL_DRV         0xa0
  112 #define   PDRV_SW_SET                   (1<<31)
  113 #define   LC_CKDRVPD                    (1<<19)
  114 #define   LC_CKDRVOHZ                   (1<<18)
  115 #define   LC_CKDRVHZ                    (1<<17)
  116 #define MT7620_PERST_GPIO_MODE  (3<<16)
  117 #define   MT7620_PERST                  (0<<16)
  118 #define   MT7620_GPIO                   (2<<16)
  119 #define MT7620_PKG_BGA          (1<<16)
  120 
  121 #define MT7628_PERST_GPIO_MODE  (1<<16)
  122 #define   MT7628_PERST                  (0<<16)
  123 
  124 #define MT7621_PERST_GPIO_MODE  (3<<10)
  125 #define   MT7621_PERST_GPIO             (1<<10)
  126 #define MT7621_UARTL3_GPIO_MODE (3<<3)
  127 #define   MT7621_UARTL3_GPIO            (1<<3)
  128 #define MT7621_PCIE0_RST        (1<<19)
  129 #define MT7621_PCIE1_RST        (1<<8)
  130 #define MT7621_PCIE2_RST        (1<<7)
  131 #define MT7621_PCIE_RST         (MT7621_PCIE0_RST | MT7621_PCIE1_RST | \
  132                                  MT7621_PCIE2_RST)
  133 
  134 #define RT3883_PCI_RST          (1<<24)
  135 #define RT3883_PCI_CLK          (1<<19)
  136 #define RT3883_PCI_HOST_MODE    (1<<7)
  137 #define RT3883_PCIE_RC_MODE     (1<<8)
  138 /* End of chip specific defines */
  139 
  140 #define MT_WRITE32(sc, off, val) \
  141         bus_write_4((sc)->pci_res[0], (off), (val))
  142 #define MT_WRITE16(sc, off, val) \
  143         bus_write_2((sc)->pci_res[0], (off), (val))
  144 #define MT_WRITE8(sc, off, val) \
  145         bus_write_1((sc)->pci_res[0], (off), (val))
  146 #define MT_READ32(sc, off) \
  147         bus_read_4((sc)->pci_res[0], (off))
  148 #define MT_READ16(sc, off) \
  149         bus_read_2((sc)->pci_res[0], (off))
  150 #define MT_READ8(sc, off) \
  151         bus_read_1((sc)->pci_res[0], (off))
  152 
  153 #define MT_CLR_SET32(sc, off, clr, set) \
  154         MT_WRITE32((sc), (off), ((MT_READ32((sc), (off)) & ~(clr)) | (off)))
  155 
  156 #endif /* __MTK_PCIE_H__ */

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