Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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FreeBSD/Linux Kernel Cross Reference
sys/mips/mediatek/mtk_xhci.c
Version:
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1 #include <sys/cdefs.h> 2 __FBSDID("$FreeBSD: releng/12.0/sys/mips/mediatek/mtk_xhci.c 307518 2016-10-17 10:20:38Z hselasky $"); 3 4 /*- 5 * Copyright (c) 2015 Stanislav Galabov. All rights reserved. 6 * Copyright (c) 2010,2011 Aleksandr Rybalko. All rights reserved. 7 * Copyright (c) 2007-2008 Hans Petter Selasky. All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 */ 30 31 #include <sys/stdint.h> 32 #include <sys/stddef.h> 33 #include <sys/param.h> 34 #include <sys/queue.h> 35 #include <sys/types.h> 36 #include <sys/systm.h> 37 #include <sys/kernel.h> 38 #include <sys/bus.h> 39 #include <sys/module.h> 40 #include <sys/lock.h> 41 #include <sys/mutex.h> 42 #include <sys/condvar.h> 43 #include <sys/sysctl.h> 44 #include <sys/sx.h> 45 #include <sys/unistd.h> 46 #include <sys/callout.h> 47 #include <sys/malloc.h> 48 #include <sys/priv.h> 49 #include <sys/rman.h> 50 51 #include <dev/usb/usb.h> 52 #include <dev/usb/usbdi.h> 53 54 #include <dev/usb/usb_core.h> 55 #include <dev/usb/usb_busdma.h> 56 #include <dev/usb/usb_process.h> 57 #include <dev/usb/usb_util.h> 58 59 #include <dev/usb/usb_controller.h> 60 #include <dev/usb/usb_bus.h> 61 62 #include <dev/usb/controller/xhci.h> 63 64 #include <dev/ofw/openfirm.h> 65 #include <dev/ofw/ofw_bus.h> 66 #include <dev/ofw/ofw_bus_subr.h> 67 68 #define XHCI_HC_DEVSTR "MTK USB 3.0 controller" 69 70 static device_probe_t mtk_xhci_fdt_probe; 71 static device_attach_t mtk_xhci_fdt_attach; 72 static device_detach_t mtk_xhci_fdt_detach; 73 74 static void mtk_xhci_fdt_init(device_t dev); 75 76 static int 77 mtk_xhci_fdt_probe(device_t self) 78 { 79 80 if (!ofw_bus_status_okay(self)) 81 return (ENXIO); 82 83 if (!ofw_bus_is_compatible(self, "mediatek,mt8173-xhci")) 84 return (ENXIO); 85 86 device_set_desc(self, XHCI_HC_DEVSTR); 87 88 return (BUS_PROBE_DEFAULT); 89 } 90 91 static int 92 mtk_xhci_fdt_attach(device_t self) 93 { 94 struct xhci_softc *sc = device_get_softc(self); 95 int err; 96 int rid; 97 98 /* initialise some bus fields */ 99 sc->sc_bus.parent = self; 100 sc->sc_bus.devices = sc->sc_devices; 101 sc->sc_bus.devices_max = XHCI_MAX_DEVICES; 102 103 rid = 0; 104 sc->sc_io_res = bus_alloc_resource_any(self, SYS_RES_MEMORY, &rid, 105 RF_ACTIVE); 106 if (!sc->sc_io_res) { 107 device_printf(self, "Could not map memory\n"); 108 goto error; 109 } 110 sc->sc_io_tag = rman_get_bustag(sc->sc_io_res); 111 sc->sc_io_hdl = rman_get_bushandle(sc->sc_io_res); 112 sc->sc_io_size = rman_get_size(sc->sc_io_res); 113 114 mtk_xhci_fdt_init(self); 115 116 rid = 0; 117 sc->sc_irq_res = bus_alloc_resource_any(self, SYS_RES_IRQ, &rid, 118 RF_SHAREABLE | RF_ACTIVE); 119 if (sc->sc_irq_res == NULL) { 120 device_printf(self, "Could not allocate irq\n"); 121 goto error; 122 } 123 124 sc->sc_bus.bdev = device_add_child(self, "usbus", -1); 125 if (!(sc->sc_bus.bdev)) { 126 device_printf(self, "Could not add USB device\n"); 127 goto error; 128 } 129 device_set_ivars(sc->sc_bus.bdev, &sc->sc_bus); 130 device_set_desc(sc->sc_bus.bdev, XHCI_HC_DEVSTR); 131 132 sprintf(sc->sc_vendor, "Mediatek"); 133 134 err = bus_setup_intr(self, sc->sc_irq_res, INTR_TYPE_BIO | INTR_MPSAFE, 135 NULL, (driver_intr_t *)xhci_interrupt, sc, &sc->sc_intr_hdl); 136 if (err) { 137 device_printf(self, "Could not setup irq, %d\n", err); 138 sc->sc_intr_hdl = NULL; 139 goto error; 140 } 141 142 err = xhci_init(sc, self, 1); 143 if (err == 0) 144 err = xhci_halt_controller(sc); 145 if (err == 0) 146 err = xhci_start_controller(sc); 147 if (err == 0) 148 err = device_probe_and_attach(sc->sc_bus.bdev); 149 if (err) { 150 device_printf(self, "USB init failed err=%d\n", err); 151 goto error; 152 } 153 return (0); 154 155 error: 156 mtk_xhci_fdt_detach(self); 157 return (ENXIO); 158 } 159 160 static int 161 mtk_xhci_fdt_detach(device_t self) 162 { 163 struct xhci_softc *sc = device_get_softc(self); 164 int err; 165 166 /* during module unload there are lots of children leftover */ 167 device_delete_children(self); 168 169 if (sc->sc_irq_res && sc->sc_intr_hdl) { 170 /* 171 * only call xhci_detach() after xhci_init() 172 */ 173 xhci_uninit(sc); 174 175 err = bus_teardown_intr(self, sc->sc_irq_res, sc->sc_intr_hdl); 176 if (err) 177 device_printf(self, "Could not tear down irq, %d\n", 178 err); 179 sc->sc_intr_hdl = NULL; 180 } 181 if (sc->sc_irq_res) { 182 bus_release_resource(self, SYS_RES_IRQ, 0, 183 sc->sc_irq_res); 184 sc->sc_irq_res = NULL; 185 } 186 if (sc->sc_io_res) { 187 bus_release_resource(self, SYS_RES_MEMORY, 0, 188 sc->sc_io_res); 189 sc->sc_io_res = NULL; 190 } 191 192 return (0); 193 } 194 195 static device_method_t mtk_xhci_fdt_methods[] = { 196 /* Device interface */ 197 DEVMETHOD(device_probe, mtk_xhci_fdt_probe), 198 DEVMETHOD(device_attach, mtk_xhci_fdt_attach), 199 DEVMETHOD(device_detach, mtk_xhci_fdt_detach), 200 DEVMETHOD(device_suspend, bus_generic_suspend), 201 DEVMETHOD(device_resume, bus_generic_resume), 202 DEVMETHOD(device_shutdown, bus_generic_shutdown), 203 204 DEVMETHOD_END 205 }; 206 207 static driver_t mtk_xhci_fdt_driver = { 208 .name = "xhci", 209 .methods = mtk_xhci_fdt_methods, 210 .size = sizeof(struct xhci_softc), 211 }; 212 213 static devclass_t mtk_xhci_fdt_devclass; 214 215 DRIVER_MODULE(xhci, simplebus, mtk_xhci_fdt_driver, mtk_xhci_fdt_devclass, 0, 216 0); 217 218 #define USB_HDMA_CFG 0x950 219 #define USB_HDMA_CFG_MT7621_VAL 0x10E0E0C 220 221 #define U3_LTSSM_TIMING_PARAM3 0x2514 222 #define U3_LTSSM_TIMING_VAL 0x3E8012C 223 224 #define SYNC_HS_EOF 0x938 225 #define SYNC_HS_EOF_VAL 0x201F3 226 227 #define USB_IP_SPAR0 0x107C8 228 #define USB_IP_SPAR0_VAL 1 229 230 #define U2_PHY_BASE_P0 0x10800 231 #define U2_PHY_BASE_P1 0x11000 232 #define U2_PHYD_CR1 0x64 233 #define U2_PHYD_CR1_MASK (3<<18) 234 #define U2_PHYD_CR1_VAL (1<<18) 235 236 #define USB_IP_PW_CTRL 0x10700 237 #define USB_IP_PW_CTRL_1 0x10704 238 #define USB_IP_CAP 0x10724 239 #define USB_U3_CTRL(p) (0x10730 + ((p) * 0x08)) 240 #define USB_U2_CTRL(p) (0x10750 + ((p) * 0x08)) 241 242 #define USB_IP_SW_RST (1 << 0) 243 #define USB_IP_PDN (1 << 0) 244 245 #define USB_PORT_DIS (1 << 0) 246 #define USB_PORT_PDN (1 << 1) 247 248 #define U3_PORT_NUM(p) (p & 0xFF) 249 #define U2_PORT_NUM(p) ((p>>8) & 0xFF) 250 251 #define RD4(_sc, _reg) bus_read_4((_sc)->sc_io_res, (_reg)) 252 #define WR4(_sc, _reg, _val) bus_write_4((_sc)->sc_io_res, (_reg), (_val)) 253 #define CLRSET4(_sc, _reg, _clr, _set) \ 254 WR4((_sc), (_reg), (RD4((_sc), (_reg)) & ~(_clr)) | (_set)) 255 256 static void 257 mtk_xhci_fdt_init(device_t dev) 258 { 259 struct xhci_softc *sc; 260 uint32_t temp, u3_ports, u2_ports, i; 261 262 sc = device_get_softc(dev); 263 264 temp = RD4(sc, USB_IP_CAP); 265 u3_ports = U3_PORT_NUM(temp); 266 u2_ports = U2_PORT_NUM(temp); 267 268 device_printf(dev, "%d USB3 ports, %d USB2 ports\n", 269 u3_ports, u2_ports); 270 271 CLRSET4(sc, USB_IP_PW_CTRL, 0, USB_IP_SW_RST); 272 CLRSET4(sc, USB_IP_PW_CTRL, USB_IP_SW_RST, 0); 273 CLRSET4(sc, USB_IP_PW_CTRL_1, USB_IP_PDN, 0); 274 275 for (i = 0; i < u3_ports; i++) 276 CLRSET4(sc, USB_U3_CTRL(i), USB_PORT_PDN | USB_PORT_DIS, 0); 277 278 for (i = 0; i < u2_ports; i++) 279 CLRSET4(sc, USB_U2_CTRL(i), USB_PORT_PDN | USB_PORT_DIS, 0); 280 281 DELAY(100000); 282 283 WR4(sc, USB_HDMA_CFG, USB_HDMA_CFG_MT7621_VAL); 284 WR4(sc, U3_LTSSM_TIMING_PARAM3, U3_LTSSM_TIMING_VAL); 285 WR4(sc, SYNC_HS_EOF, SYNC_HS_EOF_VAL); 286 WR4(sc, USB_IP_SPAR0, USB_IP_SPAR0_VAL); 287 CLRSET4(sc, U2_PHY_BASE_P0 + U2_PHYD_CR1, U2_PHYD_CR1_MASK, 288 U2_PHYD_CR1_VAL); 289 CLRSET4(sc, U2_PHY_BASE_P1 + U2_PHYD_CR1, U2_PHYD_CR1_MASK, 290 U2_PHYD_CR1_VAL); 291 }
Cache object: b49c8613f4ea52e94823cd1b1d6a3c63
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