Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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FreeBSD/Linux Kernel Cross Reference
sys/mips/mips/cache.c
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1 /* $NetBSD: cache.c,v 1.33 2005/12/24 23:24:01 perry Exp $ */ 2 3 /*- 4 * Copyright 2001, 2002 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Jason R. Thorpe and Simon Burge for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 /*- 39 * Copyright 2000, 2001 40 * Broadcom Corporation. All rights reserved. 41 * 42 * This software is furnished under license and may be used and copied only 43 * in accordance with the following terms and conditions. Subject to these 44 * conditions, you may download, copy, install, use, modify and distribute 45 * modified or unmodified copies of this software in source and/or binary 46 * form. No title or ownership is transferred hereby. 47 * 48 * 1) Any source code used, modified or distributed must reproduce and 49 * retain this copyright notice and list of conditions as they appear in 50 * the source file. 51 * 52 * 2) No right is granted to use any trade name, trademark, or logo of 53 * Broadcom Corporation. The "Broadcom Corporation" name may not be 54 * used to endorse or promote products derived from this software 55 * without the prior written permission of Broadcom Corporation. 56 * 57 * 3) THIS SOFTWARE IS PROVIDED "AS-IS" AND ANY EXPRESS OR IMPLIED 58 * WARRANTIES, INCLUDING BUT NOT LIMITED TO, ANY IMPLIED WARRANTIES OF 59 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR 60 * NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM BE LIABLE 61 * FOR ANY DAMAGES WHATSOEVER, AND IN PARTICULAR, BROADCOM SHALL NOT BE 62 * LIABLE FOR DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 63 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 64 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 65 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 66 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE 67 * OR OTHERWISE), EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 68 */ 69 70 #include <sys/cdefs.h> 71 __FBSDID("$FreeBSD: releng/11.0/sys/mips/mips/cache.c 280691 2015-03-26 14:51:24Z br $"); 72 73 #include <sys/types.h> 74 #include <sys/systm.h> 75 76 #include <machine/cpuinfo.h> 77 #include <machine/cache.h> 78 79 struct mips_cache_ops mips_cache_ops; 80 81 #if defined(MIPS_DISABLE_L1_CACHE) || defined(CPU_RMI) || defined(CPU_NLM) 82 static void 83 cache_noop(vm_offset_t va, vm_size_t size) 84 { 85 } 86 #endif 87 88 void 89 mips_config_cache(struct mips_cpuinfo * cpuinfo) 90 { 91 92 switch (cpuinfo->l1.ic_linesize) { 93 case 16: 94 mips_cache_ops.mco_icache_sync_all = mipsNN_icache_sync_all_16; 95 mips_cache_ops.mco_icache_sync_range = 96 mipsNN_icache_sync_range_16; 97 mips_cache_ops.mco_icache_sync_range_index = 98 mipsNN_icache_sync_range_index_16; 99 break; 100 case 32: 101 mips_cache_ops.mco_icache_sync_all = mipsNN_icache_sync_all_32; 102 mips_cache_ops.mco_icache_sync_range = 103 mipsNN_icache_sync_range_32; 104 mips_cache_ops.mco_icache_sync_range_index = 105 mipsNN_icache_sync_range_index_32; 106 break; 107 case 64: 108 mips_cache_ops.mco_icache_sync_all = mipsNN_icache_sync_all_64; 109 mips_cache_ops.mco_icache_sync_range = 110 mipsNN_icache_sync_range_64; 111 mips_cache_ops.mco_icache_sync_range_index = 112 mipsNN_icache_sync_range_index_64; 113 break; 114 case 128: 115 mips_cache_ops.mco_icache_sync_all = mipsNN_icache_sync_all_128; 116 mips_cache_ops.mco_icache_sync_range = 117 mipsNN_icache_sync_range_128; 118 mips_cache_ops.mco_icache_sync_range_index = 119 mipsNN_icache_sync_range_index_128; 120 break; 121 122 #ifdef MIPS_DISABLE_L1_CACHE 123 case 0: 124 mips_cache_ops.mco_icache_sync_all = (void (*)(void))cache_noop; 125 mips_cache_ops.mco_icache_sync_range = cache_noop; 126 mips_cache_ops.mco_icache_sync_range_index = cache_noop; 127 break; 128 #endif 129 default: 130 panic("no Icache ops for %d byte lines", 131 cpuinfo->l1.ic_linesize); 132 } 133 134 switch (cpuinfo->l1.dc_linesize) { 135 case 16: 136 mips_cache_ops.mco_pdcache_wbinv_all = 137 mips_cache_ops.mco_intern_pdcache_wbinv_all = 138 mipsNN_pdcache_wbinv_all_16; 139 mips_cache_ops.mco_pdcache_wbinv_range = 140 mipsNN_pdcache_wbinv_range_16; 141 mips_cache_ops.mco_pdcache_wbinv_range_index = 142 mips_cache_ops.mco_intern_pdcache_wbinv_range_index = 143 mipsNN_pdcache_wbinv_range_index_16; 144 mips_cache_ops.mco_pdcache_inv_range = 145 mipsNN_pdcache_inv_range_16; 146 mips_cache_ops.mco_pdcache_wb_range = 147 mips_cache_ops.mco_intern_pdcache_wb_range = 148 mipsNN_pdcache_wb_range_16; 149 break; 150 case 32: 151 mips_cache_ops.mco_pdcache_wbinv_all = 152 mips_cache_ops.mco_intern_pdcache_wbinv_all = 153 mipsNN_pdcache_wbinv_all_32; 154 #if defined(CPU_RMI) || defined(CPU_NLM) 155 mips_cache_ops.mco_pdcache_wbinv_range = cache_noop; 156 #else 157 mips_cache_ops.mco_pdcache_wbinv_range = 158 mipsNN_pdcache_wbinv_range_32; 159 #endif 160 #if defined(CPU_RMI) || defined(CPU_NLM) 161 mips_cache_ops.mco_pdcache_wbinv_range_index = 162 mips_cache_ops.mco_intern_pdcache_wbinv_range_index = cache_noop; 163 mips_cache_ops.mco_pdcache_inv_range = cache_noop; 164 #else 165 mips_cache_ops.mco_pdcache_wbinv_range_index = 166 mips_cache_ops.mco_intern_pdcache_wbinv_range_index = 167 mipsNN_pdcache_wbinv_range_index_32; 168 mips_cache_ops.mco_pdcache_inv_range = 169 mipsNN_pdcache_inv_range_32; 170 #endif 171 #if defined(CPU_RMI) || defined(CPU_NLM) 172 mips_cache_ops.mco_pdcache_wb_range = 173 mips_cache_ops.mco_intern_pdcache_wb_range = cache_noop; 174 #else 175 mips_cache_ops.mco_pdcache_wb_range = 176 mips_cache_ops.mco_intern_pdcache_wb_range = 177 mipsNN_pdcache_wb_range_32; 178 #endif 179 break; 180 case 64: 181 mips_cache_ops.mco_pdcache_wbinv_all = 182 mips_cache_ops.mco_intern_pdcache_wbinv_all = 183 mipsNN_pdcache_wbinv_all_64; 184 mips_cache_ops.mco_pdcache_wbinv_range = 185 mipsNN_pdcache_wbinv_range_64; 186 mips_cache_ops.mco_pdcache_wbinv_range_index = 187 mips_cache_ops.mco_intern_pdcache_wbinv_range_index = 188 mipsNN_pdcache_wbinv_range_index_64; 189 mips_cache_ops.mco_pdcache_inv_range = 190 mipsNN_pdcache_inv_range_64; 191 mips_cache_ops.mco_pdcache_wb_range = 192 mips_cache_ops.mco_intern_pdcache_wb_range = 193 mipsNN_pdcache_wb_range_64; 194 break; 195 case 128: 196 mips_cache_ops.mco_pdcache_wbinv_all = 197 mips_cache_ops.mco_intern_pdcache_wbinv_all = 198 mipsNN_pdcache_wbinv_all_128; 199 mips_cache_ops.mco_pdcache_wbinv_range = 200 mipsNN_pdcache_wbinv_range_128; 201 mips_cache_ops.mco_pdcache_wbinv_range_index = 202 mips_cache_ops.mco_intern_pdcache_wbinv_range_index = 203 mipsNN_pdcache_wbinv_range_index_128; 204 mips_cache_ops.mco_pdcache_inv_range = 205 mipsNN_pdcache_inv_range_128; 206 mips_cache_ops.mco_pdcache_wb_range = 207 mips_cache_ops.mco_intern_pdcache_wb_range = 208 mipsNN_pdcache_wb_range_128; 209 break; 210 #ifdef MIPS_DISABLE_L1_CACHE 211 case 0: 212 mips_cache_ops.mco_pdcache_wbinv_all = 213 mips_cache_ops.mco_intern_pdcache_wbinv_all = 214 (void (*)(void))cache_noop; 215 mips_cache_ops.mco_pdcache_wbinv_range = cache_noop; 216 mips_cache_ops.mco_pdcache_wbinv_range_index = cache_noop; 217 mips_cache_ops.mco_intern_pdcache_wbinv_range_index = 218 cache_noop; 219 mips_cache_ops.mco_pdcache_inv_range = cache_noop; 220 mips_cache_ops.mco_pdcache_wb_range = cache_noop; 221 mips_cache_ops.mco_intern_pdcache_wb_range = cache_noop; 222 break; 223 #endif 224 default: 225 panic("no Dcache ops for %d byte lines", 226 cpuinfo->l1.dc_linesize); 227 } 228 229 mipsNN_cache_init(cpuinfo); 230 231 #if 0 232 if (mips_cpu_flags & 233 (CPU_MIPS_D_CACHE_COHERENT | CPU_MIPS_I_D_CACHE_COHERENT)) { 234 #ifdef CACHE_DEBUG 235 printf(" Dcache is coherent\n"); 236 #endif 237 mips_cache_ops.mco_pdcache_wbinv_all = 238 (void (*)(void))cache_noop; 239 mips_cache_ops.mco_pdcache_wbinv_range = cache_noop; 240 mips_cache_ops.mco_pdcache_wbinv_range_index = cache_noop; 241 mips_cache_ops.mco_pdcache_inv_range = cache_noop; 242 mips_cache_ops.mco_pdcache_wb_range = cache_noop; 243 } 244 if (mips_cpu_flags & CPU_MIPS_I_D_CACHE_COHERENT) { 245 #ifdef CACHE_DEBUG 246 printf(" Icache is coherent against Dcache\n"); 247 #endif 248 mips_cache_ops.mco_intern_pdcache_wbinv_all = 249 (void (*)(void))cache_noop; 250 mips_cache_ops.mco_intern_pdcache_wbinv_range_index = 251 cache_noop; 252 mips_cache_ops.mco_intern_pdcache_wb_range = cache_noop; 253 } 254 #endif 255 256 /* Check that all cache ops are set up. */ 257 /* must have primary Icache */ 258 if (cpuinfo->l1.ic_size) { 259 260 if (!mips_cache_ops.mco_icache_sync_all) 261 panic("no icache_sync_all cache op"); 262 if (!mips_cache_ops.mco_icache_sync_range) 263 panic("no icache_sync_range cache op"); 264 if (!mips_cache_ops.mco_icache_sync_range_index) 265 panic("no icache_sync_range_index cache op"); 266 } 267 /* must have primary Dcache */ 268 if (cpuinfo->l1.dc_size) { 269 if (!mips_cache_ops.mco_pdcache_wbinv_all) 270 panic("no pdcache_wbinv_all"); 271 if (!mips_cache_ops.mco_pdcache_wbinv_range) 272 panic("no pdcache_wbinv_range"); 273 if (!mips_cache_ops.mco_pdcache_wbinv_range_index) 274 panic("no pdcache_wbinv_range_index"); 275 if (!mips_cache_ops.mco_pdcache_inv_range) 276 panic("no pdcache_inv_range"); 277 if (!mips_cache_ops.mco_pdcache_wb_range) 278 panic("no pdcache_wb_range"); 279 } 280 281 /* L2 data cache */ 282 if (!cpuinfo->l2.dc_size) { 283 /* No L2 found, ignore */ 284 return; 285 } 286 287 switch (cpuinfo->l2.dc_linesize) { 288 case 32: 289 mips_cache_ops.mco_sdcache_wbinv_all = 290 mipsNN_sdcache_wbinv_all_32; 291 mips_cache_ops.mco_sdcache_wbinv_range = 292 mipsNN_sdcache_wbinv_range_32; 293 mips_cache_ops.mco_sdcache_wbinv_range_index = 294 mipsNN_sdcache_wbinv_range_index_32; 295 mips_cache_ops.mco_sdcache_inv_range = 296 mipsNN_sdcache_inv_range_32; 297 mips_cache_ops.mco_sdcache_wb_range = 298 mipsNN_sdcache_wb_range_32; 299 break; 300 case 64: 301 mips_cache_ops.mco_sdcache_wbinv_all = 302 mipsNN_sdcache_wbinv_all_64; 303 mips_cache_ops.mco_sdcache_wbinv_range = 304 mipsNN_sdcache_wbinv_range_64; 305 mips_cache_ops.mco_sdcache_wbinv_range_index = 306 mipsNN_sdcache_wbinv_range_index_64; 307 mips_cache_ops.mco_sdcache_inv_range = 308 mipsNN_sdcache_inv_range_64; 309 mips_cache_ops.mco_sdcache_wb_range = 310 mipsNN_sdcache_wb_range_64; 311 break; 312 case 128: 313 mips_cache_ops.mco_sdcache_wbinv_all = 314 mipsNN_sdcache_wbinv_all_128; 315 mips_cache_ops.mco_sdcache_wbinv_range = 316 mipsNN_sdcache_wbinv_range_128; 317 mips_cache_ops.mco_sdcache_wbinv_range_index = 318 mipsNN_sdcache_wbinv_range_index_128; 319 mips_cache_ops.mco_sdcache_inv_range = 320 mipsNN_sdcache_inv_range_128; 321 mips_cache_ops.mco_sdcache_wb_range = 322 mipsNN_sdcache_wb_range_128; 323 break; 324 default: 325 #ifdef CACHE_DEBUG 326 printf(" no sdcache ops for %d byte lines", 327 cpuinfo->l2.dc_linesize); 328 #endif 329 break; 330 } 331 }
Cache object: 7e8eae99384f15bdca3c60c32aa21f59
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