Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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FreeBSD/Linux Kernel Cross Reference
sys/mips/mips/cache.c
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1 /* $NetBSD: cache.c,v 1.33 2005/12/24 23:24:01 perry Exp $ */ 2 3 /*- 4 * Copyright 2001, 2002 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Jason R. Thorpe and Simon Burge for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 /*- 39 * Copyright 2000, 2001 40 * Broadcom Corporation. All rights reserved. 41 * 42 * This software is furnished under license and may be used and copied only 43 * in accordance with the following terms and conditions. Subject to these 44 * conditions, you may download, copy, install, use, modify and distribute 45 * modified or unmodified copies of this software in source and/or binary 46 * form. No title or ownership is transferred hereby. 47 * 48 * 1) Any source code used, modified or distributed must reproduce and 49 * retain this copyright notice and list of conditions as they appear in 50 * the source file. 51 * 52 * 2) No right is granted to use any trade name, trademark, or logo of 53 * Broadcom Corporation. The "Broadcom Corporation" name may not be 54 * used to endorse or promote products derived from this software 55 * without the prior written permission of Broadcom Corporation. 56 * 57 * 3) THIS SOFTWARE IS PROVIDED "AS-IS" AND ANY EXPRESS OR IMPLIED 58 * WARRANTIES, INCLUDING BUT NOT LIMITED TO, ANY IMPLIED WARRANTIES OF 59 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR 60 * NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM BE LIABLE 61 * FOR ANY DAMAGES WHATSOEVER, AND IN PARTICULAR, BROADCOM SHALL NOT BE 62 * LIABLE FOR DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 63 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 64 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 65 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 66 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE 67 * OR OTHERWISE), EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 68 */ 69 70 #include <sys/cdefs.h> 71 __FBSDID("$FreeBSD: releng/8.0/sys/mips/mips/cache.c 178218 2008-04-15 05:35:00Z imp $"); 72 73 #include <sys/types.h> 74 #include <sys/systm.h> 75 76 #include <machine/cpuinfo.h> 77 #include <machine/cache.h> 78 79 struct mips_cache_ops mips_cache_ops; 80 81 void 82 mips_config_cache(struct mips_cpuinfo * cpuinfo) 83 { 84 switch (cpuinfo->l1.ic_linesize) { 85 case 16: 86 mips_cache_ops.mco_icache_sync_all = mipsNN_icache_sync_all_16; 87 mips_cache_ops.mco_icache_sync_range = 88 mipsNN_icache_sync_range_16; 89 mips_cache_ops.mco_icache_sync_range_index = 90 mipsNN_icache_sync_range_index_16; 91 break; 92 case 32: 93 mips_cache_ops.mco_icache_sync_all = mipsNN_icache_sync_all_32; 94 mips_cache_ops.mco_icache_sync_range = 95 mipsNN_icache_sync_range_32; 96 mips_cache_ops.mco_icache_sync_range_index = 97 mipsNN_icache_sync_range_index_32; 98 break; 99 #ifdef TARGET_OCTEON 100 case 128: 101 mips_cache_ops.mco_icache_sync_all = mipsNN_icache_sync_all_128; 102 mips_cache_ops.mco_icache_sync_range = 103 mipsNN_icache_sync_range_128; 104 mips_cache_ops.mco_icache_sync_range_index = 105 mipsNN_icache_sync_range_index_128; 106 break; 107 #endif 108 109 #ifdef MIPS_DISABLE_L1_CACHE 110 case 0: 111 mips_cache_ops.mco_icache_sync_all = cache_noop; 112 mips_cache_ops.mco_icache_sync_range = 113 (void (*)(vaddr_t, vsize_t))cache_noop; 114 mips_cache_ops.mco_icache_sync_range_index = 115 (void (*)(vaddr_t, vsize_t))cache_noop; 116 break; 117 #endif 118 default: 119 panic("no Icache ops for %d byte lines", 120 cpuinfo->l1.ic_linesize); 121 } 122 123 switch (cpuinfo->l1.dc_linesize) { 124 case 16: 125 mips_cache_ops.mco_pdcache_wbinv_all = 126 mips_cache_ops.mco_intern_pdcache_wbinv_all = 127 mipsNN_pdcache_wbinv_all_16; 128 mips_cache_ops.mco_pdcache_wbinv_range = 129 mipsNN_pdcache_wbinv_range_16; 130 mips_cache_ops.mco_pdcache_wbinv_range_index = 131 mips_cache_ops.mco_intern_pdcache_wbinv_range_index = 132 mipsNN_pdcache_wbinv_range_index_16; 133 mips_cache_ops.mco_pdcache_inv_range = 134 mipsNN_pdcache_inv_range_16; 135 mips_cache_ops.mco_pdcache_wb_range = 136 mips_cache_ops.mco_intern_pdcache_wb_range = 137 mipsNN_pdcache_wb_range_16; 138 break; 139 case 32: 140 mips_cache_ops.mco_pdcache_wbinv_all = 141 mips_cache_ops.mco_intern_pdcache_wbinv_all = 142 mipsNN_pdcache_wbinv_all_32; 143 mips_cache_ops.mco_pdcache_wbinv_range = 144 mipsNN_pdcache_wbinv_range_32; 145 mips_cache_ops.mco_pdcache_wbinv_range_index = 146 mips_cache_ops.mco_intern_pdcache_wbinv_range_index = 147 mipsNN_pdcache_wbinv_range_index_32; 148 mips_cache_ops.mco_pdcache_inv_range = 149 mipsNN_pdcache_inv_range_32; 150 mips_cache_ops.mco_pdcache_wb_range = 151 mips_cache_ops.mco_intern_pdcache_wb_range = 152 mipsNN_pdcache_wb_range_32; 153 break; 154 #ifdef TARGET_OCTEON 155 case 128: 156 mips_cache_ops.mco_pdcache_wbinv_all = 157 mips_cache_ops.mco_intern_pdcache_wbinv_all = 158 mipsNN_pdcache_wbinv_all_128; 159 mips_cache_ops.mco_pdcache_wbinv_range = 160 mipsNN_pdcache_wbinv_range_128; 161 mips_cache_ops.mco_pdcache_wbinv_range_index = 162 mips_cache_ops.mco_intern_pdcache_wbinv_range_index = 163 mipsNN_pdcache_wbinv_range_index_128; 164 mips_cache_ops.mco_pdcache_inv_range = 165 mipsNN_pdcache_inv_range_128; 166 mips_cache_ops.mco_pdcache_wb_range = 167 mips_cache_ops.mco_intern_pdcache_wb_range = 168 mipsNN_pdcache_wb_range_128; 169 break; 170 #endif 171 #ifdef MIPS_DISABLE_L1_CACHE 172 case 0: 173 mips_cache_ops.mco_pdcache_wbinv_all = cache_noop; 174 mips_cache_ops.mco_intern_pdcache_wbinv_all = cache_noop; 175 mips_cache_ops.mco_pdcache_wbinv_range = 176 (void (*)(vaddr_t, vsize_t))cache_noop; 177 mips_cache_ops.mco_pdcache_wbinv_range_index = 178 (void (*)(vaddr_t, vsize_t))cache_noop; 179 mips_cache_ops.mco_intern_pdcache_wbinv_range_index = 180 (void (*)(vaddr_t, vsize_t))cache_noop; 181 mips_cache_ops.mco_pdcache_inv_range = 182 (void (*)(vaddr_t, vsize_t))cache_noop; 183 mips_cache_ops.mco_pdcache_wb_range = 184 (void (*)(vaddr_t, vsize_t))cache_noop; 185 mips_cache_ops.mco_intern_pdcache_wb_range = 186 (void (*)(vaddr_t, vsize_t))cache_noop; 187 break; 188 #endif 189 default: 190 panic("no Dcache ops for %d byte lines", 191 cpuinfo->l1.dc_linesize); 192 } 193 194 mipsNN_cache_init(cpuinfo); 195 196 #if 0 197 if (mips_cpu_flags & 198 (CPU_MIPS_D_CACHE_COHERENT | CPU_MIPS_I_D_CACHE_COHERENT)) { 199 #ifdef CACHE_DEBUG 200 printf(" Dcache is coherent\n"); 201 #endif 202 mips_cache_ops.mco_pdcache_wbinv_all = cache_noop; 203 mips_cache_ops.mco_pdcache_wbinv_range = 204 (void (*)(vaddr_t, vsize_t))cache_noop; 205 mips_cache_ops.mco_pdcache_wbinv_range_index = 206 (void (*)(vaddr_t, vsize_t))cache_noop; 207 mips_cache_ops.mco_pdcache_inv_range = 208 (void (*)(vaddr_t, vsize_t))cache_noop; 209 mips_cache_ops.mco_pdcache_wb_range = 210 (void (*)(vaddr_t, vsize_t))cache_noop; 211 } 212 if (mips_cpu_flags & CPU_MIPS_I_D_CACHE_COHERENT) { 213 #ifdef CACHE_DEBUG 214 printf(" Icache is coherent against Dcache\n"); 215 #endif 216 mips_cache_ops.mco_intern_pdcache_wbinv_all = 217 cache_noop; 218 mips_cache_ops.mco_intern_pdcache_wbinv_range_index = 219 (void (*)(vaddr_t, vsize_t))cache_noop; 220 mips_cache_ops.mco_intern_pdcache_wb_range = 221 (void (*)(vaddr_t, vsize_t))cache_noop; 222 } 223 #endif 224 225 /* Check that all cache ops are set up. */ 226 if (mips_picache_size || 1) { /* XXX- must have primary Icache */ 227 if (!mips_cache_ops.mco_icache_sync_all) 228 panic("no icache_sync_all cache op"); 229 if (!mips_cache_ops.mco_icache_sync_range) 230 panic("no icache_sync_range cache op"); 231 if (!mips_cache_ops.mco_icache_sync_range_index) 232 panic("no icache_sync_range_index cache op"); 233 } 234 if (mips_pdcache_size || 1) { /* XXX- must have primary Icache */ 235 if (!mips_cache_ops.mco_pdcache_wbinv_all) 236 panic("no pdcache_wbinv_all"); 237 if (!mips_cache_ops.mco_pdcache_wbinv_range) 238 panic("no pdcache_wbinv_range"); 239 if (!mips_cache_ops.mco_pdcache_wbinv_range_index) 240 panic("no pdcache_wbinv_range_index"); 241 if (!mips_cache_ops.mco_pdcache_inv_range) 242 panic("no pdcache_inv_range"); 243 if (!mips_cache_ops.mco_pdcache_wb_range) 244 panic("no pdcache_wb_range"); 245 } 246 247 /* XXXMIPS: No secondary cache handlers yet */ 248 #ifdef notyet 249 if (mips_sdcache_size) { 250 if (!mips_cache_ops.mco_sdcache_wbinv_all) 251 panic("no sdcache_wbinv_all"); 252 if (!mips_cache_ops.mco_sdcache_wbinv_range) 253 panic("no sdcache_wbinv_range"); 254 if (!mips_cache_ops.mco_sdcache_wbinv_range_index) 255 panic("no sdcache_wbinv_range_index"); 256 if (!mips_cache_ops.mco_sdcache_inv_range) 257 panic("no sdcache_inv_range"); 258 if (!mips_cache_ops.mco_sdcache_wb_range) 259 panic("no sdcache_wb_range"); 260 } 261 #endif 262 }
Cache object: cfc49af9723737d594e5cf2f744721e7
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