The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


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FreeBSD/Linux Kernel Cross Reference
sys/mips/mips/cache.c

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    1 /*      $NetBSD: cache.c,v 1.33 2005/12/24 23:24:01 perry Exp $ */
    2 
    3 /*-
    4  * Copyright 2001, 2002 Wasabi Systems, Inc.
    5  * All rights reserved.
    6  *
    7  * Written by Jason R. Thorpe and Simon Burge for Wasabi Systems, Inc.
    8  *
    9  * Redistribution and use in source and binary forms, with or without
   10  * modification, are permitted provided that the following conditions
   11  * are met:
   12  * 1. Redistributions of source code must retain the above copyright
   13  *    notice, this list of conditions and the following disclaimer.
   14  * 2. Redistributions in binary form must reproduce the above copyright
   15  *    notice, this list of conditions and the following disclaimer in the
   16  *    documentation and/or other materials provided with the distribution.
   17  * 3. All advertising materials mentioning features or use of this software
   18  *    must display the following acknowledgement:
   19  *      This product includes software developed for the NetBSD Project by
   20  *      Wasabi Systems, Inc.
   21  * 4. The name of Wasabi Systems, Inc. may not be used to endorse
   22  *    or promote products derived from this software without specific prior
   23  *    written permission.
   24  *
   25  * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
   26  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
   27  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
   28  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL WASABI SYSTEMS, INC
   29  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
   30  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
   31  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
   32  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
   33  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
   34  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
   35  * POSSIBILITY OF SUCH DAMAGE.
   36  */
   37 
   38 /*-
   39  * Copyright 2000, 2001
   40  * Broadcom Corporation. All rights reserved.
   41  * 
   42  * This software is furnished under license and may be used and copied only
   43  * in accordance with the following terms and conditions.  Subject to these
   44  * conditions, you may download, copy, install, use, modify and distribute
   45  * modified or unmodified copies of this software in source and/or binary
   46  * form. No title or ownership is transferred hereby.
   47  * 
   48  * 1) Any source code used, modified or distributed must reproduce and
   49  *    retain this copyright notice and list of conditions as they appear in
   50  *    the source file.
   51  * 
   52  * 2) No right is granted to use any trade name, trademark, or logo of
   53  *    Broadcom Corporation.  The "Broadcom Corporation" name may not be
   54  *    used to endorse or promote products derived from this software
   55  *    without the prior written permission of Broadcom Corporation.
   56  *
   57  * 3) THIS SOFTWARE IS PROVIDED "AS-IS" AND ANY EXPRESS OR IMPLIED
   58  *    WARRANTIES, INCLUDING BUT NOT LIMITED TO, ANY IMPLIED WARRANTIES OF
   59  *    MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR
   60  *    NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM BE LIABLE
   61  *    FOR ANY DAMAGES WHATSOEVER, AND IN PARTICULAR, BROADCOM SHALL NOT BE
   62  *    LIABLE FOR DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
   63  *    CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
   64  *    SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
   65  *    BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
   66  *    WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
   67  *    OR OTHERWISE), EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
   68  */
   69 
   70 #include <sys/cdefs.h>
   71 __FBSDID("$FreeBSD: releng/8.4/sys/mips/mips/cache.c 215938 2010-11-27 12:26:40Z jchandra $");
   72 
   73 #include <sys/types.h>
   74 #include <sys/systm.h>
   75 
   76 #include "opt_cputype.h"
   77 
   78 #include <machine/cpuinfo.h>
   79 #include <machine/cache.h>
   80 
   81 struct mips_cache_ops mips_cache_ops;
   82 
   83 void
   84 mips_config_cache(struct mips_cpuinfo * cpuinfo)
   85 {
   86 
   87         switch (cpuinfo->l1.ic_linesize) {
   88         case 16:
   89                 mips_cache_ops.mco_icache_sync_all = mipsNN_icache_sync_all_16;
   90                 mips_cache_ops.mco_icache_sync_range =
   91                     mipsNN_icache_sync_range_16;
   92                 mips_cache_ops.mco_icache_sync_range_index =
   93                     mipsNN_icache_sync_range_index_16;
   94                 break;
   95         case 32:
   96                 mips_cache_ops.mco_icache_sync_all = mipsNN_icache_sync_all_32;
   97                 mips_cache_ops.mco_icache_sync_range =
   98                     mipsNN_icache_sync_range_32;
   99                 mips_cache_ops.mco_icache_sync_range_index =
  100                     mipsNN_icache_sync_range_index_32;
  101                 break;
  102 #ifdef CPU_CNMIPS
  103         case 128:
  104                 mips_cache_ops.mco_icache_sync_all = mipsNN_icache_sync_all_128;
  105                 mips_cache_ops.mco_icache_sync_range =
  106                     mipsNN_icache_sync_range_128;
  107                 mips_cache_ops.mco_icache_sync_range_index =
  108                     mipsNN_icache_sync_range_index_128;
  109                 break;
  110 #endif
  111 
  112 #ifdef MIPS_DISABLE_L1_CACHE
  113         case 0:
  114                 mips_cache_ops.mco_icache_sync_all = cache_noop;
  115                 mips_cache_ops.mco_icache_sync_range =
  116                     (void (*)(vaddr_t, vsize_t))cache_noop;
  117                 mips_cache_ops.mco_icache_sync_range_index =
  118                     (void (*)(vaddr_t, vsize_t))cache_noop;
  119                 break;
  120 #endif
  121         default:
  122                 panic("no Icache ops for %d byte lines",
  123                     cpuinfo->l1.ic_linesize);
  124         }
  125 
  126         switch (cpuinfo->l1.dc_linesize) {
  127         case 16:
  128                 mips_cache_ops.mco_pdcache_wbinv_all =
  129                     mips_cache_ops.mco_intern_pdcache_wbinv_all =
  130                     mipsNN_pdcache_wbinv_all_16;
  131                 mips_cache_ops.mco_pdcache_wbinv_range =
  132                     mipsNN_pdcache_wbinv_range_16;
  133                 mips_cache_ops.mco_pdcache_wbinv_range_index =
  134                     mips_cache_ops.mco_intern_pdcache_wbinv_range_index =
  135                     mipsNN_pdcache_wbinv_range_index_16;
  136                 mips_cache_ops.mco_pdcache_inv_range =
  137                     mipsNN_pdcache_inv_range_16;
  138                 mips_cache_ops.mco_pdcache_wb_range =
  139                     mips_cache_ops.mco_intern_pdcache_wb_range =
  140                     mipsNN_pdcache_wb_range_16;
  141                 break;
  142         case 32:
  143                 mips_cache_ops.mco_pdcache_wbinv_all =
  144                     mips_cache_ops.mco_intern_pdcache_wbinv_all =
  145                     mipsNN_pdcache_wbinv_all_32;
  146                 mips_cache_ops.mco_pdcache_wbinv_range =
  147                     mipsNN_pdcache_wbinv_range_32;
  148                 mips_cache_ops.mco_pdcache_wbinv_range_index =
  149                     mips_cache_ops.mco_intern_pdcache_wbinv_range_index =
  150                     mipsNN_pdcache_wbinv_range_index_32;
  151                 mips_cache_ops.mco_pdcache_inv_range =
  152                     mipsNN_pdcache_inv_range_32;
  153                 mips_cache_ops.mco_pdcache_wb_range =
  154                     mips_cache_ops.mco_intern_pdcache_wb_range =
  155                     mipsNN_pdcache_wb_range_32;
  156                 break;
  157 #ifdef CPU_CNMIPS
  158         case 128:
  159                 mips_cache_ops.mco_pdcache_wbinv_all =
  160                     mips_cache_ops.mco_intern_pdcache_wbinv_all =
  161                     mipsNN_pdcache_wbinv_all_128;
  162                 mips_cache_ops.mco_pdcache_wbinv_range =
  163                     mipsNN_pdcache_wbinv_range_128;
  164                 mips_cache_ops.mco_pdcache_wbinv_range_index =
  165                     mips_cache_ops.mco_intern_pdcache_wbinv_range_index =
  166                     mipsNN_pdcache_wbinv_range_index_128;
  167                 mips_cache_ops.mco_pdcache_inv_range =
  168                     mipsNN_pdcache_inv_range_128;
  169                 mips_cache_ops.mco_pdcache_wb_range =
  170                     mips_cache_ops.mco_intern_pdcache_wb_range =
  171                     mipsNN_pdcache_wb_range_128;
  172                 break;
  173 #endif          
  174 #ifdef MIPS_DISABLE_L1_CACHE
  175         case 0:
  176                 mips_cache_ops.mco_pdcache_wbinv_all = cache_noop;
  177                 mips_cache_ops.mco_intern_pdcache_wbinv_all = cache_noop;
  178                 mips_cache_ops.mco_pdcache_wbinv_range =
  179                     (void (*)(vaddr_t, vsize_t))cache_noop;
  180                 mips_cache_ops.mco_pdcache_wbinv_range_index =
  181                     (void (*)(vaddr_t, vsize_t))cache_noop;
  182                 mips_cache_ops.mco_intern_pdcache_wbinv_range_index =
  183                     (void (*)(vaddr_t, vsize_t))cache_noop;
  184                 mips_cache_ops.mco_pdcache_inv_range =
  185                     (void (*)(vaddr_t, vsize_t))cache_noop;
  186                 mips_cache_ops.mco_pdcache_wb_range =
  187                     (void (*)(vaddr_t, vsize_t))cache_noop;
  188                 mips_cache_ops.mco_intern_pdcache_wb_range =
  189                     (void (*)(vaddr_t, vsize_t))cache_noop;
  190                 break;
  191 #endif
  192         default:
  193                 panic("no Dcache ops for %d byte lines",
  194                     cpuinfo->l1.dc_linesize);
  195         }
  196 
  197         mipsNN_cache_init(cpuinfo);
  198 
  199 #if 0
  200         if (mips_cpu_flags &
  201             (CPU_MIPS_D_CACHE_COHERENT | CPU_MIPS_I_D_CACHE_COHERENT)) {
  202 #ifdef CACHE_DEBUG
  203                 printf("  Dcache is coherent\n");
  204 #endif
  205                 mips_cache_ops.mco_pdcache_wbinv_all = cache_noop;
  206                 mips_cache_ops.mco_pdcache_wbinv_range =
  207                     (void (*)(vaddr_t, vsize_t))cache_noop;
  208                 mips_cache_ops.mco_pdcache_wbinv_range_index =
  209                     (void (*)(vaddr_t, vsize_t))cache_noop;
  210                 mips_cache_ops.mco_pdcache_inv_range =
  211                     (void (*)(vaddr_t, vsize_t))cache_noop;
  212                 mips_cache_ops.mco_pdcache_wb_range =
  213                     (void (*)(vaddr_t, vsize_t))cache_noop;
  214         }
  215         if (mips_cpu_flags & CPU_MIPS_I_D_CACHE_COHERENT) {
  216 #ifdef CACHE_DEBUG
  217                 printf("  Icache is coherent against Dcache\n");
  218 #endif
  219                 mips_cache_ops.mco_intern_pdcache_wbinv_all =
  220                     cache_noop;
  221                 mips_cache_ops.mco_intern_pdcache_wbinv_range_index =
  222                     (void (*)(vaddr_t, vsize_t))cache_noop;
  223                 mips_cache_ops.mco_intern_pdcache_wb_range =
  224                     (void (*)(vaddr_t, vsize_t))cache_noop;
  225         }
  226 #endif
  227 
  228         /* Check that all cache ops are set up. */
  229         /* must have primary Icache */
  230         if (cpuinfo->l1.ic_size) {   
  231                 
  232                 if (!mips_cache_ops.mco_icache_sync_all)
  233                         panic("no icache_sync_all cache op");
  234                 if (!mips_cache_ops.mco_icache_sync_range)
  235                         panic("no icache_sync_range cache op");
  236                 if (!mips_cache_ops.mco_icache_sync_range_index)
  237                         panic("no icache_sync_range_index cache op");
  238         }
  239         /* must have primary Dcache */
  240         if (cpuinfo->l1.dc_size) {
  241                 if (!mips_cache_ops.mco_pdcache_wbinv_all)
  242                         panic("no pdcache_wbinv_all");
  243                 if (!mips_cache_ops.mco_pdcache_wbinv_range)
  244                         panic("no pdcache_wbinv_range");
  245                 if (!mips_cache_ops.mco_pdcache_wbinv_range_index)
  246                         panic("no pdcache_wbinv_range_index");
  247                 if (!mips_cache_ops.mco_pdcache_inv_range)
  248                         panic("no pdcache_inv_range");
  249                 if (!mips_cache_ops.mco_pdcache_wb_range)
  250                         panic("no pdcache_wb_range");
  251         }
  252 
  253         /* XXXMIPS: No secondary cache handlers yet */
  254 #ifdef notyet
  255         if (mips_sdcache_size) {
  256                 if (!mips_cache_ops.mco_sdcache_wbinv_all)
  257                         panic("no sdcache_wbinv_all");
  258                 if (!mips_cache_ops.mco_sdcache_wbinv_range)
  259                         panic("no sdcache_wbinv_range");
  260                 if (!mips_cache_ops.mco_sdcache_wbinv_range_index)
  261                         panic("no sdcache_wbinv_range_index");
  262                 if (!mips_cache_ops.mco_sdcache_inv_range)
  263                         panic("no sdcache_inv_range");
  264                 if (!mips_cache_ops.mco_sdcache_wb_range)
  265                         panic("no sdcache_wb_range");
  266         }
  267 #endif
  268 }

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