Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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FreeBSD/Linux Kernel Cross Reference
sys/mips/mips/cache.c
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1 /* $NetBSD: cache.c,v 1.33 2005/12/24 23:24:01 perry Exp $ */ 2 3 /*- 4 * Copyright 2001, 2002 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Jason R. Thorpe and Simon Burge for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 /*- 39 * Copyright 2000, 2001 40 * Broadcom Corporation. All rights reserved. 41 * 42 * This software is furnished under license and may be used and copied only 43 * in accordance with the following terms and conditions. Subject to these 44 * conditions, you may download, copy, install, use, modify and distribute 45 * modified or unmodified copies of this software in source and/or binary 46 * form. No title or ownership is transferred hereby. 47 * 48 * 1) Any source code used, modified or distributed must reproduce and 49 * retain this copyright notice and list of conditions as they appear in 50 * the source file. 51 * 52 * 2) No right is granted to use any trade name, trademark, or logo of 53 * Broadcom Corporation. The "Broadcom Corporation" name may not be 54 * used to endorse or promote products derived from this software 55 * without the prior written permission of Broadcom Corporation. 56 * 57 * 3) THIS SOFTWARE IS PROVIDED "AS-IS" AND ANY EXPRESS OR IMPLIED 58 * WARRANTIES, INCLUDING BUT NOT LIMITED TO, ANY IMPLIED WARRANTIES OF 59 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR 60 * NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM BE LIABLE 61 * FOR ANY DAMAGES WHATSOEVER, AND IN PARTICULAR, BROADCOM SHALL NOT BE 62 * LIABLE FOR DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 63 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 64 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 65 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 66 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE 67 * OR OTHERWISE), EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 68 */ 69 70 #include <sys/cdefs.h> 71 __FBSDID("$FreeBSD: releng/9.0/sys/mips/mips/cache.c 224139 2011-07-17 16:50:12Z bz $"); 72 73 #include <sys/types.h> 74 #include <sys/systm.h> 75 76 #include "opt_cputype.h" 77 78 #include <machine/cpuinfo.h> 79 #include <machine/cache.h> 80 81 struct mips_cache_ops mips_cache_ops; 82 83 #if defined(MIPS_DISABLE_L1_CACHE) || defined(CPU_RMI) || defined(CPU_NLM) 84 static void 85 cache_noop(vm_offset_t va, vm_size_t size) 86 { 87 } 88 #endif 89 90 void 91 mips_config_cache(struct mips_cpuinfo * cpuinfo) 92 { 93 94 switch (cpuinfo->l1.ic_linesize) { 95 case 16: 96 mips_cache_ops.mco_icache_sync_all = mipsNN_icache_sync_all_16; 97 mips_cache_ops.mco_icache_sync_range = 98 mipsNN_icache_sync_range_16; 99 mips_cache_ops.mco_icache_sync_range_index = 100 mipsNN_icache_sync_range_index_16; 101 break; 102 case 32: 103 mips_cache_ops.mco_icache_sync_all = mipsNN_icache_sync_all_32; 104 #ifdef CPU_NLM 105 mips_cache_ops.mco_icache_sync_range = 106 mipsNN_icache_sync_range_index_32; 107 #else 108 mips_cache_ops.mco_icache_sync_range = 109 mipsNN_icache_sync_range_32; 110 #endif 111 mips_cache_ops.mco_icache_sync_range_index = 112 mipsNN_icache_sync_range_index_32; 113 break; 114 #ifdef CPU_CNMIPS 115 case 128: 116 mips_cache_ops.mco_icache_sync_all = mipsNN_icache_sync_all_128; 117 mips_cache_ops.mco_icache_sync_range = 118 mipsNN_icache_sync_range_128; 119 mips_cache_ops.mco_icache_sync_range_index = 120 mipsNN_icache_sync_range_index_128; 121 break; 122 #endif 123 124 #ifdef MIPS_DISABLE_L1_CACHE 125 case 0: 126 mips_cache_ops.mco_icache_sync_all = cache_noop; 127 mips_cache_ops.mco_icache_sync_range = 128 (void (*)(vaddr_t, vsize_t))cache_noop; 129 mips_cache_ops.mco_icache_sync_range_index = 130 (void (*)(vaddr_t, vsize_t))cache_noop; 131 break; 132 #endif 133 default: 134 panic("no Icache ops for %d byte lines", 135 cpuinfo->l1.ic_linesize); 136 } 137 138 switch (cpuinfo->l1.dc_linesize) { 139 case 16: 140 mips_cache_ops.mco_pdcache_wbinv_all = 141 mips_cache_ops.mco_intern_pdcache_wbinv_all = 142 mipsNN_pdcache_wbinv_all_16; 143 mips_cache_ops.mco_pdcache_wbinv_range = 144 mipsNN_pdcache_wbinv_range_16; 145 mips_cache_ops.mco_pdcache_wbinv_range_index = 146 mips_cache_ops.mco_intern_pdcache_wbinv_range_index = 147 mipsNN_pdcache_wbinv_range_index_16; 148 mips_cache_ops.mco_pdcache_inv_range = 149 mipsNN_pdcache_inv_range_16; 150 mips_cache_ops.mco_pdcache_wb_range = 151 mips_cache_ops.mco_intern_pdcache_wb_range = 152 mipsNN_pdcache_wb_range_16; 153 break; 154 case 32: 155 mips_cache_ops.mco_pdcache_wbinv_all = 156 mips_cache_ops.mco_intern_pdcache_wbinv_all = 157 mipsNN_pdcache_wbinv_all_32; 158 #ifdef CPU_NLM 159 mips_cache_ops.mco_pdcache_wbinv_range = 160 mipsNN_pdcache_wbinv_range_index_32; 161 #else 162 mips_cache_ops.mco_pdcache_wbinv_range = 163 mipsNN_pdcache_wbinv_range_32; 164 #endif 165 mips_cache_ops.mco_pdcache_wbinv_range_index = 166 mips_cache_ops.mco_intern_pdcache_wbinv_range_index = 167 mipsNN_pdcache_wbinv_range_index_32; 168 mips_cache_ops.mco_pdcache_inv_range = 169 mipsNN_pdcache_inv_range_32; 170 #if defined(CPU_RMI) || defined(CPU_NLM) 171 mips_cache_ops.mco_pdcache_wb_range = 172 mips_cache_ops.mco_intern_pdcache_wb_range = cache_noop; 173 #else 174 mips_cache_ops.mco_pdcache_wb_range = 175 mips_cache_ops.mco_intern_pdcache_wb_range = 176 mipsNN_pdcache_wb_range_32; 177 #endif 178 break; 179 #ifdef CPU_CNMIPS 180 case 128: 181 mips_cache_ops.mco_pdcache_wbinv_all = 182 mips_cache_ops.mco_intern_pdcache_wbinv_all = 183 mipsNN_pdcache_wbinv_all_128; 184 mips_cache_ops.mco_pdcache_wbinv_range = 185 mipsNN_pdcache_wbinv_range_128; 186 mips_cache_ops.mco_pdcache_wbinv_range_index = 187 mips_cache_ops.mco_intern_pdcache_wbinv_range_index = 188 mipsNN_pdcache_wbinv_range_index_128; 189 mips_cache_ops.mco_pdcache_inv_range = 190 mipsNN_pdcache_inv_range_128; 191 mips_cache_ops.mco_pdcache_wb_range = 192 mips_cache_ops.mco_intern_pdcache_wb_range = 193 mipsNN_pdcache_wb_range_128; 194 break; 195 #endif 196 #ifdef MIPS_DISABLE_L1_CACHE 197 case 0: 198 mips_cache_ops.mco_pdcache_wbinv_all = cache_noop; 199 mips_cache_ops.mco_intern_pdcache_wbinv_all = cache_noop; 200 mips_cache_ops.mco_pdcache_wbinv_range = 201 (void (*)(vaddr_t, vsize_t))cache_noop; 202 mips_cache_ops.mco_pdcache_wbinv_range_index = 203 (void (*)(vaddr_t, vsize_t))cache_noop; 204 mips_cache_ops.mco_intern_pdcache_wbinv_range_index = 205 (void (*)(vaddr_t, vsize_t))cache_noop; 206 mips_cache_ops.mco_pdcache_inv_range = 207 (void (*)(vaddr_t, vsize_t))cache_noop; 208 mips_cache_ops.mco_pdcache_wb_range = 209 (void (*)(vaddr_t, vsize_t))cache_noop; 210 mips_cache_ops.mco_intern_pdcache_wb_range = 211 (void (*)(vaddr_t, vsize_t))cache_noop; 212 break; 213 #endif 214 default: 215 panic("no Dcache ops for %d byte lines", 216 cpuinfo->l1.dc_linesize); 217 } 218 219 mipsNN_cache_init(cpuinfo); 220 221 #if 0 222 if (mips_cpu_flags & 223 (CPU_MIPS_D_CACHE_COHERENT | CPU_MIPS_I_D_CACHE_COHERENT)) { 224 #ifdef CACHE_DEBUG 225 printf(" Dcache is coherent\n"); 226 #endif 227 mips_cache_ops.mco_pdcache_wbinv_all = cache_noop; 228 mips_cache_ops.mco_pdcache_wbinv_range = 229 (void (*)(vaddr_t, vsize_t))cache_noop; 230 mips_cache_ops.mco_pdcache_wbinv_range_index = 231 (void (*)(vaddr_t, vsize_t))cache_noop; 232 mips_cache_ops.mco_pdcache_inv_range = 233 (void (*)(vaddr_t, vsize_t))cache_noop; 234 mips_cache_ops.mco_pdcache_wb_range = 235 (void (*)(vaddr_t, vsize_t))cache_noop; 236 } 237 if (mips_cpu_flags & CPU_MIPS_I_D_CACHE_COHERENT) { 238 #ifdef CACHE_DEBUG 239 printf(" Icache is coherent against Dcache\n"); 240 #endif 241 mips_cache_ops.mco_intern_pdcache_wbinv_all = 242 cache_noop; 243 mips_cache_ops.mco_intern_pdcache_wbinv_range_index = 244 (void (*)(vaddr_t, vsize_t))cache_noop; 245 mips_cache_ops.mco_intern_pdcache_wb_range = 246 (void (*)(vaddr_t, vsize_t))cache_noop; 247 } 248 #endif 249 250 /* Check that all cache ops are set up. */ 251 /* must have primary Icache */ 252 if (cpuinfo->l1.ic_size) { 253 254 if (!mips_cache_ops.mco_icache_sync_all) 255 panic("no icache_sync_all cache op"); 256 if (!mips_cache_ops.mco_icache_sync_range) 257 panic("no icache_sync_range cache op"); 258 if (!mips_cache_ops.mco_icache_sync_range_index) 259 panic("no icache_sync_range_index cache op"); 260 } 261 /* must have primary Dcache */ 262 if (cpuinfo->l1.dc_size) { 263 if (!mips_cache_ops.mco_pdcache_wbinv_all) 264 panic("no pdcache_wbinv_all"); 265 if (!mips_cache_ops.mco_pdcache_wbinv_range) 266 panic("no pdcache_wbinv_range"); 267 if (!mips_cache_ops.mco_pdcache_wbinv_range_index) 268 panic("no pdcache_wbinv_range_index"); 269 if (!mips_cache_ops.mco_pdcache_inv_range) 270 panic("no pdcache_inv_range"); 271 if (!mips_cache_ops.mco_pdcache_wb_range) 272 panic("no pdcache_wb_range"); 273 } 274 275 /* XXXMIPS: No secondary cache handlers yet */ 276 #ifdef notyet 277 if (mips_sdcache_size) { 278 if (!mips_cache_ops.mco_sdcache_wbinv_all) 279 panic("no sdcache_wbinv_all"); 280 if (!mips_cache_ops.mco_sdcache_wbinv_range) 281 panic("no sdcache_wbinv_range"); 282 if (!mips_cache_ops.mco_sdcache_wbinv_range_index) 283 panic("no sdcache_wbinv_range_index"); 284 if (!mips_cache_ops.mco_sdcache_inv_range) 285 panic("no sdcache_inv_range"); 286 if (!mips_cache_ops.mco_sdcache_wb_range) 287 panic("no sdcache_wb_range"); 288 } 289 #endif 290 }
Cache object: fe84f606e356e70c4ed193687a555c8a
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