The Design and Implementation of the FreeBSD Operating System, Second Edition
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FreeBSD/Linux Kernel Cross Reference
sys/mips/mips/machdep.c

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    1     /*  $OpenBSD: machdep.c,v 1.33 1998/09/15 10:58:54 pefo Exp $       */
    2 /* tracked to 1.38 */
    3 /*-
    4  * SPDX-License-Identifier: BSD-3-Clause
    5  *
    6  * Copyright (c) 1988 University of Utah.
    7  * Copyright (c) 1992, 1993
    8  *      The Regents of the University of California.  All rights reserved.
    9  *
   10  * This code is derived from software contributed to Berkeley by
   11  * the Systems Programming Group of the University of Utah Computer
   12  * Science Department, The Mach Operating System project at
   13  * Carnegie-Mellon University and Ralph Campbell.
   14  *
   15  * Redistribution and use in source and binary forms, with or without
   16  * modification, are permitted provided that the following conditions
   17  * are met:
   18  * 1. Redistributions of source code must retain the above copyright
   19  *    notice, this list of conditions and the following disclaimer.
   20  * 2. Redistributions in binary form must reproduce the above copyright
   21  *    notice, this list of conditions and the following disclaimer in the
   22  *    documentation and/or other materials provided with the distribution.
   23  * 3. Neither the name of the University nor the names of its contributors
   24  *    may be used to endorse or promote products derived from this software
   25  *    without specific prior written permission.
   26  *
   27  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
   28  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   29  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   30  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
   31  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
   32  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
   33  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
   34  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
   35  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   36  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   37  * SUCH DAMAGE.
   38  *
   39  *      from: @(#)machdep.c     8.3 (Berkeley) 1/12/94
   40  *      Id: machdep.c,v 1.33 1998/09/15 10:58:54 pefo Exp
   41  *      JNPR: machdep.c,v 1.11.2.3 2007/08/29 12:24:49
   42  */
   43 
   44 #include <sys/cdefs.h>
   45 __FBSDID("$FreeBSD: stable/12/sys/mips/mips/machdep.c 328978 2018-02-07 16:58:01Z arichardson $");
   46 
   47 #include "opt_ddb.h"
   48 #include "opt_md.h"
   49 
   50 #include <sys/param.h>
   51 #include <sys/proc.h>
   52 #include <sys/systm.h>
   53 #include <sys/buf.h>
   54 #include <sys/bus.h>
   55 #include <sys/conf.h>
   56 #include <sys/cpu.h>
   57 #include <sys/kernel.h>
   58 #include <sys/linker.h>
   59 #include <sys/malloc.h>
   60 #include <sys/mbuf.h>
   61 #include <sys/msgbuf.h>
   62 #include <sys/reboot.h>
   63 #include <sys/rwlock.h>
   64 #include <sys/sched.h>
   65 #include <sys/sysctl.h>
   66 #include <sys/sysproto.h>
   67 #include <sys/vmmeter.h>
   68 
   69 #include <vm/vm.h>
   70 #include <vm/vm_kern.h>
   71 #include <vm/vm_object.h>
   72 #include <vm/vm_page.h>
   73 #include <vm/pmap.h>
   74 #include <vm/vm_map.h>
   75 #include <vm/vm_pager.h>
   76 #include <vm/vm_extern.h>
   77 #include <sys/socket.h>
   78 
   79 #include <sys/user.h>
   80 #include <sys/interrupt.h>
   81 #include <sys/cons.h>
   82 #include <sys/syslog.h>
   83 #include <machine/asm.h>
   84 #include <machine/bootinfo.h>
   85 #include <machine/cache.h>
   86 #include <machine/clock.h>
   87 #include <machine/cpu.h>
   88 #include <machine/cpuregs.h>
   89 #include <machine/elf.h>
   90 #include <machine/hwfunc.h>
   91 #include <machine/intr_machdep.h>
   92 #include <machine/md_var.h>
   93 #include <machine/tlb.h>
   94 #ifdef DDB
   95 #include <sys/kdb.h>
   96 #include <ddb/ddb.h>
   97 #endif
   98 
   99 #include <sys/random.h>
  100 #include <net/if.h>
  101 
  102 #define BOOTINFO_DEBUG  0
  103 
  104 char machine[] = "mips";
  105 SYSCTL_STRING(_hw, HW_MACHINE, machine, CTLFLAG_RD, machine, 0, "Machine class");
  106 
  107 char cpu_model[80];
  108 SYSCTL_STRING(_hw, HW_MODEL, model, CTLFLAG_RD, cpu_model, 0, "Machine model");
  109 
  110 char cpu_board[80];
  111 SYSCTL_STRING(_hw, OID_AUTO, board, CTLFLAG_RD, cpu_board, 0, "Machine board");
  112 
  113 int cold = 1;
  114 long realmem = 0;
  115 long Maxmem = 0;
  116 int cpu_clock = MIPS_DEFAULT_HZ;
  117 SYSCTL_INT(_hw, OID_AUTO, clockrate, CTLFLAG_RD, 
  118     &cpu_clock, 0, "CPU instruction clock rate");
  119 int clocks_running = 0;
  120 
  121 vm_offset_t kstack0;
  122 
  123 /*
  124  * Each entry in the pcpu_space[] array is laid out in the following manner:
  125  * struct pcpu for cpu 'n'      pcpu_space[n]
  126  * boot stack for cpu 'n'       pcpu_space[n] + PAGE_SIZE * 2 - CALLFRAME_SIZ
  127  *
  128  * Note that the boot stack grows downwards and we assume that we never
  129  * use enough stack space to trample over the 'struct pcpu' that is at
  130  * the beginning of the array.
  131  *
  132  * The array is aligned on a (PAGE_SIZE * 2) boundary so that the 'struct pcpu'
  133  * is always in the even page frame of the wired TLB entry on SMP kernels.
  134  *
  135  * The array is in the .data section so that the stack does not get zeroed out
  136  * when the .bss section is zeroed.
  137  */
  138 char pcpu_space[MAXCPU][PAGE_SIZE * 2] \
  139         __aligned(PAGE_SIZE * 2) __section(".data");
  140 
  141 struct pcpu *pcpup = (struct pcpu *)pcpu_space;
  142 
  143 vm_paddr_t phys_avail[PHYS_AVAIL_ENTRIES + 2];
  144 vm_paddr_t physmem_desc[PHYS_AVAIL_ENTRIES + 2];
  145 vm_paddr_t dump_avail[PHYS_AVAIL_ENTRIES + 2];
  146 
  147 #ifdef UNIMPLEMENTED
  148 struct platform platform;
  149 #endif
  150 
  151 static void cpu_startup(void *);
  152 SYSINIT(cpu, SI_SUB_CPU, SI_ORDER_FIRST, cpu_startup, NULL);
  153 
  154 struct kva_md_info kmi;
  155 
  156 int cpucfg;                     /* Value of processor config register */
  157 int num_tlbentries = 64;        /* Size of the CPU tlb */
  158 int cputype;
  159 
  160 extern char MipsException[], MipsExceptionEnd[];
  161 
  162 /* TLB miss handler address and end */
  163 extern char MipsTLBMiss[], MipsTLBMissEnd[];
  164 
  165 /* Cache error handler */
  166 extern char MipsCache[], MipsCacheEnd[];
  167 
  168 /* MIPS wait skip region */
  169 extern char MipsWaitStart[], MipsWaitEnd[];
  170 
  171 extern char edata[], end[];
  172 
  173 u_int32_t bootdev;
  174 struct bootinfo bootinfo;
  175 /*
  176  * First kseg0 address available for use. By default it's equal to &end.
  177  * But in some cases there might be additional data placed right after 
  178  * _end by loader or ELF trampoline.
  179  */
  180 vm_offset_t kernel_kseg0_end = (vm_offset_t)&end;
  181 
  182 static void
  183 cpu_startup(void *dummy)
  184 {
  185 
  186         if (boothowto & RB_VERBOSE)
  187                 bootverbose++;
  188 
  189         printf("real memory  = %ju (%juK bytes)\n", ptoa((uintmax_t)realmem),
  190             ptoa((uintmax_t)realmem) / 1024);
  191 
  192         /*
  193          * Display any holes after the first chunk of extended memory.
  194          */
  195         if (bootverbose) {
  196                 int indx;
  197 
  198                 printf("Physical memory chunk(s):\n");
  199                 for (indx = 0; phys_avail[indx + 1] != 0; indx += 2) {
  200                         vm_paddr_t size1 = phys_avail[indx + 1] - phys_avail[indx];
  201 
  202                         printf("0x%08jx - 0x%08jx, %ju bytes (%ju pages)\n",
  203                             (uintmax_t)phys_avail[indx],
  204                             (uintmax_t)phys_avail[indx + 1] - 1,
  205                             (uintmax_t)size1,
  206                             (uintmax_t)size1 / PAGE_SIZE);
  207                 }
  208         }
  209 
  210         vm_ksubmap_init(&kmi);
  211 
  212         printf("avail memory = %ju (%juMB)\n", 
  213             ptoa((uintmax_t)vm_free_count()),
  214             ptoa((uintmax_t)vm_free_count()) / 1048576);
  215         cpu_init_interrupts();
  216 
  217         /*
  218          * Set up buffers, so they can be used to read disk labels.
  219          */
  220         bufinit();
  221         vm_pager_bufferinit();
  222 }
  223 
  224 /*
  225  * Shutdown the CPU as much as possible
  226  */
  227 void
  228 cpu_reset(void)
  229 {
  230 
  231         platform_reset();
  232 }
  233 
  234 /*
  235  * Flush the D-cache for non-DMA I/O so that the I-cache can
  236  * be made coherent later.
  237  */
  238 void
  239 cpu_flush_dcache(void *ptr, size_t len)
  240 {
  241         /* TBD */
  242 }
  243 
  244 /* Get current clock frequency for the given cpu id. */
  245 int
  246 cpu_est_clockrate(int cpu_id, uint64_t *rate)
  247 {
  248 
  249         return (ENXIO);
  250 }
  251 
  252 /*
  253  * Shutdown the CPU as much as possible
  254  */
  255 void
  256 cpu_halt(void)
  257 {
  258         for (;;)
  259                 ;
  260 }
  261 
  262 SYSCTL_STRUCT(_machdep, OID_AUTO, bootinfo, CTLFLAG_RD, &bootinfo,
  263     bootinfo, "Bootinfo struct: kernel filename, BIOS harddisk geometry, etc");
  264 
  265 /*
  266  * Initialize per cpu data structures, include curthread.
  267  */
  268 void
  269 mips_pcpu0_init()
  270 {
  271         /* Initialize pcpu info of cpu-zero */
  272         pcpu_init(PCPU_ADDR(0), 0, sizeof(struct pcpu));
  273         PCPU_SET(curthread, &thread0);
  274 }
  275 
  276 /*
  277  * Initialize mips and configure to run kernel
  278  */
  279 void
  280 mips_proc0_init(void)
  281 {
  282 #ifdef SMP
  283         if (platform_processor_id() != 0)
  284                 panic("BSP must be processor number 0");
  285 #endif
  286         proc_linkup0(&proc0, &thread0);
  287 
  288         KASSERT((kstack0 & PAGE_MASK) == 0,
  289                 ("kstack0 is not aligned on a page boundary: 0x%0lx",
  290                 (long)kstack0));
  291         thread0.td_kstack = kstack0;
  292         thread0.td_kstack_pages = KSTACK_PAGES;
  293         /* 
  294          * Do not use cpu_thread_alloc to initialize these fields 
  295          * thread0 is the only thread that has kstack located in KSEG0 
  296          * while cpu_thread_alloc handles kstack allocated in KSEG2.
  297          */
  298         thread0.td_pcb = (struct pcb *)(thread0.td_kstack +
  299             thread0.td_kstack_pages * PAGE_SIZE) - 1;
  300         thread0.td_frame = &thread0.td_pcb->pcb_regs;
  301 
  302         /* Steal memory for the dynamic per-cpu area. */
  303         dpcpu_init((void *)pmap_steal_memory(DPCPU_SIZE), 0);
  304 
  305         PCPU_SET(curpcb, thread0.td_pcb);
  306         /*
  307          * There is no need to initialize md_upte array for thread0 as it's
  308          * located in .bss section and should be explicitly zeroed during 
  309          * kernel initialization.
  310          */
  311 }
  312 
  313 void
  314 cpu_initclocks(void)
  315 {
  316 
  317         platform_initclocks();
  318         cpu_initclocks_bsp();
  319 }
  320 
  321 /*
  322  * Initialize the hardware exception vectors, and the jump table used to
  323  * call locore cache and TLB management functions, based on the kind
  324  * of CPU the kernel is running on.
  325  */
  326 void
  327 mips_vector_init(void)
  328 {
  329         /*
  330          * Make sure that the Wait region logic is not been 
  331          * changed
  332          */
  333         if (MipsWaitEnd - MipsWaitStart != 16)
  334                 panic("startup: MIPS wait region not correct");
  335         /*
  336          * Copy down exception vector code.
  337          */
  338         if (MipsTLBMissEnd - MipsTLBMiss > 0x80)
  339                 panic("startup: UTLB code too large");
  340 
  341         if (MipsCacheEnd - MipsCache > 0x80)
  342                 panic("startup: Cache error code too large");
  343 
  344         bcopy(MipsTLBMiss, (void *)MIPS_UTLB_MISS_EXC_VEC,
  345               MipsTLBMissEnd - MipsTLBMiss);
  346 
  347         /*
  348          * XXXRW: Why don't we install the XTLB handler for all 64-bit
  349          * architectures?
  350          */
  351 #if defined(__mips_n64) || defined(CPU_RMI) || defined(CPU_NLM) || defined(CPU_BERI)
  352 /* Fake, but sufficient, for the 32-bit with 64-bit hardware addresses  */
  353         bcopy(MipsTLBMiss, (void *)MIPS_XTLB_MISS_EXC_VEC,
  354               MipsTLBMissEnd - MipsTLBMiss);
  355 #endif
  356 
  357         bcopy(MipsException, (void *)MIPS_GEN_EXC_VEC,
  358               MipsExceptionEnd - MipsException);
  359 
  360         bcopy(MipsCache, (void *)MIPS_CACHE_ERR_EXC_VEC,
  361               MipsCacheEnd - MipsCache);
  362 
  363         /*
  364          * Clear out the I and D caches.
  365          */
  366         mips_icache_sync_all();
  367         mips_dcache_wbinv_all();
  368 
  369         /* 
  370          * Mask all interrupts. Each interrupt will be enabled
  371          * when handler is installed for it
  372          */
  373         set_intr_mask(0);
  374 
  375         /* Clear BEV in SR so we start handling our own exceptions */
  376         mips_wr_status(mips_rd_status() & ~MIPS_SR_BEV);
  377 }
  378 
  379 /*
  380  * Fix kernel_kseg0_end address in case trampoline placed debug sympols 
  381  * data there
  382  */
  383 void
  384 mips_postboot_fixup(void)
  385 {
  386         /*
  387          * We store u_long sized objects into the reload area, so the array
  388          * must be so aligned. The standard allows any alignment for char data.
  389          */
  390         _Alignas(_Alignof(u_long)) static char fake_preload[256];
  391         caddr_t preload_ptr = (caddr_t)&fake_preload[0];
  392         size_t size = 0;
  393 
  394 #define PRELOAD_PUSH_VALUE(type, value) do {            \
  395         *(type *)(preload_ptr + size) = (value);        \
  396         size += sizeof(type);                           \
  397 } while (0);
  398 
  399         /*
  400          * Provide kernel module file information
  401          */
  402         PRELOAD_PUSH_VALUE(uint32_t, MODINFO_NAME);
  403         PRELOAD_PUSH_VALUE(uint32_t, strlen("kernel") + 1);
  404         strcpy((char*)(preload_ptr + size), "kernel");
  405         size += strlen("kernel") + 1;
  406         size = roundup(size, sizeof(u_long));
  407 
  408         PRELOAD_PUSH_VALUE(uint32_t, MODINFO_TYPE);
  409         PRELOAD_PUSH_VALUE(uint32_t, strlen("elf kernel") + 1);
  410         strcpy((char*)(preload_ptr + size), "elf kernel");
  411         size += strlen("elf kernel") + 1;
  412         size = roundup(size, sizeof(u_long));
  413 
  414         PRELOAD_PUSH_VALUE(uint32_t, MODINFO_ADDR);
  415         PRELOAD_PUSH_VALUE(uint32_t, sizeof(vm_offset_t));
  416         PRELOAD_PUSH_VALUE(vm_offset_t, KERNLOADADDR);
  417         size = roundup(size, sizeof(u_long));
  418 
  419         PRELOAD_PUSH_VALUE(uint32_t, MODINFO_SIZE);
  420         PRELOAD_PUSH_VALUE(uint32_t, sizeof(size_t));
  421         PRELOAD_PUSH_VALUE(size_t, (size_t)&end - KERNLOADADDR);
  422         size = roundup(size, sizeof(u_long));
  423 
  424         /* End marker */
  425         PRELOAD_PUSH_VALUE(uint32_t, 0);
  426         PRELOAD_PUSH_VALUE(uint32_t, 0);
  427 
  428 #undef  PRELOAD_PUSH_VALUE
  429 
  430         KASSERT((size < sizeof(fake_preload)),
  431                 ("fake preload size is more thenallocated"));
  432 
  433         preload_metadata = (void *)fake_preload;
  434 
  435 #ifdef DDB
  436         Elf_Size *trampoline_data = (Elf_Size*)kernel_kseg0_end;
  437         Elf_Size symtabsize = 0;
  438         vm_offset_t ksym_start;
  439         vm_offset_t ksym_end;
  440 
  441         if (trampoline_data[0] == SYMTAB_MAGIC) {
  442                 symtabsize = trampoline_data[1];
  443                 kernel_kseg0_end += 2 * sizeof(Elf_Size);
  444                 /* start of .symtab */
  445                 ksym_start = kernel_kseg0_end;
  446                 kernel_kseg0_end += symtabsize;
  447                 /* end of .strtab */
  448                 ksym_end = kernel_kseg0_end;
  449                 db_fetch_ksymtab(ksym_start, ksym_end);
  450         }
  451 #endif
  452 }
  453 
  454 #ifdef SMP
  455 void
  456 mips_pcpu_tlb_init(struct pcpu *pcpu)
  457 {
  458         vm_paddr_t pa;
  459         pt_entry_t pte;
  460 
  461         /*
  462          * Map the pcpu structure at the virtual address 'pcpup'.
  463          * We use a wired tlb index to do this one-time mapping.
  464          */
  465         pa = vtophys(pcpu);
  466         pte = PTE_D | PTE_V | PTE_G | PTE_C_CACHE;
  467         tlb_insert_wired(PCPU_TLB_ENTRY, (vm_offset_t)pcpup,
  468                          TLBLO_PA_TO_PFN(pa) | pte,
  469                          TLBLO_PA_TO_PFN(pa + PAGE_SIZE) | pte);
  470 }
  471 #endif
  472 
  473 /*
  474  * Initialise a struct pcpu.
  475  */
  476 void
  477 cpu_pcpu_init(struct pcpu *pcpu, int cpuid, size_t size)
  478 {
  479 
  480         pcpu->pc_next_asid = 1;
  481         pcpu->pc_asid_generation = 1;
  482         pcpu->pc_self = pcpu;
  483 #ifdef SMP
  484         if ((vm_offset_t)pcpup >= VM_MIN_KERNEL_ADDRESS &&
  485             (vm_offset_t)pcpup <= VM_MAX_KERNEL_ADDRESS) {
  486                 mips_pcpu_tlb_init(pcpu);
  487         }
  488 #endif
  489 }
  490 
  491 int
  492 fill_dbregs(struct thread *td, struct dbreg *dbregs)
  493 {
  494 
  495         /* No debug registers on mips */
  496         return (ENOSYS);
  497 }
  498 
  499 int
  500 set_dbregs(struct thread *td, struct dbreg *dbregs)
  501 {
  502 
  503         /* No debug registers on mips */
  504         return (ENOSYS);
  505 }
  506 
  507 void
  508 spinlock_enter(void)
  509 {
  510         struct thread *td;
  511         register_t intr;
  512 
  513         td = curthread;
  514         if (td->td_md.md_spinlock_count == 0) {
  515                 intr = intr_disable();
  516                 td->td_md.md_spinlock_count = 1;
  517                 td->td_md.md_saved_intr = intr;
  518         } else
  519                 td->td_md.md_spinlock_count++;
  520         critical_enter();
  521 }
  522 
  523 void
  524 spinlock_exit(void)
  525 {
  526         struct thread *td;
  527         register_t intr;
  528 
  529         td = curthread;
  530         critical_exit();
  531         intr = td->td_md.md_saved_intr;
  532         td->td_md.md_spinlock_count--;
  533         if (td->td_md.md_spinlock_count == 0)
  534                 intr_restore(intr);
  535 }
  536 
  537 /*
  538  * call platform specific code to halt (until next interrupt) for the idle loop
  539  */
  540 void
  541 cpu_idle(int busy)
  542 {
  543         KASSERT((mips_rd_status() & MIPS_SR_INT_IE) != 0,
  544                 ("interrupts disabled in idle process."));
  545         KASSERT((mips_rd_status() & MIPS_INT_MASK) != 0,
  546                 ("all interrupts masked in idle process."));
  547 
  548         if (!busy) {
  549                 critical_enter();
  550                 cpu_idleclock();
  551         }
  552         mips_wait();
  553         if (!busy) {
  554                 cpu_activeclock();
  555                 critical_exit();
  556         }
  557 }
  558 
  559 int
  560 cpu_idle_wakeup(int cpu)
  561 {
  562 
  563         return (0);
  564 }
  565 
  566 int
  567 is_cacheable_mem(vm_paddr_t pa)
  568 {
  569         int i;
  570 
  571         for (i = 0; physmem_desc[i + 1] != 0; i += 2) {
  572                 if (pa >= physmem_desc[i] && pa < physmem_desc[i + 1])
  573                         return (1);
  574         }
  575 
  576         return (0);
  577 }

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