1 /*-
2 * SPDX-License-Identifier: BSD-3-Clause
3 *
4 * Copyright (c) 1992 Terrence R. Lambert.
5 * Copyright (c) 1982, 1987, 1990 The Regents of the University of California.
6 * All rights reserved.
7 *
8 * This code is derived from software contributed to Berkeley by
9 * William Jolitz.
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 * 1. Redistributions of source code must retain the above copyright
15 * notice, this list of conditions and the following disclaimer.
16 * 2. Redistributions in binary form must reproduce the above copyright
17 * notice, this list of conditions and the following disclaimer in the
18 * documentation and/or other materials provided with the distribution.
19 * 3. Neither the name of the University nor the names of its contributors
20 * may be used to endorse or promote products derived from this software
21 * without specific prior written permission.
22 *
23 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
26 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
27 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
28 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
29 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
30 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
31 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
32 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
33 * SUCH DAMAGE.
34 *
35 * from: @(#)machdep.c 7.4 (Berkeley) 6/3/91
36 * from: src/sys/i386/i386/machdep.c,v 1.385.2.3 2000/05/10 02:04:46 obrien
37 * JNPR: pm_machdep.c,v 1.9.2.1 2007/08/16 15:59:10 girish
38 */
39
40 #include <sys/cdefs.h>
41 __FBSDID("$FreeBSD$");
42
43 #include <sys/param.h>
44 #include <sys/systm.h>
45 #include <sys/sysent.h>
46 #include <sys/proc.h>
47 #include <sys/signalvar.h>
48 #include <sys/exec.h>
49 #include <sys/ktr.h>
50 #include <sys/imgact.h>
51 #include <sys/ucontext.h>
52 #include <sys/lock.h>
53 #include <sys/syscallsubr.h>
54 #include <sys/sysproto.h>
55 #include <sys/ptrace.h>
56 #include <sys/syslog.h>
57 #include <vm/vm.h>
58 #include <vm/pmap.h>
59 #include <vm/vm_map.h>
60 #include <vm/vm_extern.h>
61 #include <sys/user.h>
62 #include <sys/uio.h>
63 #include <machine/abi.h>
64 #include <machine/cpuinfo.h>
65 #include <machine/reg.h>
66 #include <machine/md_var.h>
67 #include <machine/sigframe.h>
68 #include <machine/tls.h>
69 #include <machine/vmparam.h>
70 #include <sys/vnode.h>
71 #include <fs/pseudofs/pseudofs.h>
72 #include <fs/procfs/procfs.h>
73
74 #define UCONTEXT_MAGIC 0xACEDBADE
75
76 /*
77 * Send an interrupt to process.
78 *
79 * Stack is set up to allow sigcode stored
80 * at top to call routine, followed by kcall
81 * to sigreturn routine below. After sigreturn
82 * resets the signal mask, the stack, and the
83 * frame pointer, it returns to the user
84 * specified pc, psl.
85 */
86 void
87 sendsig(sig_t catcher, ksiginfo_t *ksi, sigset_t *mask)
88 {
89 struct proc *p;
90 struct thread *td;
91 struct trapframe *regs;
92 struct sigacts *psp;
93 struct sigframe sf, *sfp;
94 int sig;
95 int oonstack;
96
97 td = curthread;
98 p = td->td_proc;
99 PROC_LOCK_ASSERT(p, MA_OWNED);
100 sig = ksi->ksi_signo;
101 psp = p->p_sigacts;
102 mtx_assert(&psp->ps_mtx, MA_OWNED);
103
104 regs = td->td_frame;
105 oonstack = sigonstack(regs->sp);
106
107 /* save user context */
108 bzero(&sf, sizeof(struct sigframe));
109 sf.sf_uc.uc_sigmask = *mask;
110 sf.sf_uc.uc_stack = td->td_sigstk;
111 sf.sf_uc.uc_mcontext.mc_onstack = (oonstack) ? 1 : 0;
112 sf.sf_uc.uc_mcontext.mc_pc = regs->pc;
113 sf.sf_uc.uc_mcontext.mullo = regs->mullo;
114 sf.sf_uc.uc_mcontext.mulhi = regs->mulhi;
115 sf.sf_uc.uc_mcontext.mc_tls = td->td_md.md_tls;
116 sf.sf_uc.uc_mcontext.mc_regs[0] = UCONTEXT_MAGIC; /* magic number */
117 bcopy((void *)®s->ast, (void *)&sf.sf_uc.uc_mcontext.mc_regs[1],
118 sizeof(sf.sf_uc.uc_mcontext.mc_regs) - sizeof(register_t));
119 sf.sf_uc.uc_mcontext.mc_fpused = td->td_md.md_flags & MDTD_FPUSED;
120 if (sf.sf_uc.uc_mcontext.mc_fpused) {
121 /* if FPU has current state, save it first */
122 if (td == PCPU_GET(fpcurthread))
123 MipsSaveCurFPState(td);
124 bcopy((void *)&td->td_frame->f0,
125 (void *)sf.sf_uc.uc_mcontext.mc_fpregs,
126 sizeof(sf.sf_uc.uc_mcontext.mc_fpregs));
127 }
128
129 /* Allocate and validate space for the signal handler context. */
130 if ((td->td_pflags & TDP_ALTSTACK) != 0 && !oonstack &&
131 SIGISMEMBER(psp->ps_sigonstack, sig)) {
132 sfp = (struct sigframe *)(((uintptr_t)td->td_sigstk.ss_sp +
133 td->td_sigstk.ss_size - sizeof(struct sigframe))
134 & ~(STACK_ALIGN - 1));
135 } else
136 sfp = (struct sigframe *)((vm_offset_t)(regs->sp -
137 sizeof(struct sigframe)) & ~(STACK_ALIGN - 1));
138
139 /* Build the argument list for the signal handler. */
140 regs->a0 = sig;
141 regs->a2 = (register_t)(intptr_t)&sfp->sf_uc;
142 if (SIGISMEMBER(psp->ps_siginfo, sig)) {
143 /* Signal handler installed with SA_SIGINFO. */
144 regs->a1 = (register_t)(intptr_t)&sfp->sf_si;
145 /* sf.sf_ahu.sf_action = (__siginfohandler_t *)catcher; */
146
147 /* fill siginfo structure */
148 sf.sf_si = ksi->ksi_info;
149 sf.sf_si.si_signo = sig;
150 } else {
151 /* Old FreeBSD-style arguments. */
152 regs->a1 = ksi->ksi_code;
153 regs->a3 = (uintptr_t)ksi->ksi_addr;
154 /* sf.sf_ahu.sf_handler = catcher; */
155 }
156
157 mtx_unlock(&psp->ps_mtx);
158 PROC_UNLOCK(p);
159
160 /*
161 * Copy the sigframe out to the user's stack.
162 */
163 if (copyout(&sf, sfp, sizeof(struct sigframe)) != 0) {
164 /*
165 * Something is wrong with the stack pointer.
166 * ...Kill the process.
167 */
168 PROC_LOCK(p);
169 sigexit(td, SIGILL);
170 }
171
172 regs->pc = (register_t)(intptr_t)catcher;
173 regs->t9 = (register_t)(intptr_t)catcher;
174 regs->sp = (register_t)(intptr_t)sfp;
175 /*
176 * Signal trampoline code is at base of user stack.
177 */
178 regs->ra = (register_t)(intptr_t)PS_STRINGS - *(p->p_sysent->sv_szsigcode);
179 PROC_LOCK(p);
180 mtx_lock(&psp->ps_mtx);
181 }
182
183 /*
184 * System call to cleanup state after a signal
185 * has been taken. Reset signal mask and
186 * stack state from context left by sendsig (above).
187 * Return to previous pc as specified by
188 * context left by sendsig.
189 */
190 int
191 sys_sigreturn(struct thread *td, struct sigreturn_args *uap)
192 {
193 ucontext_t uc;
194 int error;
195
196 error = copyin(uap->sigcntxp, &uc, sizeof(uc));
197 if (error != 0)
198 return (error);
199
200 error = set_mcontext(td, &uc.uc_mcontext);
201 if (error != 0)
202 return (error);
203
204 kern_sigprocmask(td, SIG_SETMASK, &uc.uc_sigmask, NULL, 0);
205
206 return (EJUSTRETURN);
207 }
208
209 int
210 ptrace_set_pc(struct thread *td, unsigned long addr)
211 {
212 td->td_frame->pc = (register_t) addr;
213 return 0;
214 }
215
216 static int
217 ptrace_read_int(struct thread *td, uintptr_t addr, int *v)
218 {
219
220 if (proc_readmem(td, td->td_proc, addr, v, sizeof(*v)) != sizeof(*v))
221 return (EFAULT);
222 return (0);
223 }
224
225 static int
226 ptrace_write_int(struct thread *td, uintptr_t addr, int v)
227 {
228
229 if (proc_writemem(td, td->td_proc, addr, &v, sizeof(v)) != sizeof(v))
230 return (EFAULT);
231 return (0);
232 }
233
234 int
235 ptrace_single_step(struct thread *td)
236 {
237 uintptr_t va;
238 struct trapframe *locr0 = td->td_frame;
239 int error;
240 int bpinstr = MIPS_BREAK_SSTEP;
241 int curinstr;
242 struct proc *p;
243
244 p = td->td_proc;
245 PROC_UNLOCK(p);
246 /*
247 * Fetch what's at the current location.
248 */
249 error = ptrace_read_int(td, locr0->pc, &curinstr);
250 if (error)
251 goto out;
252
253 CTR3(KTR_PTRACE,
254 "ptrace_single_step: tid %d, current instr at %#lx: %#08x",
255 td->td_tid, locr0->pc, curinstr);
256
257 /* compute next address after current location */
258 if (locr0->cause & MIPS_CR_BR_DELAY) {
259 va = MipsEmulateBranch(locr0, locr0->pc, locr0->fsr,
260 (uintptr_t)&curinstr);
261 } else {
262 va = locr0->pc + 4;
263 }
264 if (td->td_md.md_ss_addr) {
265 printf("SS %s (%d): breakpoint already set at %p (va %p)\n",
266 p->p_comm, p->p_pid, (void *)td->td_md.md_ss_addr,
267 (void *)va); /* XXX */
268 error = EFAULT;
269 goto out;
270 }
271 td->td_md.md_ss_addr = va;
272 /*
273 * Fetch what's at the current location.
274 */
275 error = ptrace_read_int(td, (off_t)va, &td->td_md.md_ss_instr);
276 if (error)
277 goto out;
278
279 /*
280 * Store breakpoint instruction at the "next" location now.
281 */
282 error = ptrace_write_int(td, va, bpinstr);
283
284 /*
285 * The sync'ing of I & D caches is done by proc_rwmem()
286 * through proc_writemem().
287 */
288
289 out:
290 PROC_LOCK(p);
291 if (error == 0)
292 CTR3(KTR_PTRACE,
293 "ptrace_single_step: tid %d, break set at %#lx: (%#08x)",
294 td->td_tid, va, td->td_md.md_ss_instr);
295 return (error);
296 }
297
298 void
299 makectx(struct trapframe *tf, struct pcb *pcb)
300 {
301
302 pcb->pcb_context[PCB_REG_RA] = tf->ra;
303 pcb->pcb_context[PCB_REG_PC] = tf->pc;
304 pcb->pcb_context[PCB_REG_SP] = tf->sp;
305 }
306
307 int
308 fill_regs(struct thread *td, struct reg *regs)
309 {
310 memcpy(regs, td->td_frame, sizeof(struct reg));
311 return (0);
312 }
313
314 int
315 set_regs(struct thread *td, struct reg *regs)
316 {
317 struct trapframe *f;
318 register_t sr;
319
320 f = (struct trapframe *) td->td_frame;
321 /*
322 * Don't allow the user to change SR
323 */
324 sr = f->sr;
325 memcpy(td->td_frame, regs, sizeof(struct reg));
326 f->sr = sr;
327 return (0);
328 }
329
330 int
331 get_mcontext(struct thread *td, mcontext_t *mcp, int flags)
332 {
333 struct trapframe *tp;
334
335 tp = td->td_frame;
336 PROC_LOCK(curthread->td_proc);
337 mcp->mc_onstack = sigonstack(tp->sp);
338 PROC_UNLOCK(curthread->td_proc);
339 bcopy((void *)&td->td_frame->zero, (void *)&mcp->mc_regs,
340 sizeof(mcp->mc_regs));
341
342 mcp->mc_fpused = td->td_md.md_flags & MDTD_FPUSED;
343 if (mcp->mc_fpused) {
344 bcopy((void *)&td->td_frame->f0, (void *)&mcp->mc_fpregs,
345 sizeof(mcp->mc_fpregs));
346 }
347 if (flags & GET_MC_CLEAR_RET) {
348 mcp->mc_regs[V0] = 0;
349 mcp->mc_regs[V1] = 0;
350 mcp->mc_regs[A3] = 0;
351 }
352
353 mcp->mc_pc = td->td_frame->pc;
354 mcp->mullo = td->td_frame->mullo;
355 mcp->mulhi = td->td_frame->mulhi;
356 mcp->mc_tls = td->td_md.md_tls;
357 return (0);
358 }
359
360 int
361 set_mcontext(struct thread *td, mcontext_t *mcp)
362 {
363 struct trapframe *tp;
364
365 tp = td->td_frame;
366 bcopy((void *)&mcp->mc_regs, (void *)&td->td_frame->zero,
367 sizeof(mcp->mc_regs));
368
369 td->td_md.md_flags = mcp->mc_fpused & MDTD_FPUSED;
370 if (mcp->mc_fpused) {
371 bcopy((void *)&mcp->mc_fpregs, (void *)&td->td_frame->f0,
372 sizeof(mcp->mc_fpregs));
373 }
374 td->td_frame->pc = mcp->mc_pc;
375 td->td_frame->mullo = mcp->mullo;
376 td->td_frame->mulhi = mcp->mulhi;
377 td->td_md.md_tls = mcp->mc_tls;
378 /* Dont let user to set any bits in status and cause registers. */
379
380 return (0);
381 }
382
383 int
384 fill_fpregs(struct thread *td, struct fpreg *fpregs)
385 {
386 if (td == PCPU_GET(fpcurthread))
387 MipsSaveCurFPState(td);
388 memcpy(fpregs, &td->td_frame->f0, sizeof(struct fpreg));
389 fpregs->r_regs[FIR_NUM] = cpuinfo.fpu_id;
390 return 0;
391 }
392
393 int
394 set_fpregs(struct thread *td, struct fpreg *fpregs)
395 {
396 if (PCPU_GET(fpcurthread) == td)
397 PCPU_SET(fpcurthread, (struct thread *)0);
398 memcpy(&td->td_frame->f0, fpregs, sizeof(struct fpreg));
399 return 0;
400 }
401
402 /*
403 * Clear registers on exec
404 * $sp is set to the stack pointer passed in. $pc is set to the entry
405 * point given by the exec_package passed in, as is $t9 (used for PIC
406 * code by the MIPS elf abi).
407 */
408 void
409 exec_setregs(struct thread *td, struct image_params *imgp, uintptr_t stack)
410 {
411
412 bzero((caddr_t)td->td_frame, sizeof(struct trapframe));
413
414 td->td_frame->sp = ((register_t)stack) & ~(STACK_ALIGN - 1);
415
416 /*
417 * If we're running o32 or n32 programs but have 64-bit registers,
418 * GCC may use stack-relative addressing near the top of user
419 * address space that, due to sign extension, will yield an
420 * invalid address. For instance, if sp is 0x7fffff00 then GCC
421 * might do something like this to load a word from 0x7ffffff0:
422 *
423 * addu sp, sp, 32768
424 * lw t0, -32528(sp)
425 *
426 * On systems with 64-bit registers, sp is sign-extended to
427 * 0xffffffff80007f00 and the load is instead done from
428 * 0xffffffff7ffffff0.
429 *
430 * To prevent this, we subtract 64K from the stack pointer here
431 * for processes with 32-bit pointers.
432 */
433 #if defined(__mips_n32) || defined(__mips_n64)
434 if (!SV_PROC_FLAG(td->td_proc, SV_LP64))
435 td->td_frame->sp -= 65536;
436 #endif
437
438 td->td_frame->pc = imgp->entry_addr & ~3;
439 td->td_frame->t9 = imgp->entry_addr & ~3; /* abicall req */
440 td->td_frame->sr = MIPS_SR_KSU_USER | MIPS_SR_EXL | MIPS_SR_INT_IE |
441 (mips_rd_status() & MIPS_SR_INT_MASK);
442 #if defined(__mips_n32) || defined(__mips_n64)
443 td->td_frame->sr |= MIPS_SR_PX;
444 #endif
445 #if defined(__mips_n64)
446 if (SV_PROC_FLAG(td->td_proc, SV_LP64))
447 td->td_frame->sr |= MIPS_SR_UX;
448 td->td_frame->sr |= MIPS_SR_KX;
449 #endif
450 /*
451 * FREEBSD_DEVELOPERS_FIXME:
452 * Setup any other CPU-Specific registers (Not MIPS Standard)
453 * and/or bits in other standard MIPS registers (if CPU-Specific)
454 * that are needed.
455 */
456
457 /*
458 * Set up arguments for the rtld-capable crt0:
459 * a0 stack pointer
460 * a1 rtld cleanup (filled in by dynamic loader)
461 * a2 rtld object (filled in by dynamic loader)
462 * a3 ps_strings
463 */
464 td->td_frame->a0 = (register_t) stack;
465 td->td_frame->a1 = 0;
466 td->td_frame->a2 = 0;
467 td->td_frame->a3 = (register_t)imgp->ps_strings;
468
469 td->td_md.md_flags &= ~MDTD_FPUSED;
470 if (PCPU_GET(fpcurthread) == td)
471 PCPU_SET(fpcurthread, (struct thread *)0);
472 td->td_md.md_ss_addr = 0;
473
474 td->td_md.md_tls = NULL;
475 #ifdef COMPAT_FREEBSD32
476 if (!SV_PROC_FLAG(td->td_proc, SV_LP64))
477 td->td_proc->p_md.md_tls_tcb_offset = TLS_TP_OFFSET +
478 TLS_TCB_SIZE32;
479 else
480 #endif
481 td->td_proc->p_md.md_tls_tcb_offset = TLS_TP_OFFSET +
482 TLS_TCB_SIZE;
483 }
484
485 int
486 ptrace_clear_single_step(struct thread *td)
487 {
488 struct proc *p;
489 int error;
490
491 p = td->td_proc;
492 PROC_LOCK_ASSERT(p, MA_OWNED);
493 if (!td->td_md.md_ss_addr)
494 return EINVAL;
495
496 /*
497 * Restore original instruction and clear BP
498 */
499 PROC_UNLOCK(p);
500 CTR3(KTR_PTRACE,
501 "ptrace_clear_single_step: tid %d, restore instr at %#lx: %#08x",
502 td->td_tid, td->td_md.md_ss_addr, td->td_md.md_ss_instr);
503 error = ptrace_write_int(td, td->td_md.md_ss_addr,
504 td->td_md.md_ss_instr);
505 PROC_LOCK(p);
506
507 /* The sync'ing of I & D caches is done by proc_rwmem(). */
508
509 if (error != 0) {
510 log(LOG_ERR,
511 "SS %s %d: can't restore instruction at %p: %x\n",
512 p->p_comm, p->p_pid, (void *)td->td_md.md_ss_addr,
513 td->td_md.md_ss_instr);
514 }
515 td->td_md.md_ss_addr = 0;
516 return 0;
517 }
Cache object: 45af0a81e64890699057ace3d31d4788
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