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sys/mips/mips/pmap.c
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1 /* 2 * Copyright (c) 1991 Regents of the University of California. 3 * All rights reserved. 4 * Copyright (c) 1994 John S. Dyson 5 * All rights reserved. 6 * Copyright (c) 1994 David Greenman 7 * All rights reserved. 8 * 9 * This code is derived from software contributed to Berkeley by 10 * the Systems Programming Group of the University of Utah Computer 11 * Science Department and William Jolitz of UUNET Technologies Inc. 12 * 13 * Redistribution and use in source and binary forms, with or without 14 * modification, are permitted provided that the following conditions 15 * are met: 16 * 1. Redistributions of source code must retain the above copyright 17 * notice, this list of conditions and the following disclaimer. 18 * 2. Redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution. 21 * 4. Neither the name of the University nor the names of its contributors 22 * may be used to endorse or promote products derived from this software 23 * without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 27 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 28 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 29 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 30 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 31 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 32 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 33 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 34 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 35 * SUCH DAMAGE. 36 * 37 * from: @(#)pmap.c 7.7 (Berkeley) 5/12/91 38 * from: src/sys/i386/i386/pmap.c,v 1.250.2.8 2000/11/21 00:09:14 ps 39 * JNPR: pmap.c,v 1.11.2.1 2007/08/16 11:51:06 girish 40 */ 41 42 /* 43 * Manages physical address maps. 44 * 45 * Since the information managed by this module is 46 * also stored by the logical address mapping module, 47 * this module may throw away valid virtual-to-physical 48 * mappings at almost any time. However, invalidations 49 * of virtual-to-physical mappings must be done as 50 * requested. 51 * 52 * In order to cope with hardware architectures which 53 * make virtual-to-physical map invalidates expensive, 54 * this module may delay invalidate or reduced protection 55 * operations until such time as they are actually 56 * necessary. This module is given full information as 57 * to which processors are currently using which maps, 58 * and to when physical maps must be made correct. 59 */ 60 61 #include <sys/cdefs.h> 62 __FBSDID("$FreeBSD: releng/10.2/sys/mips/mips/pmap.c 270920 2014-09-01 07:58:15Z kib $"); 63 64 #include "opt_ddb.h" 65 #include "opt_pmap.h" 66 67 #include <sys/param.h> 68 #include <sys/systm.h> 69 #include <sys/lock.h> 70 #include <sys/mman.h> 71 #include <sys/msgbuf.h> 72 #include <sys/mutex.h> 73 #include <sys/pcpu.h> 74 #include <sys/proc.h> 75 #include <sys/rwlock.h> 76 #include <sys/sched.h> 77 #ifdef SMP 78 #include <sys/smp.h> 79 #else 80 #include <sys/cpuset.h> 81 #endif 82 #include <sys/sysctl.h> 83 #include <sys/vmmeter.h> 84 85 #ifdef DDB 86 #include <ddb/ddb.h> 87 #endif 88 89 #include <vm/vm.h> 90 #include <vm/vm_param.h> 91 #include <vm/vm_kern.h> 92 #include <vm/vm_page.h> 93 #include <vm/vm_map.h> 94 #include <vm/vm_object.h> 95 #include <vm/vm_extern.h> 96 #include <vm/vm_pageout.h> 97 #include <vm/vm_pager.h> 98 #include <vm/uma.h> 99 100 #include <machine/cache.h> 101 #include <machine/md_var.h> 102 #include <machine/tlb.h> 103 104 #undef PMAP_DEBUG 105 106 #if !defined(DIAGNOSTIC) 107 #define PMAP_INLINE __inline 108 #else 109 #define PMAP_INLINE 110 #endif 111 112 #ifdef PV_STATS 113 #define PV_STAT(x) do { x ; } while (0) 114 #else 115 #define PV_STAT(x) do { } while (0) 116 #endif 117 118 /* 119 * Get PDEs and PTEs for user/kernel address space 120 */ 121 #define pmap_seg_index(v) (((v) >> SEGSHIFT) & (NPDEPG - 1)) 122 #define pmap_pde_index(v) (((v) >> PDRSHIFT) & (NPDEPG - 1)) 123 #define pmap_pte_index(v) (((v) >> PAGE_SHIFT) & (NPTEPG - 1)) 124 #define pmap_pde_pindex(v) ((v) >> PDRSHIFT) 125 126 #ifdef __mips_n64 127 #define NUPDE (NPDEPG * NPDEPG) 128 #define NUSERPGTBLS (NUPDE + NPDEPG) 129 #else 130 #define NUPDE (NPDEPG) 131 #define NUSERPGTBLS (NUPDE) 132 #endif 133 134 #define is_kernel_pmap(x) ((x) == kernel_pmap) 135 136 struct pmap kernel_pmap_store; 137 pd_entry_t *kernel_segmap; 138 139 vm_offset_t virtual_avail; /* VA of first avail page (after kernel bss) */ 140 vm_offset_t virtual_end; /* VA of last avail page (end of kernel AS) */ 141 142 static int nkpt; 143 unsigned pmap_max_asid; /* max ASID supported by the system */ 144 145 #define PMAP_ASID_RESERVED 0 146 147 vm_offset_t kernel_vm_end = VM_MIN_KERNEL_ADDRESS; 148 149 static void pmap_asid_alloc(pmap_t pmap); 150 151 static struct rwlock_padalign pvh_global_lock; 152 153 /* 154 * Data for the pv entry allocation mechanism 155 */ 156 static TAILQ_HEAD(pch, pv_chunk) pv_chunks = TAILQ_HEAD_INITIALIZER(pv_chunks); 157 static int pv_entry_count; 158 159 static void free_pv_chunk(struct pv_chunk *pc); 160 static void free_pv_entry(pmap_t pmap, pv_entry_t pv); 161 static pv_entry_t get_pv_entry(pmap_t pmap, boolean_t try); 162 static vm_page_t pmap_pv_reclaim(pmap_t locked_pmap); 163 static void pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va); 164 static pv_entry_t pmap_pvh_remove(struct md_page *pvh, pmap_t pmap, 165 vm_offset_t va); 166 static vm_page_t pmap_alloc_direct_page(unsigned int index, int req); 167 static vm_page_t pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va, 168 vm_page_t m, vm_prot_t prot, vm_page_t mpte); 169 static int pmap_remove_pte(struct pmap *pmap, pt_entry_t *ptq, vm_offset_t va, 170 pd_entry_t pde); 171 static void pmap_remove_page(struct pmap *pmap, vm_offset_t va); 172 static void pmap_remove_entry(struct pmap *pmap, vm_page_t m, vm_offset_t va); 173 static boolean_t pmap_try_insert_pv_entry(pmap_t pmap, vm_page_t mpte, 174 vm_offset_t va, vm_page_t m); 175 static void pmap_update_page(pmap_t pmap, vm_offset_t va, pt_entry_t pte); 176 static void pmap_invalidate_all(pmap_t pmap); 177 static void pmap_invalidate_page(pmap_t pmap, vm_offset_t va); 178 static void _pmap_unwire_ptp(pmap_t pmap, vm_offset_t va, vm_page_t m); 179 180 static vm_page_t pmap_allocpte(pmap_t pmap, vm_offset_t va, u_int flags); 181 static vm_page_t _pmap_allocpte(pmap_t pmap, unsigned ptepindex, u_int flags); 182 static int pmap_unuse_pt(pmap_t, vm_offset_t, pd_entry_t); 183 static pt_entry_t init_pte_prot(vm_page_t m, vm_prot_t access, vm_prot_t prot); 184 185 static void pmap_invalidate_page_action(void *arg); 186 static void pmap_invalidate_range_action(void *arg); 187 static void pmap_update_page_action(void *arg); 188 189 #ifndef __mips_n64 190 /* 191 * This structure is for high memory (memory above 512Meg in 32 bit) support. 192 * The highmem area does not have a KSEG0 mapping, and we need a mechanism to 193 * do temporary per-CPU mappings for pmap_zero_page, pmap_copy_page etc. 194 * 195 * At bootup, we reserve 2 virtual pages per CPU for mapping highmem pages. To 196 * access a highmem physical address on a CPU, we map the physical address to 197 * the reserved virtual address for the CPU in the kernel pagetable. This is 198 * done with interrupts disabled(although a spinlock and sched_pin would be 199 * sufficient). 200 */ 201 struct local_sysmaps { 202 vm_offset_t base; 203 uint32_t saved_intr; 204 uint16_t valid1, valid2; 205 }; 206 static struct local_sysmaps sysmap_lmem[MAXCPU]; 207 208 static __inline void 209 pmap_alloc_lmem_map(void) 210 { 211 int i; 212 213 for (i = 0; i < MAXCPU; i++) { 214 sysmap_lmem[i].base = virtual_avail; 215 virtual_avail += PAGE_SIZE * 2; 216 sysmap_lmem[i].valid1 = sysmap_lmem[i].valid2 = 0; 217 } 218 } 219 220 static __inline vm_offset_t 221 pmap_lmem_map1(vm_paddr_t phys) 222 { 223 struct local_sysmaps *sysm; 224 pt_entry_t *pte, npte; 225 vm_offset_t va; 226 uint32_t intr; 227 int cpu; 228 229 intr = intr_disable(); 230 cpu = PCPU_GET(cpuid); 231 sysm = &sysmap_lmem[cpu]; 232 sysm->saved_intr = intr; 233 va = sysm->base; 234 npte = TLBLO_PA_TO_PFN(phys) | PTE_C_CACHE | PTE_D | PTE_V | PTE_G; 235 pte = pmap_pte(kernel_pmap, va); 236 *pte = npte; 237 sysm->valid1 = 1; 238 return (va); 239 } 240 241 static __inline vm_offset_t 242 pmap_lmem_map2(vm_paddr_t phys1, vm_paddr_t phys2) 243 { 244 struct local_sysmaps *sysm; 245 pt_entry_t *pte, npte; 246 vm_offset_t va1, va2; 247 uint32_t intr; 248 int cpu; 249 250 intr = intr_disable(); 251 cpu = PCPU_GET(cpuid); 252 sysm = &sysmap_lmem[cpu]; 253 sysm->saved_intr = intr; 254 va1 = sysm->base; 255 va2 = sysm->base + PAGE_SIZE; 256 npte = TLBLO_PA_TO_PFN(phys1) | PTE_C_CACHE | PTE_D | PTE_V | PTE_G; 257 pte = pmap_pte(kernel_pmap, va1); 258 *pte = npte; 259 npte = TLBLO_PA_TO_PFN(phys2) | PTE_C_CACHE | PTE_D | PTE_V | PTE_G; 260 pte = pmap_pte(kernel_pmap, va2); 261 *pte = npte; 262 sysm->valid1 = 1; 263 sysm->valid2 = 1; 264 return (va1); 265 } 266 267 static __inline void 268 pmap_lmem_unmap(void) 269 { 270 struct local_sysmaps *sysm; 271 pt_entry_t *pte; 272 int cpu; 273 274 cpu = PCPU_GET(cpuid); 275 sysm = &sysmap_lmem[cpu]; 276 pte = pmap_pte(kernel_pmap, sysm->base); 277 *pte = PTE_G; 278 tlb_invalidate_address(kernel_pmap, sysm->base); 279 sysm->valid1 = 0; 280 if (sysm->valid2) { 281 pte = pmap_pte(kernel_pmap, sysm->base + PAGE_SIZE); 282 *pte = PTE_G; 283 tlb_invalidate_address(kernel_pmap, sysm->base + PAGE_SIZE); 284 sysm->valid2 = 0; 285 } 286 intr_restore(sysm->saved_intr); 287 } 288 #else /* __mips_n64 */ 289 290 static __inline void 291 pmap_alloc_lmem_map(void) 292 { 293 } 294 295 static __inline vm_offset_t 296 pmap_lmem_map1(vm_paddr_t phys) 297 { 298 299 return (0); 300 } 301 302 static __inline vm_offset_t 303 pmap_lmem_map2(vm_paddr_t phys1, vm_paddr_t phys2) 304 { 305 306 return (0); 307 } 308 309 static __inline vm_offset_t 310 pmap_lmem_unmap(void) 311 { 312 313 return (0); 314 } 315 #endif /* !__mips_n64 */ 316 317 /* 318 * Page table entry lookup routines. 319 */ 320 static __inline pd_entry_t * 321 pmap_segmap(pmap_t pmap, vm_offset_t va) 322 { 323 324 return (&pmap->pm_segtab[pmap_seg_index(va)]); 325 } 326 327 #ifdef __mips_n64 328 static __inline pd_entry_t * 329 pmap_pdpe_to_pde(pd_entry_t *pdpe, vm_offset_t va) 330 { 331 pd_entry_t *pde; 332 333 pde = (pd_entry_t *)*pdpe; 334 return (&pde[pmap_pde_index(va)]); 335 } 336 337 static __inline pd_entry_t * 338 pmap_pde(pmap_t pmap, vm_offset_t va) 339 { 340 pd_entry_t *pdpe; 341 342 pdpe = pmap_segmap(pmap, va); 343 if (*pdpe == NULL) 344 return (NULL); 345 346 return (pmap_pdpe_to_pde(pdpe, va)); 347 } 348 #else 349 static __inline pd_entry_t * 350 pmap_pdpe_to_pde(pd_entry_t *pdpe, vm_offset_t va) 351 { 352 353 return (pdpe); 354 } 355 356 static __inline 357 pd_entry_t *pmap_pde(pmap_t pmap, vm_offset_t va) 358 { 359 360 return (pmap_segmap(pmap, va)); 361 } 362 #endif 363 364 static __inline pt_entry_t * 365 pmap_pde_to_pte(pd_entry_t *pde, vm_offset_t va) 366 { 367 pt_entry_t *pte; 368 369 pte = (pt_entry_t *)*pde; 370 return (&pte[pmap_pte_index(va)]); 371 } 372 373 pt_entry_t * 374 pmap_pte(pmap_t pmap, vm_offset_t va) 375 { 376 pd_entry_t *pde; 377 378 pde = pmap_pde(pmap, va); 379 if (pde == NULL || *pde == NULL) 380 return (NULL); 381 382 return (pmap_pde_to_pte(pde, va)); 383 } 384 385 vm_offset_t 386 pmap_steal_memory(vm_size_t size) 387 { 388 vm_paddr_t bank_size, pa; 389 vm_offset_t va; 390 391 size = round_page(size); 392 bank_size = phys_avail[1] - phys_avail[0]; 393 while (size > bank_size) { 394 int i; 395 396 for (i = 0; phys_avail[i + 2]; i += 2) { 397 phys_avail[i] = phys_avail[i + 2]; 398 phys_avail[i + 1] = phys_avail[i + 3]; 399 } 400 phys_avail[i] = 0; 401 phys_avail[i + 1] = 0; 402 if (!phys_avail[0]) 403 panic("pmap_steal_memory: out of memory"); 404 bank_size = phys_avail[1] - phys_avail[0]; 405 } 406 407 pa = phys_avail[0]; 408 phys_avail[0] += size; 409 if (MIPS_DIRECT_MAPPABLE(pa) == 0) 410 panic("Out of memory below 512Meg?"); 411 va = MIPS_PHYS_TO_DIRECT(pa); 412 bzero((caddr_t)va, size); 413 return (va); 414 } 415 416 /* 417 * Bootstrap the system enough to run with virtual memory. This 418 * assumes that the phys_avail array has been initialized. 419 */ 420 static void 421 pmap_create_kernel_pagetable(void) 422 { 423 int i, j; 424 vm_offset_t ptaddr; 425 pt_entry_t *pte; 426 #ifdef __mips_n64 427 pd_entry_t *pde; 428 vm_offset_t pdaddr; 429 int npt, npde; 430 #endif 431 432 /* 433 * Allocate segment table for the kernel 434 */ 435 kernel_segmap = (pd_entry_t *)pmap_steal_memory(PAGE_SIZE); 436 437 /* 438 * Allocate second level page tables for the kernel 439 */ 440 #ifdef __mips_n64 441 npde = howmany(NKPT, NPDEPG); 442 pdaddr = pmap_steal_memory(PAGE_SIZE * npde); 443 #endif 444 nkpt = NKPT; 445 ptaddr = pmap_steal_memory(PAGE_SIZE * nkpt); 446 447 /* 448 * The R[4-7]?00 stores only one copy of the Global bit in the 449 * translation lookaside buffer for each 2 page entry. Thus invalid 450 * entrys must have the Global bit set so when Entry LO and Entry HI 451 * G bits are anded together they will produce a global bit to store 452 * in the tlb. 453 */ 454 for (i = 0, pte = (pt_entry_t *)ptaddr; i < (nkpt * NPTEPG); i++, pte++) 455 *pte = PTE_G; 456 457 #ifdef __mips_n64 458 for (i = 0, npt = nkpt; npt > 0; i++) { 459 kernel_segmap[i] = (pd_entry_t)(pdaddr + i * PAGE_SIZE); 460 pde = (pd_entry_t *)kernel_segmap[i]; 461 462 for (j = 0; j < NPDEPG && npt > 0; j++, npt--) 463 pde[j] = (pd_entry_t)(ptaddr + (i * NPDEPG + j) * PAGE_SIZE); 464 } 465 #else 466 for (i = 0, j = pmap_seg_index(VM_MIN_KERNEL_ADDRESS); i < nkpt; i++, j++) 467 kernel_segmap[j] = (pd_entry_t)(ptaddr + (i * PAGE_SIZE)); 468 #endif 469 470 PMAP_LOCK_INIT(kernel_pmap); 471 kernel_pmap->pm_segtab = kernel_segmap; 472 CPU_FILL(&kernel_pmap->pm_active); 473 TAILQ_INIT(&kernel_pmap->pm_pvchunk); 474 kernel_pmap->pm_asid[0].asid = PMAP_ASID_RESERVED; 475 kernel_pmap->pm_asid[0].gen = 0; 476 kernel_vm_end += nkpt * NPTEPG * PAGE_SIZE; 477 } 478 479 void 480 pmap_bootstrap(void) 481 { 482 int i; 483 int need_local_mappings = 0; 484 485 /* Sort. */ 486 again: 487 for (i = 0; phys_avail[i + 1] != 0; i += 2) { 488 /* 489 * Keep the memory aligned on page boundary. 490 */ 491 phys_avail[i] = round_page(phys_avail[i]); 492 phys_avail[i + 1] = trunc_page(phys_avail[i + 1]); 493 494 if (i < 2) 495 continue; 496 if (phys_avail[i - 2] > phys_avail[i]) { 497 vm_paddr_t ptemp[2]; 498 499 ptemp[0] = phys_avail[i + 0]; 500 ptemp[1] = phys_avail[i + 1]; 501 502 phys_avail[i + 0] = phys_avail[i - 2]; 503 phys_avail[i + 1] = phys_avail[i - 1]; 504 505 phys_avail[i - 2] = ptemp[0]; 506 phys_avail[i - 1] = ptemp[1]; 507 goto again; 508 } 509 } 510 511 /* 512 * In 32 bit, we may have memory which cannot be mapped directly. 513 * This memory will need temporary mapping before it can be 514 * accessed. 515 */ 516 if (!MIPS_DIRECT_MAPPABLE(phys_avail[i - 1] - 1)) 517 need_local_mappings = 1; 518 519 /* 520 * Copy the phys_avail[] array before we start stealing memory from it. 521 */ 522 for (i = 0; phys_avail[i + 1] != 0; i += 2) { 523 physmem_desc[i] = phys_avail[i]; 524 physmem_desc[i + 1] = phys_avail[i + 1]; 525 } 526 527 Maxmem = atop(phys_avail[i - 1]); 528 529 if (bootverbose) { 530 printf("Physical memory chunk(s):\n"); 531 for (i = 0; phys_avail[i + 1] != 0; i += 2) { 532 vm_paddr_t size; 533 534 size = phys_avail[i + 1] - phys_avail[i]; 535 printf("%#08jx - %#08jx, %ju bytes (%ju pages)\n", 536 (uintmax_t) phys_avail[i], 537 (uintmax_t) phys_avail[i + 1] - 1, 538 (uintmax_t) size, (uintmax_t) size / PAGE_SIZE); 539 } 540 printf("Maxmem is 0x%0jx\n", ptoa((uintmax_t)Maxmem)); 541 } 542 /* 543 * Steal the message buffer from the beginning of memory. 544 */ 545 msgbufp = (struct msgbuf *)pmap_steal_memory(msgbufsize); 546 msgbufinit(msgbufp, msgbufsize); 547 548 /* 549 * Steal thread0 kstack. 550 */ 551 kstack0 = pmap_steal_memory(KSTACK_PAGES << PAGE_SHIFT); 552 553 virtual_avail = VM_MIN_KERNEL_ADDRESS; 554 virtual_end = VM_MAX_KERNEL_ADDRESS; 555 556 #ifdef SMP 557 /* 558 * Steal some virtual address space to map the pcpu area. 559 */ 560 virtual_avail = roundup2(virtual_avail, PAGE_SIZE * 2); 561 pcpup = (struct pcpu *)virtual_avail; 562 virtual_avail += PAGE_SIZE * 2; 563 564 /* 565 * Initialize the wired TLB entry mapping the pcpu region for 566 * the BSP at 'pcpup'. Up until this point we were operating 567 * with the 'pcpup' for the BSP pointing to a virtual address 568 * in KSEG0 so there was no need for a TLB mapping. 569 */ 570 mips_pcpu_tlb_init(PCPU_ADDR(0)); 571 572 if (bootverbose) 573 printf("pcpu is available at virtual address %p.\n", pcpup); 574 #endif 575 576 if (need_local_mappings) 577 pmap_alloc_lmem_map(); 578 pmap_create_kernel_pagetable(); 579 pmap_max_asid = VMNUM_PIDS; 580 mips_wr_entryhi(0); 581 mips_wr_pagemask(0); 582 583 /* 584 * Initialize the global pv list lock. 585 */ 586 rw_init(&pvh_global_lock, "pmap pv global"); 587 } 588 589 /* 590 * Initialize a vm_page's machine-dependent fields. 591 */ 592 void 593 pmap_page_init(vm_page_t m) 594 { 595 596 TAILQ_INIT(&m->md.pv_list); 597 m->md.pv_flags = 0; 598 } 599 600 /* 601 * Initialize the pmap module. 602 * Called by vm_init, to initialize any structures that the pmap 603 * system needs to map virtual memory. 604 */ 605 void 606 pmap_init(void) 607 { 608 } 609 610 /*************************************************** 611 * Low level helper routines..... 612 ***************************************************/ 613 614 #ifdef SMP 615 static __inline void 616 pmap_call_on_active_cpus(pmap_t pmap, void (*fn)(void *), void *arg) 617 { 618 int cpuid, cpu, self; 619 cpuset_t active_cpus; 620 621 sched_pin(); 622 if (is_kernel_pmap(pmap)) { 623 smp_rendezvous(NULL, fn, NULL, arg); 624 goto out; 625 } 626 /* Force ASID update on inactive CPUs */ 627 CPU_FOREACH(cpu) { 628 if (!CPU_ISSET(cpu, &pmap->pm_active)) 629 pmap->pm_asid[cpu].gen = 0; 630 } 631 cpuid = PCPU_GET(cpuid); 632 /* 633 * XXX: barrier/locking for active? 634 * 635 * Take a snapshot of active here, any further changes are ignored. 636 * tlb update/invalidate should be harmless on inactive CPUs 637 */ 638 active_cpus = pmap->pm_active; 639 self = CPU_ISSET(cpuid, &active_cpus); 640 CPU_CLR(cpuid, &active_cpus); 641 /* Optimize for the case where this cpu is the only active one */ 642 if (CPU_EMPTY(&active_cpus)) { 643 if (self) 644 fn(arg); 645 } else { 646 if (self) 647 CPU_SET(cpuid, &active_cpus); 648 smp_rendezvous_cpus(active_cpus, NULL, fn, NULL, arg); 649 } 650 out: 651 sched_unpin(); 652 } 653 #else /* !SMP */ 654 static __inline void 655 pmap_call_on_active_cpus(pmap_t pmap, void (*fn)(void *), void *arg) 656 { 657 int cpuid; 658 659 if (is_kernel_pmap(pmap)) { 660 fn(arg); 661 return; 662 } 663 cpuid = PCPU_GET(cpuid); 664 if (!CPU_ISSET(cpuid, &pmap->pm_active)) 665 pmap->pm_asid[cpuid].gen = 0; 666 else 667 fn(arg); 668 } 669 #endif /* SMP */ 670 671 static void 672 pmap_invalidate_all(pmap_t pmap) 673 { 674 675 pmap_call_on_active_cpus(pmap, 676 (void (*)(void *))tlb_invalidate_all_user, pmap); 677 } 678 679 struct pmap_invalidate_page_arg { 680 pmap_t pmap; 681 vm_offset_t va; 682 }; 683 684 static void 685 pmap_invalidate_page_action(void *arg) 686 { 687 struct pmap_invalidate_page_arg *p = arg; 688 689 tlb_invalidate_address(p->pmap, p->va); 690 } 691 692 static void 693 pmap_invalidate_page(pmap_t pmap, vm_offset_t va) 694 { 695 struct pmap_invalidate_page_arg arg; 696 697 arg.pmap = pmap; 698 arg.va = va; 699 pmap_call_on_active_cpus(pmap, pmap_invalidate_page_action, &arg); 700 } 701 702 struct pmap_invalidate_range_arg { 703 pmap_t pmap; 704 vm_offset_t sva; 705 vm_offset_t eva; 706 }; 707 708 static void 709 pmap_invalidate_range_action(void *arg) 710 { 711 struct pmap_invalidate_range_arg *p = arg; 712 713 tlb_invalidate_range(p->pmap, p->sva, p->eva); 714 } 715 716 static void 717 pmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva) 718 { 719 struct pmap_invalidate_range_arg arg; 720 721 arg.pmap = pmap; 722 arg.sva = sva; 723 arg.eva = eva; 724 pmap_call_on_active_cpus(pmap, pmap_invalidate_range_action, &arg); 725 } 726 727 struct pmap_update_page_arg { 728 pmap_t pmap; 729 vm_offset_t va; 730 pt_entry_t pte; 731 }; 732 733 static void 734 pmap_update_page_action(void *arg) 735 { 736 struct pmap_update_page_arg *p = arg; 737 738 tlb_update(p->pmap, p->va, p->pte); 739 } 740 741 static void 742 pmap_update_page(pmap_t pmap, vm_offset_t va, pt_entry_t pte) 743 { 744 struct pmap_update_page_arg arg; 745 746 arg.pmap = pmap; 747 arg.va = va; 748 arg.pte = pte; 749 pmap_call_on_active_cpus(pmap, pmap_update_page_action, &arg); 750 } 751 752 /* 753 * Routine: pmap_extract 754 * Function: 755 * Extract the physical page address associated 756 * with the given map/virtual_address pair. 757 */ 758 vm_paddr_t 759 pmap_extract(pmap_t pmap, vm_offset_t va) 760 { 761 pt_entry_t *pte; 762 vm_offset_t retval = 0; 763 764 PMAP_LOCK(pmap); 765 pte = pmap_pte(pmap, va); 766 if (pte) { 767 retval = TLBLO_PTE_TO_PA(*pte) | (va & PAGE_MASK); 768 } 769 PMAP_UNLOCK(pmap); 770 return (retval); 771 } 772 773 /* 774 * Routine: pmap_extract_and_hold 775 * Function: 776 * Atomically extract and hold the physical page 777 * with the given pmap and virtual address pair 778 * if that mapping permits the given protection. 779 */ 780 vm_page_t 781 pmap_extract_and_hold(pmap_t pmap, vm_offset_t va, vm_prot_t prot) 782 { 783 pt_entry_t pte, *ptep; 784 vm_paddr_t pa, pte_pa; 785 vm_page_t m; 786 787 m = NULL; 788 pa = 0; 789 PMAP_LOCK(pmap); 790 retry: 791 ptep = pmap_pte(pmap, va); 792 if (ptep != NULL) { 793 pte = *ptep; 794 if (pte_test(&pte, PTE_V) && (!pte_test(&pte, PTE_RO) || 795 (prot & VM_PROT_WRITE) == 0)) { 796 pte_pa = TLBLO_PTE_TO_PA(pte); 797 if (vm_page_pa_tryrelock(pmap, pte_pa, &pa)) 798 goto retry; 799 m = PHYS_TO_VM_PAGE(pte_pa); 800 vm_page_hold(m); 801 } 802 } 803 PA_UNLOCK_COND(pa); 804 PMAP_UNLOCK(pmap); 805 return (m); 806 } 807 808 /*************************************************** 809 * Low level mapping routines..... 810 ***************************************************/ 811 812 /* 813 * add a wired page to the kva 814 */ 815 void 816 pmap_kenter_attr(vm_offset_t va, vm_paddr_t pa, int attr) 817 { 818 pt_entry_t *pte; 819 pt_entry_t opte, npte; 820 821 #ifdef PMAP_DEBUG 822 printf("pmap_kenter: va: %p -> pa: %p\n", (void *)va, (void *)pa); 823 #endif 824 825 pte = pmap_pte(kernel_pmap, va); 826 opte = *pte; 827 npte = TLBLO_PA_TO_PFN(pa) | attr | PTE_D | PTE_V | PTE_G; 828 *pte = npte; 829 if (pte_test(&opte, PTE_V) && opte != npte) 830 pmap_update_page(kernel_pmap, va, npte); 831 } 832 833 void 834 pmap_kenter(vm_offset_t va, vm_paddr_t pa) 835 { 836 837 KASSERT(is_cacheable_mem(pa), 838 ("pmap_kenter: memory at 0x%lx is not cacheable", (u_long)pa)); 839 840 pmap_kenter_attr(va, pa, PTE_C_CACHE); 841 } 842 843 /* 844 * remove a page from the kernel pagetables 845 */ 846 /* PMAP_INLINE */ void 847 pmap_kremove(vm_offset_t va) 848 { 849 pt_entry_t *pte; 850 851 /* 852 * Write back all caches from the page being destroyed 853 */ 854 mips_dcache_wbinv_range_index(va, PAGE_SIZE); 855 856 pte = pmap_pte(kernel_pmap, va); 857 *pte = PTE_G; 858 pmap_invalidate_page(kernel_pmap, va); 859 } 860 861 /* 862 * Used to map a range of physical addresses into kernel 863 * virtual address space. 864 * 865 * The value passed in '*virt' is a suggested virtual address for 866 * the mapping. Architectures which can support a direct-mapped 867 * physical to virtual region can return the appropriate address 868 * within that region, leaving '*virt' unchanged. Other 869 * architectures should map the pages starting at '*virt' and 870 * update '*virt' with the first usable address after the mapped 871 * region. 872 * 873 * Use XKPHYS for 64 bit, and KSEG0 where possible for 32 bit. 874 */ 875 vm_offset_t 876 pmap_map(vm_offset_t *virt, vm_paddr_t start, vm_paddr_t end, int prot) 877 { 878 vm_offset_t va, sva; 879 880 if (MIPS_DIRECT_MAPPABLE(end - 1)) 881 return (MIPS_PHYS_TO_DIRECT(start)); 882 883 va = sva = *virt; 884 while (start < end) { 885 pmap_kenter(va, start); 886 va += PAGE_SIZE; 887 start += PAGE_SIZE; 888 } 889 *virt = va; 890 return (sva); 891 } 892 893 /* 894 * Add a list of wired pages to the kva 895 * this routine is only used for temporary 896 * kernel mappings that do not need to have 897 * page modification or references recorded. 898 * Note that old mappings are simply written 899 * over. The page *must* be wired. 900 */ 901 void 902 pmap_qenter(vm_offset_t va, vm_page_t *m, int count) 903 { 904 int i; 905 vm_offset_t origva = va; 906 907 for (i = 0; i < count; i++) { 908 pmap_flush_pvcache(m[i]); 909 pmap_kenter(va, VM_PAGE_TO_PHYS(m[i])); 910 va += PAGE_SIZE; 911 } 912 913 mips_dcache_wbinv_range_index(origva, PAGE_SIZE*count); 914 } 915 916 /* 917 * this routine jerks page mappings from the 918 * kernel -- it is meant only for temporary mappings. 919 */ 920 void 921 pmap_qremove(vm_offset_t va, int count) 922 { 923 pt_entry_t *pte; 924 vm_offset_t origva; 925 926 if (count < 1) 927 return; 928 mips_dcache_wbinv_range_index(va, PAGE_SIZE * count); 929 origva = va; 930 do { 931 pte = pmap_pte(kernel_pmap, va); 932 *pte = PTE_G; 933 va += PAGE_SIZE; 934 } while (--count > 0); 935 pmap_invalidate_range(kernel_pmap, origva, va); 936 } 937 938 /*************************************************** 939 * Page table page management routines..... 940 ***************************************************/ 941 942 /* 943 * Decrements a page table page's wire count, which is used to record the 944 * number of valid page table entries within the page. If the wire count 945 * drops to zero, then the page table page is unmapped. Returns TRUE if the 946 * page table page was unmapped and FALSE otherwise. 947 */ 948 static PMAP_INLINE boolean_t 949 pmap_unwire_ptp(pmap_t pmap, vm_offset_t va, vm_page_t m) 950 { 951 952 --m->wire_count; 953 if (m->wire_count == 0) { 954 _pmap_unwire_ptp(pmap, va, m); 955 return (TRUE); 956 } else 957 return (FALSE); 958 } 959 960 static void 961 _pmap_unwire_ptp(pmap_t pmap, vm_offset_t va, vm_page_t m) 962 { 963 pd_entry_t *pde; 964 965 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 966 /* 967 * unmap the page table page 968 */ 969 #ifdef __mips_n64 970 if (m->pindex < NUPDE) 971 pde = pmap_pde(pmap, va); 972 else 973 pde = pmap_segmap(pmap, va); 974 #else 975 pde = pmap_pde(pmap, va); 976 #endif 977 *pde = 0; 978 pmap->pm_stats.resident_count--; 979 980 #ifdef __mips_n64 981 if (m->pindex < NUPDE) { 982 pd_entry_t *pdp; 983 vm_page_t pdpg; 984 985 /* 986 * Recursively decrement next level pagetable refcount 987 */ 988 pdp = (pd_entry_t *)*pmap_segmap(pmap, va); 989 pdpg = PHYS_TO_VM_PAGE(MIPS_DIRECT_TO_PHYS(pdp)); 990 pmap_unwire_ptp(pmap, va, pdpg); 991 } 992 #endif 993 994 /* 995 * If the page is finally unwired, simply free it. 996 */ 997 vm_page_free_zero(m); 998 atomic_subtract_int(&cnt.v_wire_count, 1); 999 } 1000 1001 /* 1002 * After removing a page table entry, this routine is used to 1003 * conditionally free the page, and manage the hold/wire counts. 1004 */ 1005 static int 1006 pmap_unuse_pt(pmap_t pmap, vm_offset_t va, pd_entry_t pde) 1007 { 1008 vm_page_t mpte; 1009 1010 if (va >= VM_MAXUSER_ADDRESS) 1011 return (0); 1012 KASSERT(pde != 0, ("pmap_unuse_pt: pde != 0")); 1013 mpte = PHYS_TO_VM_PAGE(MIPS_DIRECT_TO_PHYS(pde)); 1014 return (pmap_unwire_ptp(pmap, va, mpte)); 1015 } 1016 1017 void 1018 pmap_pinit0(pmap_t pmap) 1019 { 1020 int i; 1021 1022 PMAP_LOCK_INIT(pmap); 1023 pmap->pm_segtab = kernel_segmap; 1024 CPU_ZERO(&pmap->pm_active); 1025 for (i = 0; i < MAXCPU; i++) { 1026 pmap->pm_asid[i].asid = PMAP_ASID_RESERVED; 1027 pmap->pm_asid[i].gen = 0; 1028 } 1029 PCPU_SET(curpmap, pmap); 1030 TAILQ_INIT(&pmap->pm_pvchunk); 1031 bzero(&pmap->pm_stats, sizeof pmap->pm_stats); 1032 } 1033 1034 void 1035 pmap_grow_direct_page_cache() 1036 { 1037 1038 #ifdef __mips_n64 1039 vm_pageout_grow_cache(3, 0, MIPS_XKPHYS_LARGEST_PHYS); 1040 #else 1041 vm_pageout_grow_cache(3, 0, MIPS_KSEG0_LARGEST_PHYS); 1042 #endif 1043 } 1044 1045 static vm_page_t 1046 pmap_alloc_direct_page(unsigned int index, int req) 1047 { 1048 vm_page_t m; 1049 1050 m = vm_page_alloc_freelist(VM_FREELIST_DIRECT, req | VM_ALLOC_WIRED | 1051 VM_ALLOC_ZERO); 1052 if (m == NULL) 1053 return (NULL); 1054 1055 if ((m->flags & PG_ZERO) == 0) 1056 pmap_zero_page(m); 1057 1058 m->pindex = index; 1059 return (m); 1060 } 1061 1062 /* 1063 * Initialize a preallocated and zeroed pmap structure, 1064 * such as one in a vmspace structure. 1065 */ 1066 int 1067 pmap_pinit(pmap_t pmap) 1068 { 1069 vm_offset_t ptdva; 1070 vm_page_t ptdpg; 1071 int i; 1072 1073 /* 1074 * allocate the page directory page 1075 */ 1076 while ((ptdpg = pmap_alloc_direct_page(NUSERPGTBLS, VM_ALLOC_NORMAL)) == NULL) 1077 pmap_grow_direct_page_cache(); 1078 1079 ptdva = MIPS_PHYS_TO_DIRECT(VM_PAGE_TO_PHYS(ptdpg)); 1080 pmap->pm_segtab = (pd_entry_t *)ptdva; 1081 CPU_ZERO(&pmap->pm_active); 1082 for (i = 0; i < MAXCPU; i++) { 1083 pmap->pm_asid[i].asid = PMAP_ASID_RESERVED; 1084 pmap->pm_asid[i].gen = 0; 1085 } 1086 TAILQ_INIT(&pmap->pm_pvchunk); 1087 bzero(&pmap->pm_stats, sizeof pmap->pm_stats); 1088 1089 return (1); 1090 } 1091 1092 /* 1093 * this routine is called if the page table page is not 1094 * mapped correctly. 1095 */ 1096 static vm_page_t 1097 _pmap_allocpte(pmap_t pmap, unsigned ptepindex, u_int flags) 1098 { 1099 vm_offset_t pageva; 1100 vm_page_t m; 1101 1102 /* 1103 * Find or fabricate a new pagetable page 1104 */ 1105 if ((m = pmap_alloc_direct_page(ptepindex, VM_ALLOC_NORMAL)) == NULL) { 1106 if ((flags & PMAP_ENTER_NOSLEEP) == 0) { 1107 PMAP_UNLOCK(pmap); 1108 rw_wunlock(&pvh_global_lock); 1109 pmap_grow_direct_page_cache(); 1110 rw_wlock(&pvh_global_lock); 1111 PMAP_LOCK(pmap); 1112 } 1113 1114 /* 1115 * Indicate the need to retry. While waiting, the page 1116 * table page may have been allocated. 1117 */ 1118 return (NULL); 1119 } 1120 1121 /* 1122 * Map the pagetable page into the process address space, if it 1123 * isn't already there. 1124 */ 1125 pageva = MIPS_PHYS_TO_DIRECT(VM_PAGE_TO_PHYS(m)); 1126 1127 #ifdef __mips_n64 1128 if (ptepindex >= NUPDE) { 1129 pmap->pm_segtab[ptepindex - NUPDE] = (pd_entry_t)pageva; 1130 } else { 1131 pd_entry_t *pdep, *pde; 1132 int segindex = ptepindex >> (SEGSHIFT - PDRSHIFT); 1133 int pdeindex = ptepindex & (NPDEPG - 1); 1134 vm_page_t pg; 1135 1136 pdep = &pmap->pm_segtab[segindex]; 1137 if (*pdep == NULL) { 1138 /* recurse for allocating page dir */ 1139 if (_pmap_allocpte(pmap, NUPDE + segindex, 1140 flags) == NULL) { 1141 /* alloc failed, release current */ 1142 --m->wire_count; 1143 atomic_subtract_int(&cnt.v_wire_count, 1); 1144 vm_page_free_zero(m); 1145 return (NULL); 1146 } 1147 } else { 1148 pg = PHYS_TO_VM_PAGE(MIPS_DIRECT_TO_PHYS(*pdep)); 1149 pg->wire_count++; 1150 } 1151 /* Next level entry */ 1152 pde = (pd_entry_t *)*pdep; 1153 pde[pdeindex] = (pd_entry_t)pageva; 1154 } 1155 #else 1156 pmap->pm_segtab[ptepindex] = (pd_entry_t)pageva; 1157 #endif 1158 pmap->pm_stats.resident_count++; 1159 return (m); 1160 } 1161 1162 static vm_page_t 1163 pmap_allocpte(pmap_t pmap, vm_offset_t va, u_int flags) 1164 { 1165 unsigned ptepindex; 1166 pd_entry_t *pde; 1167 vm_page_t m; 1168 1169 /* 1170 * Calculate pagetable page index 1171 */ 1172 ptepindex = pmap_pde_pindex(va); 1173 retry: 1174 /* 1175 * Get the page directory entry 1176 */ 1177 pde = pmap_pde(pmap, va); 1178 1179 /* 1180 * If the page table page is mapped, we just increment the hold 1181 * count, and activate it. 1182 */ 1183 if (pde != NULL && *pde != NULL) { 1184 m = PHYS_TO_VM_PAGE(MIPS_DIRECT_TO_PHYS(*pde)); 1185 m->wire_count++; 1186 } else { 1187 /* 1188 * Here if the pte page isn't mapped, or if it has been 1189 * deallocated. 1190 */ 1191 m = _pmap_allocpte(pmap, ptepindex, flags); 1192 if (m == NULL && (flags & PMAP_ENTER_NOSLEEP) == 0) 1193 goto retry; 1194 } 1195 return (m); 1196 } 1197 1198 1199 /*************************************************** 1200 * Pmap allocation/deallocation routines. 1201 ***************************************************/ 1202 1203 /* 1204 * Release any resources held by the given physical map. 1205 * Called when a pmap initialized by pmap_pinit is being released. 1206 * Should only be called if the map contains no valid mappings. 1207 */ 1208 void 1209 pmap_release(pmap_t pmap) 1210 { 1211 vm_offset_t ptdva; 1212 vm_page_t ptdpg; 1213 1214 KASSERT(pmap->pm_stats.resident_count == 0, 1215 ("pmap_release: pmap resident count %ld != 0", 1216 pmap->pm_stats.resident_count)); 1217 1218 ptdva = (vm_offset_t)pmap->pm_segtab; 1219 ptdpg = PHYS_TO_VM_PAGE(MIPS_DIRECT_TO_PHYS(ptdva)); 1220 1221 ptdpg->wire_count--; 1222 atomic_subtract_int(&cnt.v_wire_count, 1); 1223 vm_page_free_zero(ptdpg); 1224 } 1225 1226 /* 1227 * grow the number of kernel page table entries, if needed 1228 */ 1229 void 1230 pmap_growkernel(vm_offset_t addr) 1231 { 1232 vm_page_t nkpg; 1233 pd_entry_t *pde, *pdpe; 1234 pt_entry_t *pte; 1235 int i; 1236 1237 mtx_assert(&kernel_map->system_mtx, MA_OWNED); 1238 addr = roundup2(addr, NBSEG); 1239 if (addr - 1 >= kernel_map->max_offset) 1240 addr = kernel_map->max_offset; 1241 while (kernel_vm_end < addr) { 1242 pdpe = pmap_segmap(kernel_pmap, kernel_vm_end); 1243 #ifdef __mips_n64 1244 if (*pdpe == 0) { 1245 /* new intermediate page table entry */ 1246 nkpg = pmap_alloc_direct_page(nkpt, VM_ALLOC_INTERRUPT); 1247 if (nkpg == NULL) 1248 panic("pmap_growkernel: no memory to grow kernel"); 1249 *pdpe = (pd_entry_t)MIPS_PHYS_TO_DIRECT(VM_PAGE_TO_PHYS(nkpg)); 1250 continue; /* try again */ 1251 } 1252 #endif 1253 pde = pmap_pdpe_to_pde(pdpe, kernel_vm_end); 1254 if (*pde != 0) { 1255 kernel_vm_end = (kernel_vm_end + NBPDR) & ~PDRMASK; 1256 if (kernel_vm_end - 1 >= kernel_map->max_offset) { 1257 kernel_vm_end = kernel_map->max_offset; 1258 break; 1259 } 1260 continue; 1261 } 1262 1263 /* 1264 * This index is bogus, but out of the way 1265 */ 1266 nkpg = pmap_alloc_direct_page(nkpt, VM_ALLOC_INTERRUPT); 1267 if (!nkpg) 1268 panic("pmap_growkernel: no memory to grow kernel"); 1269 nkpt++; 1270 *pde = (pd_entry_t)MIPS_PHYS_TO_DIRECT(VM_PAGE_TO_PHYS(nkpg)); 1271 1272 /* 1273 * The R[4-7]?00 stores only one copy of the Global bit in 1274 * the translation lookaside buffer for each 2 page entry. 1275 * Thus invalid entrys must have the Global bit set so when 1276 * Entry LO and Entry HI G bits are anded together they will 1277 * produce a global bit to store in the tlb. 1278 */ 1279 pte = (pt_entry_t *)*pde; 1280 for (i = 0; i < NPTEPG; i++) 1281 pte[i] = PTE_G; 1282 1283 kernel_vm_end = (kernel_vm_end + NBPDR) & ~PDRMASK; 1284 if (kernel_vm_end - 1 >= kernel_map->max_offset) { 1285 kernel_vm_end = kernel_map->max_offset; 1286 break; 1287 } 1288 } 1289 } 1290 1291 /*************************************************** 1292 * page management routines. 1293 ***************************************************/ 1294 1295 CTASSERT(sizeof(struct pv_chunk) == PAGE_SIZE); 1296 #ifdef __mips_n64 1297 CTASSERT(_NPCM == 3); 1298 CTASSERT(_NPCPV == 168); 1299 #else 1300 CTASSERT(_NPCM == 11); 1301 CTASSERT(_NPCPV == 336); 1302 #endif 1303 1304 static __inline struct pv_chunk * 1305 pv_to_chunk(pv_entry_t pv) 1306 { 1307 1308 return ((struct pv_chunk *)((uintptr_t)pv & ~(uintptr_t)PAGE_MASK)); 1309 } 1310 1311 #define PV_PMAP(pv) (pv_to_chunk(pv)->pc_pmap) 1312 1313 #ifdef __mips_n64 1314 #define PC_FREE0_1 0xfffffffffffffffful 1315 #define PC_FREE2 0x000000fffffffffful 1316 #else 1317 #define PC_FREE0_9 0xfffffffful /* Free values for index 0 through 9 */ 1318 #define PC_FREE10 0x0000fffful /* Free values for index 10 */ 1319 #endif 1320 1321 static const u_long pc_freemask[_NPCM] = { 1322 #ifdef __mips_n64 1323 PC_FREE0_1, PC_FREE0_1, PC_FREE2 1324 #else 1325 PC_FREE0_9, PC_FREE0_9, PC_FREE0_9, 1326 PC_FREE0_9, PC_FREE0_9, PC_FREE0_9, 1327 PC_FREE0_9, PC_FREE0_9, PC_FREE0_9, 1328 PC_FREE0_9, PC_FREE10 1329 #endif 1330 }; 1331 1332 static SYSCTL_NODE(_vm, OID_AUTO, pmap, CTLFLAG_RD, 0, "VM/pmap parameters"); 1333 1334 SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_count, CTLFLAG_RD, &pv_entry_count, 0, 1335 "Current number of pv entries"); 1336 1337 #ifdef PV_STATS 1338 static int pc_chunk_count, pc_chunk_allocs, pc_chunk_frees, pc_chunk_tryfail; 1339 1340 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_count, CTLFLAG_RD, &pc_chunk_count, 0, 1341 "Current number of pv entry chunks"); 1342 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_allocs, CTLFLAG_RD, &pc_chunk_allocs, 0, 1343 "Current number of pv entry chunks allocated"); 1344 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_frees, CTLFLAG_RD, &pc_chunk_frees, 0, 1345 "Current number of pv entry chunks frees"); 1346 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_tryfail, CTLFLAG_RD, &pc_chunk_tryfail, 0, 1347 "Number of times tried to get a chunk page but failed."); 1348 1349 static long pv_entry_frees, pv_entry_allocs; 1350 static int pv_entry_spare; 1351 1352 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_frees, CTLFLAG_RD, &pv_entry_frees, 0, 1353 "Current number of pv entry frees"); 1354 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_allocs, CTLFLAG_RD, &pv_entry_allocs, 0, 1355 "Current number of pv entry allocs"); 1356 SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_spare, CTLFLAG_RD, &pv_entry_spare, 0, 1357 "Current number of spare pv entries"); 1358 #endif 1359 1360 /* 1361 * We are in a serious low memory condition. Resort to 1362 * drastic measures to free some pages so we can allocate 1363 * another pv entry chunk. 1364 */ 1365 static vm_page_t 1366 pmap_pv_reclaim(pmap_t locked_pmap) 1367 { 1368 struct pch newtail; 1369 struct pv_chunk *pc; 1370 pd_entry_t *pde; 1371 pmap_t pmap; 1372 pt_entry_t *pte, oldpte; 1373 pv_entry_t pv; 1374 vm_offset_t va; 1375 vm_page_t m, m_pc; 1376 u_long inuse; 1377 int bit, field, freed, idx; 1378 1379 PMAP_LOCK_ASSERT(locked_pmap, MA_OWNED); 1380 pmap = NULL; 1381 m_pc = NULL; 1382 TAILQ_INIT(&newtail); 1383 while ((pc = TAILQ_FIRST(&pv_chunks)) != NULL) { 1384 TAILQ_REMOVE(&pv_chunks, pc, pc_lru); 1385 if (pmap != pc->pc_pmap) { 1386 if (pmap != NULL) { 1387 pmap_invalidate_all(pmap); 1388 if (pmap != locked_pmap) 1389 PMAP_UNLOCK(pmap); 1390 } 1391 pmap = pc->pc_pmap; 1392 /* Avoid deadlock and lock recursion. */ 1393 if (pmap > locked_pmap) 1394 PMAP_LOCK(pmap); 1395 else if (pmap != locked_pmap && !PMAP_TRYLOCK(pmap)) { 1396 pmap = NULL; 1397 TAILQ_INSERT_TAIL(&newtail, pc, pc_lru); 1398 continue; 1399 } 1400 } 1401 1402 /* 1403 * Destroy every non-wired, 4 KB page mapping in the chunk. 1404 */ 1405 freed = 0; 1406 for (field = 0; field < _NPCM; field++) { 1407 for (inuse = ~pc->pc_map[field] & pc_freemask[field]; 1408 inuse != 0; inuse &= ~(1UL << bit)) { 1409 bit = ffsl(inuse) - 1; 1410 idx = field * sizeof(inuse) * NBBY + bit; 1411 pv = &pc->pc_pventry[idx]; 1412 va = pv->pv_va; 1413 pde = pmap_pde(pmap, va); 1414 KASSERT(pde != NULL && *pde != 0, 1415 ("pmap_pv_reclaim: pde")); 1416 pte = pmap_pde_to_pte(pde, va); 1417 oldpte = *pte; 1418 if (pte_test(&oldpte, PTE_W)) 1419 continue; 1420 if (is_kernel_pmap(pmap)) 1421 *pte = PTE_G; 1422 else 1423 *pte = 0; 1424 m = PHYS_TO_VM_PAGE(TLBLO_PTE_TO_PA(oldpte)); 1425 if (pte_test(&oldpte, PTE_D)) 1426 vm_page_dirty(m); 1427 if (m->md.pv_flags & PV_TABLE_REF) 1428 vm_page_aflag_set(m, PGA_REFERENCED); 1429 m->md.pv_flags &= ~PV_TABLE_REF; 1430 TAILQ_REMOVE(&m->md.pv_list, pv, pv_list); 1431 if (TAILQ_EMPTY(&m->md.pv_list)) 1432 vm_page_aflag_clear(m, PGA_WRITEABLE); 1433 pc->pc_map[field] |= 1UL << bit; 1434 pmap_unuse_pt(pmap, va, *pde); 1435 freed++; 1436 } 1437 } 1438 if (freed == 0) { 1439 TAILQ_INSERT_TAIL(&newtail, pc, pc_lru); 1440 continue; 1441 } 1442 /* Every freed mapping is for a 4 KB page. */ 1443 pmap->pm_stats.resident_count -= freed; 1444 PV_STAT(pv_entry_frees += freed); 1445 PV_STAT(pv_entry_spare += freed); 1446 pv_entry_count -= freed; 1447 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list); 1448 for (field = 0; field < _NPCM; field++) 1449 if (pc->pc_map[field] != pc_freemask[field]) { 1450 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, 1451 pc_list); 1452 TAILQ_INSERT_TAIL(&newtail, pc, pc_lru); 1453 1454 /* 1455 * One freed pv entry in locked_pmap is 1456 * sufficient. 1457 */ 1458 if (pmap == locked_pmap) 1459 goto out; 1460 break; 1461 } 1462 if (field == _NPCM) { 1463 PV_STAT(pv_entry_spare -= _NPCPV); 1464 PV_STAT(pc_chunk_count--); 1465 PV_STAT(pc_chunk_frees++); 1466 /* Entire chunk is free; return it. */ 1467 m_pc = PHYS_TO_VM_PAGE(MIPS_DIRECT_TO_PHYS( 1468 (vm_offset_t)pc)); 1469 break; 1470 } 1471 } 1472 out: 1473 TAILQ_CONCAT(&pv_chunks, &newtail, pc_lru); 1474 if (pmap != NULL) { 1475 pmap_invalidate_all(pmap); 1476 if (pmap != locked_pmap) 1477 PMAP_UNLOCK(pmap); 1478 } 1479 return (m_pc); 1480 } 1481 1482 /* 1483 * free the pv_entry back to the free list 1484 */ 1485 static void 1486 free_pv_entry(pmap_t pmap, pv_entry_t pv) 1487 { 1488 struct pv_chunk *pc; 1489 int bit, field, idx; 1490 1491 rw_assert(&pvh_global_lock, RA_WLOCKED); 1492 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 1493 PV_STAT(pv_entry_frees++); 1494 PV_STAT(pv_entry_spare++); 1495 pv_entry_count--; 1496 pc = pv_to_chunk(pv); 1497 idx = pv - &pc->pc_pventry[0]; 1498 field = idx / (sizeof(u_long) * NBBY); 1499 bit = idx % (sizeof(u_long) * NBBY); 1500 pc->pc_map[field] |= 1ul << bit; 1501 for (idx = 0; idx < _NPCM; idx++) 1502 if (pc->pc_map[idx] != pc_freemask[idx]) { 1503 /* 1504 * 98% of the time, pc is already at the head of the 1505 * list. If it isn't already, move it to the head. 1506 */ 1507 if (__predict_false(TAILQ_FIRST(&pmap->pm_pvchunk) != 1508 pc)) { 1509 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list); 1510 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, 1511 pc_list); 1512 } 1513 return; 1514 } 1515 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list); 1516 free_pv_chunk(pc); 1517 } 1518 1519 static void 1520 free_pv_chunk(struct pv_chunk *pc) 1521 { 1522 vm_page_t m; 1523 1524 TAILQ_REMOVE(&pv_chunks, pc, pc_lru); 1525 PV_STAT(pv_entry_spare -= _NPCPV); 1526 PV_STAT(pc_chunk_count--); 1527 PV_STAT(pc_chunk_frees++); 1528 /* entire chunk is free, return it */ 1529 m = PHYS_TO_VM_PAGE(MIPS_DIRECT_TO_PHYS((vm_offset_t)pc)); 1530 vm_page_unwire(m, 0); 1531 vm_page_free(m); 1532 } 1533 1534 /* 1535 * get a new pv_entry, allocating a block from the system 1536 * when needed. 1537 */ 1538 static pv_entry_t 1539 get_pv_entry(pmap_t pmap, boolean_t try) 1540 { 1541 struct pv_chunk *pc; 1542 pv_entry_t pv; 1543 vm_page_t m; 1544 int bit, field, idx; 1545 1546 rw_assert(&pvh_global_lock, RA_WLOCKED); 1547 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 1548 PV_STAT(pv_entry_allocs++); 1549 pv_entry_count++; 1550 retry: 1551 pc = TAILQ_FIRST(&pmap->pm_pvchunk); 1552 if (pc != NULL) { 1553 for (field = 0; field < _NPCM; field++) { 1554 if (pc->pc_map[field]) { 1555 bit = ffsl(pc->pc_map[field]) - 1; 1556 break; 1557 } 1558 } 1559 if (field < _NPCM) { 1560 idx = field * sizeof(pc->pc_map[field]) * NBBY + bit; 1561 pv = &pc->pc_pventry[idx]; 1562 pc->pc_map[field] &= ~(1ul << bit); 1563 /* If this was the last item, move it to tail */ 1564 for (field = 0; field < _NPCM; field++) 1565 if (pc->pc_map[field] != 0) { 1566 PV_STAT(pv_entry_spare--); 1567 return (pv); /* not full, return */ 1568 } 1569 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list); 1570 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc, pc_list); 1571 PV_STAT(pv_entry_spare--); 1572 return (pv); 1573 } 1574 } 1575 /* No free items, allocate another chunk */ 1576 m = vm_page_alloc_freelist(VM_FREELIST_DIRECT, VM_ALLOC_NORMAL | 1577 VM_ALLOC_WIRED); 1578 if (m == NULL) { 1579 if (try) { 1580 pv_entry_count--; 1581 PV_STAT(pc_chunk_tryfail++); 1582 return (NULL); 1583 } 1584 m = pmap_pv_reclaim(pmap); 1585 if (m == NULL) 1586 goto retry; 1587 } 1588 PV_STAT(pc_chunk_count++); 1589 PV_STAT(pc_chunk_allocs++); 1590 pc = (struct pv_chunk *)MIPS_PHYS_TO_DIRECT(VM_PAGE_TO_PHYS(m)); 1591 pc->pc_pmap = pmap; 1592 pc->pc_map[0] = pc_freemask[0] & ~1ul; /* preallocated bit 0 */ 1593 for (field = 1; field < _NPCM; field++) 1594 pc->pc_map[field] = pc_freemask[field]; 1595 TAILQ_INSERT_TAIL(&pv_chunks, pc, pc_lru); 1596 pv = &pc->pc_pventry[0]; 1597 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list); 1598 PV_STAT(pv_entry_spare += _NPCPV - 1); 1599 return (pv); 1600 } 1601 1602 static pv_entry_t 1603 pmap_pvh_remove(struct md_page *pvh, pmap_t pmap, vm_offset_t va) 1604 { 1605 pv_entry_t pv; 1606 1607 rw_assert(&pvh_global_lock, RA_WLOCKED); 1608 TAILQ_FOREACH(pv, &pvh->pv_list, pv_list) { 1609 if (pmap == PV_PMAP(pv) && va == pv->pv_va) { 1610 TAILQ_REMOVE(&pvh->pv_list, pv, pv_list); 1611 break; 1612 } 1613 } 1614 return (pv); 1615 } 1616 1617 static void 1618 pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va) 1619 { 1620 pv_entry_t pv; 1621 1622 pv = pmap_pvh_remove(pvh, pmap, va); 1623 KASSERT(pv != NULL, ("pmap_pvh_free: pv not found, pa %lx va %lx", 1624 (u_long)VM_PAGE_TO_PHYS(__containerof(pvh, struct vm_page, md)), 1625 (u_long)va)); 1626 free_pv_entry(pmap, pv); 1627 } 1628 1629 static void 1630 pmap_remove_entry(pmap_t pmap, vm_page_t m, vm_offset_t va) 1631 { 1632 1633 rw_assert(&pvh_global_lock, RA_WLOCKED); 1634 pmap_pvh_free(&m->md, pmap, va); 1635 if (TAILQ_EMPTY(&m->md.pv_list)) 1636 vm_page_aflag_clear(m, PGA_WRITEABLE); 1637 } 1638 1639 /* 1640 * Conditionally create a pv entry. 1641 */ 1642 static boolean_t 1643 pmap_try_insert_pv_entry(pmap_t pmap, vm_page_t mpte, vm_offset_t va, 1644 vm_page_t m) 1645 { 1646 pv_entry_t pv; 1647 1648 rw_assert(&pvh_global_lock, RA_WLOCKED); 1649 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 1650 if ((pv = get_pv_entry(pmap, TRUE)) != NULL) { 1651 pv->pv_va = va; 1652 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_list); 1653 return (TRUE); 1654 } else 1655 return (FALSE); 1656 } 1657 1658 /* 1659 * pmap_remove_pte: do the things to unmap a page in a process 1660 */ 1661 static int 1662 pmap_remove_pte(struct pmap *pmap, pt_entry_t *ptq, vm_offset_t va, 1663 pd_entry_t pde) 1664 { 1665 pt_entry_t oldpte; 1666 vm_page_t m; 1667 vm_paddr_t pa; 1668 1669 rw_assert(&pvh_global_lock, RA_WLOCKED); 1670 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 1671 1672 /* 1673 * Write back all cache lines from the page being unmapped. 1674 */ 1675 mips_dcache_wbinv_range_index(va, PAGE_SIZE); 1676 1677 oldpte = *ptq; 1678 if (is_kernel_pmap(pmap)) 1679 *ptq = PTE_G; 1680 else 1681 *ptq = 0; 1682 1683 if (pte_test(&oldpte, PTE_W)) 1684 pmap->pm_stats.wired_count -= 1; 1685 1686 pmap->pm_stats.resident_count -= 1; 1687 1688 if (pte_test(&oldpte, PTE_MANAGED)) { 1689 pa = TLBLO_PTE_TO_PA(oldpte); 1690 m = PHYS_TO_VM_PAGE(pa); 1691 if (pte_test(&oldpte, PTE_D)) { 1692 KASSERT(!pte_test(&oldpte, PTE_RO), 1693 ("%s: modified page not writable: va: %p, pte: %#jx", 1694 __func__, (void *)va, (uintmax_t)oldpte)); 1695 vm_page_dirty(m); 1696 } 1697 if (m->md.pv_flags & PV_TABLE_REF) 1698 vm_page_aflag_set(m, PGA_REFERENCED); 1699 m->md.pv_flags &= ~PV_TABLE_REF; 1700 1701 pmap_remove_entry(pmap, m, va); 1702 } 1703 return (pmap_unuse_pt(pmap, va, pde)); 1704 } 1705 1706 /* 1707 * Remove a single page from a process address space 1708 */ 1709 static void 1710 pmap_remove_page(struct pmap *pmap, vm_offset_t va) 1711 { 1712 pd_entry_t *pde; 1713 pt_entry_t *ptq; 1714 1715 rw_assert(&pvh_global_lock, RA_WLOCKED); 1716 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 1717 pde = pmap_pde(pmap, va); 1718 if (pde == NULL || *pde == 0) 1719 return; 1720 ptq = pmap_pde_to_pte(pde, va); 1721 1722 /* 1723 * If there is no pte for this address, just skip it! 1724 */ 1725 if (!pte_test(ptq, PTE_V)) 1726 return; 1727 1728 (void)pmap_remove_pte(pmap, ptq, va, *pde); 1729 pmap_invalidate_page(pmap, va); 1730 } 1731 1732 /* 1733 * Remove the given range of addresses from the specified map. 1734 * 1735 * It is assumed that the start and end are properly 1736 * rounded to the page size. 1737 */ 1738 void 1739 pmap_remove(pmap_t pmap, vm_offset_t sva, vm_offset_t eva) 1740 { 1741 pd_entry_t *pde, *pdpe; 1742 pt_entry_t *pte; 1743 vm_offset_t va, va_next; 1744 1745 /* 1746 * Perform an unsynchronized read. This is, however, safe. 1747 */ 1748 if (pmap->pm_stats.resident_count == 0) 1749 return; 1750 1751 rw_wlock(&pvh_global_lock); 1752 PMAP_LOCK(pmap); 1753 1754 /* 1755 * special handling of removing one page. a very common operation 1756 * and easy to short circuit some code. 1757 */ 1758 if ((sva + PAGE_SIZE) == eva) { 1759 pmap_remove_page(pmap, sva); 1760 goto out; 1761 } 1762 for (; sva < eva; sva = va_next) { 1763 pdpe = pmap_segmap(pmap, sva); 1764 #ifdef __mips_n64 1765 if (*pdpe == 0) { 1766 va_next = (sva + NBSEG) & ~SEGMASK; 1767 if (va_next < sva) 1768 va_next = eva; 1769 continue; 1770 } 1771 #endif 1772 va_next = (sva + NBPDR) & ~PDRMASK; 1773 if (va_next < sva) 1774 va_next = eva; 1775 1776 pde = pmap_pdpe_to_pde(pdpe, sva); 1777 if (*pde == NULL) 1778 continue; 1779 1780 /* 1781 * Limit our scan to either the end of the va represented 1782 * by the current page table page, or to the end of the 1783 * range being removed. 1784 */ 1785 if (va_next > eva) 1786 va_next = eva; 1787 1788 va = va_next; 1789 for (pte = pmap_pde_to_pte(pde, sva); sva != va_next; pte++, 1790 sva += PAGE_SIZE) { 1791 if (!pte_test(pte, PTE_V)) { 1792 if (va != va_next) { 1793 pmap_invalidate_range(pmap, va, sva); 1794 va = va_next; 1795 } 1796 continue; 1797 } 1798 if (va == va_next) 1799 va = sva; 1800 if (pmap_remove_pte(pmap, pte, sva, *pde)) { 1801 sva += PAGE_SIZE; 1802 break; 1803 } 1804 } 1805 if (va != va_next) 1806 pmap_invalidate_range(pmap, va, sva); 1807 } 1808 out: 1809 rw_wunlock(&pvh_global_lock); 1810 PMAP_UNLOCK(pmap); 1811 } 1812 1813 /* 1814 * Routine: pmap_remove_all 1815 * Function: 1816 * Removes this physical page from 1817 * all physical maps in which it resides. 1818 * Reflects back modify bits to the pager. 1819 * 1820 * Notes: 1821 * Original versions of this routine were very 1822 * inefficient because they iteratively called 1823 * pmap_remove (slow...) 1824 */ 1825 1826 void 1827 pmap_remove_all(vm_page_t m) 1828 { 1829 pv_entry_t pv; 1830 pmap_t pmap; 1831 pd_entry_t *pde; 1832 pt_entry_t *pte, tpte; 1833 1834 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1835 ("pmap_remove_all: page %p is not managed", m)); 1836 rw_wlock(&pvh_global_lock); 1837 1838 if (m->md.pv_flags & PV_TABLE_REF) 1839 vm_page_aflag_set(m, PGA_REFERENCED); 1840 1841 while ((pv = TAILQ_FIRST(&m->md.pv_list)) != NULL) { 1842 pmap = PV_PMAP(pv); 1843 PMAP_LOCK(pmap); 1844 1845 /* 1846 * If it's last mapping writeback all caches from 1847 * the page being destroyed 1848 */ 1849 if (TAILQ_NEXT(pv, pv_list) == NULL) 1850 mips_dcache_wbinv_range_index(pv->pv_va, PAGE_SIZE); 1851 1852 pmap->pm_stats.resident_count--; 1853 1854 pde = pmap_pde(pmap, pv->pv_va); 1855 KASSERT(pde != NULL && *pde != 0, ("pmap_remove_all: pde")); 1856 pte = pmap_pde_to_pte(pde, pv->pv_va); 1857 1858 tpte = *pte; 1859 if (is_kernel_pmap(pmap)) 1860 *pte = PTE_G; 1861 else 1862 *pte = 0; 1863 1864 if (pte_test(&tpte, PTE_W)) 1865 pmap->pm_stats.wired_count--; 1866 1867 /* 1868 * Update the vm_page_t clean and reference bits. 1869 */ 1870 if (pte_test(&tpte, PTE_D)) { 1871 KASSERT(!pte_test(&tpte, PTE_RO), 1872 ("%s: modified page not writable: va: %p, pte: %#jx", 1873 __func__, (void *)pv->pv_va, (uintmax_t)tpte)); 1874 vm_page_dirty(m); 1875 } 1876 pmap_invalidate_page(pmap, pv->pv_va); 1877 1878 TAILQ_REMOVE(&m->md.pv_list, pv, pv_list); 1879 pmap_unuse_pt(pmap, pv->pv_va, *pde); 1880 free_pv_entry(pmap, pv); 1881 PMAP_UNLOCK(pmap); 1882 } 1883 1884 vm_page_aflag_clear(m, PGA_WRITEABLE); 1885 m->md.pv_flags &= ~PV_TABLE_REF; 1886 rw_wunlock(&pvh_global_lock); 1887 } 1888 1889 /* 1890 * Set the physical protection on the 1891 * specified range of this map as requested. 1892 */ 1893 void 1894 pmap_protect(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, vm_prot_t prot) 1895 { 1896 pt_entry_t pbits, *pte; 1897 pd_entry_t *pde, *pdpe; 1898 vm_offset_t va, va_next; 1899 vm_paddr_t pa; 1900 vm_page_t m; 1901 1902 if ((prot & VM_PROT_READ) == VM_PROT_NONE) { 1903 pmap_remove(pmap, sva, eva); 1904 return; 1905 } 1906 if (prot & VM_PROT_WRITE) 1907 return; 1908 1909 PMAP_LOCK(pmap); 1910 for (; sva < eva; sva = va_next) { 1911 pdpe = pmap_segmap(pmap, sva); 1912 #ifdef __mips_n64 1913 if (*pdpe == 0) { 1914 va_next = (sva + NBSEG) & ~SEGMASK; 1915 if (va_next < sva) 1916 va_next = eva; 1917 continue; 1918 } 1919 #endif 1920 va_next = (sva + NBPDR) & ~PDRMASK; 1921 if (va_next < sva) 1922 va_next = eva; 1923 1924 pde = pmap_pdpe_to_pde(pdpe, sva); 1925 if (*pde == NULL) 1926 continue; 1927 1928 /* 1929 * Limit our scan to either the end of the va represented 1930 * by the current page table page, or to the end of the 1931 * range being write protected. 1932 */ 1933 if (va_next > eva) 1934 va_next = eva; 1935 1936 va = va_next; 1937 for (pte = pmap_pde_to_pte(pde, sva); sva != va_next; pte++, 1938 sva += PAGE_SIZE) { 1939 pbits = *pte; 1940 if (!pte_test(&pbits, PTE_V) || pte_test(&pbits, 1941 PTE_RO)) { 1942 if (va != va_next) { 1943 pmap_invalidate_range(pmap, va, sva); 1944 va = va_next; 1945 } 1946 continue; 1947 } 1948 pte_set(&pbits, PTE_RO); 1949 if (pte_test(&pbits, PTE_D)) { 1950 pte_clear(&pbits, PTE_D); 1951 if (pte_test(&pbits, PTE_MANAGED)) { 1952 pa = TLBLO_PTE_TO_PA(pbits); 1953 m = PHYS_TO_VM_PAGE(pa); 1954 vm_page_dirty(m); 1955 } 1956 if (va == va_next) 1957 va = sva; 1958 } else { 1959 /* 1960 * Unless PTE_D is set, any TLB entries 1961 * mapping "sva" don't allow write access, so 1962 * they needn't be invalidated. 1963 */ 1964 if (va != va_next) { 1965 pmap_invalidate_range(pmap, va, sva); 1966 va = va_next; 1967 } 1968 } 1969 *pte = pbits; 1970 } 1971 if (va != va_next) 1972 pmap_invalidate_range(pmap, va, sva); 1973 } 1974 PMAP_UNLOCK(pmap); 1975 } 1976 1977 /* 1978 * Insert the given physical page (p) at 1979 * the specified virtual address (v) in the 1980 * target physical map with the protection requested. 1981 * 1982 * If specified, the page will be wired down, meaning 1983 * that the related pte can not be reclaimed. 1984 * 1985 * NB: This is the only routine which MAY NOT lazy-evaluate 1986 * or lose information. That is, this routine must actually 1987 * insert this page into the given map NOW. 1988 */ 1989 int 1990 pmap_enter(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot, 1991 u_int flags, int8_t psind __unused) 1992 { 1993 vm_paddr_t pa, opa; 1994 pt_entry_t *pte; 1995 pt_entry_t origpte, newpte; 1996 pv_entry_t pv; 1997 vm_page_t mpte, om; 1998 1999 va &= ~PAGE_MASK; 2000 KASSERT(va <= VM_MAX_KERNEL_ADDRESS, ("pmap_enter: toobig")); 2001 KASSERT((m->oflags & VPO_UNMANAGED) != 0 || va < kmi.clean_sva || 2002 va >= kmi.clean_eva, 2003 ("pmap_enter: managed mapping within the clean submap")); 2004 if ((m->oflags & VPO_UNMANAGED) == 0 && !vm_page_xbusied(m)) 2005 VM_OBJECT_ASSERT_LOCKED(m->object); 2006 pa = VM_PAGE_TO_PHYS(m); 2007 newpte = TLBLO_PA_TO_PFN(pa) | init_pte_prot(m, flags, prot); 2008 if ((flags & PMAP_ENTER_WIRED) != 0) 2009 newpte |= PTE_W; 2010 if (is_kernel_pmap(pmap)) 2011 newpte |= PTE_G; 2012 if (is_cacheable_mem(pa)) 2013 newpte |= PTE_C_CACHE; 2014 else 2015 newpte |= PTE_C_UNCACHED; 2016 2017 mpte = NULL; 2018 2019 rw_wlock(&pvh_global_lock); 2020 PMAP_LOCK(pmap); 2021 2022 /* 2023 * In the case that a page table page is not resident, we are 2024 * creating it here. 2025 */ 2026 if (va < VM_MAXUSER_ADDRESS) { 2027 mpte = pmap_allocpte(pmap, va, flags); 2028 if (mpte == NULL) { 2029 KASSERT((flags & PMAP_ENTER_NOSLEEP) != 0, 2030 ("pmap_allocpte failed with sleep allowed")); 2031 rw_wunlock(&pvh_global_lock); 2032 PMAP_UNLOCK(pmap); 2033 return (KERN_RESOURCE_SHORTAGE); 2034 } 2035 } 2036 pte = pmap_pte(pmap, va); 2037 2038 /* 2039 * Page Directory table entry not valid, we need a new PT page 2040 */ 2041 if (pte == NULL) { 2042 panic("pmap_enter: invalid page directory, pdir=%p, va=%p", 2043 (void *)pmap->pm_segtab, (void *)va); 2044 } 2045 om = NULL; 2046 origpte = *pte; 2047 opa = TLBLO_PTE_TO_PA(origpte); 2048 2049 /* 2050 * Mapping has not changed, must be protection or wiring change. 2051 */ 2052 if (pte_test(&origpte, PTE_V) && opa == pa) { 2053 /* 2054 * Wiring change, just update stats. We don't worry about 2055 * wiring PT pages as they remain resident as long as there 2056 * are valid mappings in them. Hence, if a user page is 2057 * wired, the PT page will be also. 2058 */ 2059 if (pte_test(&newpte, PTE_W) && !pte_test(&origpte, PTE_W)) 2060 pmap->pm_stats.wired_count++; 2061 else if (!pte_test(&newpte, PTE_W) && pte_test(&origpte, 2062 PTE_W)) 2063 pmap->pm_stats.wired_count--; 2064 2065 KASSERT(!pte_test(&origpte, PTE_D | PTE_RO), 2066 ("%s: modified page not writable: va: %p, pte: %#jx", 2067 __func__, (void *)va, (uintmax_t)origpte)); 2068 2069 /* 2070 * Remove extra pte reference 2071 */ 2072 if (mpte) 2073 mpte->wire_count--; 2074 2075 if (pte_test(&origpte, PTE_MANAGED)) { 2076 m->md.pv_flags |= PV_TABLE_REF; 2077 om = m; 2078 newpte |= PTE_MANAGED; 2079 if (!pte_test(&newpte, PTE_RO)) 2080 vm_page_aflag_set(m, PGA_WRITEABLE); 2081 } 2082 goto validate; 2083 } 2084 2085 pv = NULL; 2086 2087 /* 2088 * Mapping has changed, invalidate old range and fall through to 2089 * handle validating new mapping. 2090 */ 2091 if (opa) { 2092 if (pte_test(&origpte, PTE_W)) 2093 pmap->pm_stats.wired_count--; 2094 2095 if (pte_test(&origpte, PTE_MANAGED)) { 2096 om = PHYS_TO_VM_PAGE(opa); 2097 pv = pmap_pvh_remove(&om->md, pmap, va); 2098 } 2099 if (mpte != NULL) { 2100 mpte->wire_count--; 2101 KASSERT(mpte->wire_count > 0, 2102 ("pmap_enter: missing reference to page table page," 2103 " va: %p", (void *)va)); 2104 } 2105 } else 2106 pmap->pm_stats.resident_count++; 2107 2108 /* 2109 * Enter on the PV list if part of our managed memory. 2110 */ 2111 if ((m->oflags & VPO_UNMANAGED) == 0) { 2112 m->md.pv_flags |= PV_TABLE_REF; 2113 if (pv == NULL) 2114 pv = get_pv_entry(pmap, FALSE); 2115 pv->pv_va = va; 2116 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_list); 2117 newpte |= PTE_MANAGED; 2118 if (!pte_test(&newpte, PTE_RO)) 2119 vm_page_aflag_set(m, PGA_WRITEABLE); 2120 } else if (pv != NULL) 2121 free_pv_entry(pmap, pv); 2122 2123 /* 2124 * Increment counters 2125 */ 2126 if (pte_test(&newpte, PTE_W)) 2127 pmap->pm_stats.wired_count++; 2128 2129 validate: 2130 2131 #ifdef PMAP_DEBUG 2132 printf("pmap_enter: va: %p -> pa: %p\n", (void *)va, (void *)pa); 2133 #endif 2134 2135 /* 2136 * if the mapping or permission bits are different, we need to 2137 * update the pte. 2138 */ 2139 if (origpte != newpte) { 2140 *pte = newpte; 2141 if (pte_test(&origpte, PTE_V)) { 2142 if (pte_test(&origpte, PTE_MANAGED) && opa != pa) { 2143 if (om->md.pv_flags & PV_TABLE_REF) 2144 vm_page_aflag_set(om, PGA_REFERENCED); 2145 om->md.pv_flags &= ~PV_TABLE_REF; 2146 } 2147 if (pte_test(&origpte, PTE_D)) { 2148 KASSERT(!pte_test(&origpte, PTE_RO), 2149 ("pmap_enter: modified page not writable:" 2150 " va: %p, pte: %#jx", (void *)va, (uintmax_t)origpte)); 2151 if (pte_test(&origpte, PTE_MANAGED)) 2152 vm_page_dirty(om); 2153 } 2154 if (pte_test(&origpte, PTE_MANAGED) && 2155 TAILQ_EMPTY(&om->md.pv_list)) 2156 vm_page_aflag_clear(om, PGA_WRITEABLE); 2157 pmap_update_page(pmap, va, newpte); 2158 } 2159 } 2160 2161 /* 2162 * Sync I & D caches for executable pages. Do this only if the 2163 * target pmap belongs to the current process. Otherwise, an 2164 * unresolvable TLB miss may occur. 2165 */ 2166 if (!is_kernel_pmap(pmap) && (pmap == &curproc->p_vmspace->vm_pmap) && 2167 (prot & VM_PROT_EXECUTE)) { 2168 mips_icache_sync_range(va, PAGE_SIZE); 2169 mips_dcache_wbinv_range(va, PAGE_SIZE); 2170 } 2171 rw_wunlock(&pvh_global_lock); 2172 PMAP_UNLOCK(pmap); 2173 return (KERN_SUCCESS); 2174 } 2175 2176 /* 2177 * this code makes some *MAJOR* assumptions: 2178 * 1. Current pmap & pmap exists. 2179 * 2. Not wired. 2180 * 3. Read access. 2181 * 4. No page table pages. 2182 * but is *MUCH* faster than pmap_enter... 2183 */ 2184 2185 void 2186 pmap_enter_quick(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot) 2187 { 2188 2189 rw_wlock(&pvh_global_lock); 2190 PMAP_LOCK(pmap); 2191 (void)pmap_enter_quick_locked(pmap, va, m, prot, NULL); 2192 rw_wunlock(&pvh_global_lock); 2193 PMAP_UNLOCK(pmap); 2194 } 2195 2196 static vm_page_t 2197 pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va, vm_page_t m, 2198 vm_prot_t prot, vm_page_t mpte) 2199 { 2200 pt_entry_t *pte; 2201 vm_paddr_t pa; 2202 2203 KASSERT(va < kmi.clean_sva || va >= kmi.clean_eva || 2204 (m->oflags & VPO_UNMANAGED) != 0, 2205 ("pmap_enter_quick_locked: managed mapping within the clean submap")); 2206 rw_assert(&pvh_global_lock, RA_WLOCKED); 2207 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 2208 2209 /* 2210 * In the case that a page table page is not resident, we are 2211 * creating it here. 2212 */ 2213 if (va < VM_MAXUSER_ADDRESS) { 2214 pd_entry_t *pde; 2215 unsigned ptepindex; 2216 2217 /* 2218 * Calculate pagetable page index 2219 */ 2220 ptepindex = pmap_pde_pindex(va); 2221 if (mpte && (mpte->pindex == ptepindex)) { 2222 mpte->wire_count++; 2223 } else { 2224 /* 2225 * Get the page directory entry 2226 */ 2227 pde = pmap_pde(pmap, va); 2228 2229 /* 2230 * If the page table page is mapped, we just 2231 * increment the hold count, and activate it. 2232 */ 2233 if (pde && *pde != 0) { 2234 mpte = PHYS_TO_VM_PAGE( 2235 MIPS_DIRECT_TO_PHYS(*pde)); 2236 mpte->wire_count++; 2237 } else { 2238 mpte = _pmap_allocpte(pmap, ptepindex, 2239 PMAP_ENTER_NOSLEEP); 2240 if (mpte == NULL) 2241 return (mpte); 2242 } 2243 } 2244 } else { 2245 mpte = NULL; 2246 } 2247 2248 pte = pmap_pte(pmap, va); 2249 if (pte_test(pte, PTE_V)) { 2250 if (mpte != NULL) { 2251 mpte->wire_count--; 2252 mpte = NULL; 2253 } 2254 return (mpte); 2255 } 2256 2257 /* 2258 * Enter on the PV list if part of our managed memory. 2259 */ 2260 if ((m->oflags & VPO_UNMANAGED) == 0 && 2261 !pmap_try_insert_pv_entry(pmap, mpte, va, m)) { 2262 if (mpte != NULL) { 2263 pmap_unwire_ptp(pmap, va, mpte); 2264 mpte = NULL; 2265 } 2266 return (mpte); 2267 } 2268 2269 /* 2270 * Increment counters 2271 */ 2272 pmap->pm_stats.resident_count++; 2273 2274 pa = VM_PAGE_TO_PHYS(m); 2275 2276 /* 2277 * Now validate mapping with RO protection 2278 */ 2279 *pte = PTE_RO | TLBLO_PA_TO_PFN(pa) | PTE_V; 2280 if ((m->oflags & VPO_UNMANAGED) == 0) 2281 *pte |= PTE_MANAGED; 2282 2283 if (is_cacheable_mem(pa)) 2284 *pte |= PTE_C_CACHE; 2285 else 2286 *pte |= PTE_C_UNCACHED; 2287 2288 if (is_kernel_pmap(pmap)) 2289 *pte |= PTE_G; 2290 else { 2291 /* 2292 * Sync I & D caches. Do this only if the target pmap 2293 * belongs to the current process. Otherwise, an 2294 * unresolvable TLB miss may occur. */ 2295 if (pmap == &curproc->p_vmspace->vm_pmap) { 2296 va &= ~PAGE_MASK; 2297 mips_icache_sync_range(va, PAGE_SIZE); 2298 mips_dcache_wbinv_range(va, PAGE_SIZE); 2299 } 2300 } 2301 return (mpte); 2302 } 2303 2304 /* 2305 * Make a temporary mapping for a physical address. This is only intended 2306 * to be used for panic dumps. 2307 * 2308 * Use XKPHYS for 64 bit, and KSEG0 where possible for 32 bit. 2309 */ 2310 void * 2311 pmap_kenter_temporary(vm_paddr_t pa, int i) 2312 { 2313 vm_offset_t va; 2314 2315 if (i != 0) 2316 printf("%s: ERROR!!! More than one page of virtual address mapping not supported\n", 2317 __func__); 2318 2319 if (MIPS_DIRECT_MAPPABLE(pa)) { 2320 va = MIPS_PHYS_TO_DIRECT(pa); 2321 } else { 2322 #ifndef __mips_n64 /* XXX : to be converted to new style */ 2323 int cpu; 2324 register_t intr; 2325 struct local_sysmaps *sysm; 2326 pt_entry_t *pte, npte; 2327 2328 /* If this is used other than for dumps, we may need to leave 2329 * interrupts disasbled on return. If crash dumps don't work when 2330 * we get to this point, we might want to consider this (leaving things 2331 * disabled as a starting point ;-) 2332 */ 2333 intr = intr_disable(); 2334 cpu = PCPU_GET(cpuid); 2335 sysm = &sysmap_lmem[cpu]; 2336 /* Since this is for the debugger, no locks or any other fun */ 2337 npte = TLBLO_PA_TO_PFN(pa) | PTE_C_CACHE | PTE_D | PTE_V | 2338 PTE_G; 2339 pte = pmap_pte(kernel_pmap, sysm->base); 2340 *pte = npte; 2341 sysm->valid1 = 1; 2342 pmap_update_page(kernel_pmap, sysm->base, npte); 2343 va = sysm->base; 2344 intr_restore(intr); 2345 #endif 2346 } 2347 return ((void *)va); 2348 } 2349 2350 void 2351 pmap_kenter_temporary_free(vm_paddr_t pa) 2352 { 2353 #ifndef __mips_n64 /* XXX : to be converted to new style */ 2354 int cpu; 2355 register_t intr; 2356 struct local_sysmaps *sysm; 2357 #endif 2358 2359 if (MIPS_DIRECT_MAPPABLE(pa)) { 2360 /* nothing to do for this case */ 2361 return; 2362 } 2363 #ifndef __mips_n64 /* XXX : to be converted to new style */ 2364 cpu = PCPU_GET(cpuid); 2365 sysm = &sysmap_lmem[cpu]; 2366 if (sysm->valid1) { 2367 pt_entry_t *pte; 2368 2369 intr = intr_disable(); 2370 pte = pmap_pte(kernel_pmap, sysm->base); 2371 *pte = PTE_G; 2372 pmap_invalidate_page(kernel_pmap, sysm->base); 2373 intr_restore(intr); 2374 sysm->valid1 = 0; 2375 } 2376 #endif 2377 } 2378 2379 /* 2380 * Maps a sequence of resident pages belonging to the same object. 2381 * The sequence begins with the given page m_start. This page is 2382 * mapped at the given virtual address start. Each subsequent page is 2383 * mapped at a virtual address that is offset from start by the same 2384 * amount as the page is offset from m_start within the object. The 2385 * last page in the sequence is the page with the largest offset from 2386 * m_start that can be mapped at a virtual address less than the given 2387 * virtual address end. Not every virtual page between start and end 2388 * is mapped; only those for which a resident page exists with the 2389 * corresponding offset from m_start are mapped. 2390 */ 2391 void 2392 pmap_enter_object(pmap_t pmap, vm_offset_t start, vm_offset_t end, 2393 vm_page_t m_start, vm_prot_t prot) 2394 { 2395 vm_page_t m, mpte; 2396 vm_pindex_t diff, psize; 2397 2398 VM_OBJECT_ASSERT_LOCKED(m_start->object); 2399 2400 psize = atop(end - start); 2401 mpte = NULL; 2402 m = m_start; 2403 rw_wlock(&pvh_global_lock); 2404 PMAP_LOCK(pmap); 2405 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) { 2406 mpte = pmap_enter_quick_locked(pmap, start + ptoa(diff), m, 2407 prot, mpte); 2408 m = TAILQ_NEXT(m, listq); 2409 } 2410 rw_wunlock(&pvh_global_lock); 2411 PMAP_UNLOCK(pmap); 2412 } 2413 2414 /* 2415 * pmap_object_init_pt preloads the ptes for a given object 2416 * into the specified pmap. This eliminates the blast of soft 2417 * faults on process startup and immediately after an mmap. 2418 */ 2419 void 2420 pmap_object_init_pt(pmap_t pmap, vm_offset_t addr, 2421 vm_object_t object, vm_pindex_t pindex, vm_size_t size) 2422 { 2423 VM_OBJECT_ASSERT_WLOCKED(object); 2424 KASSERT(object->type == OBJT_DEVICE || object->type == OBJT_SG, 2425 ("pmap_object_init_pt: non-device object")); 2426 } 2427 2428 /* 2429 * Clear the wired attribute from the mappings for the specified range of 2430 * addresses in the given pmap. Every valid mapping within that range 2431 * must have the wired attribute set. In contrast, invalid mappings 2432 * cannot have the wired attribute set, so they are ignored. 2433 * 2434 * The wired attribute of the page table entry is not a hardware feature, 2435 * so there is no need to invalidate any TLB entries. 2436 */ 2437 void 2438 pmap_unwire(pmap_t pmap, vm_offset_t sva, vm_offset_t eva) 2439 { 2440 pd_entry_t *pde, *pdpe; 2441 pt_entry_t *pte; 2442 vm_offset_t va_next; 2443 2444 PMAP_LOCK(pmap); 2445 for (; sva < eva; sva = va_next) { 2446 pdpe = pmap_segmap(pmap, sva); 2447 #ifdef __mips_n64 2448 if (*pdpe == NULL) { 2449 va_next = (sva + NBSEG) & ~SEGMASK; 2450 if (va_next < sva) 2451 va_next = eva; 2452 continue; 2453 } 2454 #endif 2455 va_next = (sva + NBPDR) & ~PDRMASK; 2456 if (va_next < sva) 2457 va_next = eva; 2458 pde = pmap_pdpe_to_pde(pdpe, sva); 2459 if (*pde == NULL) 2460 continue; 2461 if (va_next > eva) 2462 va_next = eva; 2463 for (pte = pmap_pde_to_pte(pde, sva); sva != va_next; pte++, 2464 sva += PAGE_SIZE) { 2465 if (!pte_test(pte, PTE_V)) 2466 continue; 2467 if (!pte_test(pte, PTE_W)) 2468 panic("pmap_unwire: pte %#jx is missing PG_W", 2469 (uintmax_t)*pte); 2470 pte_clear(pte, PTE_W); 2471 pmap->pm_stats.wired_count--; 2472 } 2473 } 2474 PMAP_UNLOCK(pmap); 2475 } 2476 2477 /* 2478 * Copy the range specified by src_addr/len 2479 * from the source map to the range dst_addr/len 2480 * in the destination map. 2481 * 2482 * This routine is only advisory and need not do anything. 2483 */ 2484 2485 void 2486 pmap_copy(pmap_t dst_pmap, pmap_t src_pmap, vm_offset_t dst_addr, 2487 vm_size_t len, vm_offset_t src_addr) 2488 { 2489 } 2490 2491 /* 2492 * pmap_zero_page zeros the specified hardware page by mapping 2493 * the page into KVM and using bzero to clear its contents. 2494 * 2495 * Use XKPHYS for 64 bit, and KSEG0 where possible for 32 bit. 2496 */ 2497 void 2498 pmap_zero_page(vm_page_t m) 2499 { 2500 vm_offset_t va; 2501 vm_paddr_t phys = VM_PAGE_TO_PHYS(m); 2502 2503 if (MIPS_DIRECT_MAPPABLE(phys)) { 2504 va = MIPS_PHYS_TO_DIRECT(phys); 2505 bzero((caddr_t)va, PAGE_SIZE); 2506 mips_dcache_wbinv_range(va, PAGE_SIZE); 2507 } else { 2508 va = pmap_lmem_map1(phys); 2509 bzero((caddr_t)va, PAGE_SIZE); 2510 mips_dcache_wbinv_range(va, PAGE_SIZE); 2511 pmap_lmem_unmap(); 2512 } 2513 } 2514 2515 /* 2516 * pmap_zero_page_area zeros the specified hardware page by mapping 2517 * the page into KVM and using bzero to clear its contents. 2518 * 2519 * off and size may not cover an area beyond a single hardware page. 2520 */ 2521 void 2522 pmap_zero_page_area(vm_page_t m, int off, int size) 2523 { 2524 vm_offset_t va; 2525 vm_paddr_t phys = VM_PAGE_TO_PHYS(m); 2526 2527 if (MIPS_DIRECT_MAPPABLE(phys)) { 2528 va = MIPS_PHYS_TO_DIRECT(phys); 2529 bzero((char *)(caddr_t)va + off, size); 2530 mips_dcache_wbinv_range(va + off, size); 2531 } else { 2532 va = pmap_lmem_map1(phys); 2533 bzero((char *)va + off, size); 2534 mips_dcache_wbinv_range(va + off, size); 2535 pmap_lmem_unmap(); 2536 } 2537 } 2538 2539 void 2540 pmap_zero_page_idle(vm_page_t m) 2541 { 2542 vm_offset_t va; 2543 vm_paddr_t phys = VM_PAGE_TO_PHYS(m); 2544 2545 if (MIPS_DIRECT_MAPPABLE(phys)) { 2546 va = MIPS_PHYS_TO_DIRECT(phys); 2547 bzero((caddr_t)va, PAGE_SIZE); 2548 mips_dcache_wbinv_range(va, PAGE_SIZE); 2549 } else { 2550 va = pmap_lmem_map1(phys); 2551 bzero((caddr_t)va, PAGE_SIZE); 2552 mips_dcache_wbinv_range(va, PAGE_SIZE); 2553 pmap_lmem_unmap(); 2554 } 2555 } 2556 2557 /* 2558 * pmap_copy_page copies the specified (machine independent) 2559 * page by mapping the page into virtual memory and using 2560 * bcopy to copy the page, one machine dependent page at a 2561 * time. 2562 * 2563 * Use XKPHYS for 64 bit, and KSEG0 where possible for 32 bit. 2564 */ 2565 void 2566 pmap_copy_page(vm_page_t src, vm_page_t dst) 2567 { 2568 vm_offset_t va_src, va_dst; 2569 vm_paddr_t phys_src = VM_PAGE_TO_PHYS(src); 2570 vm_paddr_t phys_dst = VM_PAGE_TO_PHYS(dst); 2571 2572 if (MIPS_DIRECT_MAPPABLE(phys_src) && MIPS_DIRECT_MAPPABLE(phys_dst)) { 2573 /* easy case, all can be accessed via KSEG0 */ 2574 /* 2575 * Flush all caches for VA that are mapped to this page 2576 * to make sure that data in SDRAM is up to date 2577 */ 2578 pmap_flush_pvcache(src); 2579 mips_dcache_wbinv_range_index( 2580 MIPS_PHYS_TO_DIRECT(phys_dst), PAGE_SIZE); 2581 va_src = MIPS_PHYS_TO_DIRECT(phys_src); 2582 va_dst = MIPS_PHYS_TO_DIRECT(phys_dst); 2583 bcopy((caddr_t)va_src, (caddr_t)va_dst, PAGE_SIZE); 2584 mips_dcache_wbinv_range(va_dst, PAGE_SIZE); 2585 } else { 2586 va_src = pmap_lmem_map2(phys_src, phys_dst); 2587 va_dst = va_src + PAGE_SIZE; 2588 bcopy((void *)va_src, (void *)va_dst, PAGE_SIZE); 2589 mips_dcache_wbinv_range(va_dst, PAGE_SIZE); 2590 pmap_lmem_unmap(); 2591 } 2592 } 2593 2594 int unmapped_buf_allowed; 2595 2596 void 2597 pmap_copy_pages(vm_page_t ma[], vm_offset_t a_offset, vm_page_t mb[], 2598 vm_offset_t b_offset, int xfersize) 2599 { 2600 char *a_cp, *b_cp; 2601 vm_page_t a_m, b_m; 2602 vm_offset_t a_pg_offset, b_pg_offset; 2603 vm_paddr_t a_phys, b_phys; 2604 int cnt; 2605 2606 while (xfersize > 0) { 2607 a_pg_offset = a_offset & PAGE_MASK; 2608 cnt = min(xfersize, PAGE_SIZE - a_pg_offset); 2609 a_m = ma[a_offset >> PAGE_SHIFT]; 2610 a_phys = VM_PAGE_TO_PHYS(a_m); 2611 b_pg_offset = b_offset & PAGE_MASK; 2612 cnt = min(cnt, PAGE_SIZE - b_pg_offset); 2613 b_m = mb[b_offset >> PAGE_SHIFT]; 2614 b_phys = VM_PAGE_TO_PHYS(b_m); 2615 if (MIPS_DIRECT_MAPPABLE(a_phys) && 2616 MIPS_DIRECT_MAPPABLE(b_phys)) { 2617 pmap_flush_pvcache(a_m); 2618 mips_dcache_wbinv_range_index( 2619 MIPS_PHYS_TO_DIRECT(b_phys), PAGE_SIZE); 2620 a_cp = (char *)MIPS_PHYS_TO_DIRECT(a_phys) + 2621 a_pg_offset; 2622 b_cp = (char *)MIPS_PHYS_TO_DIRECT(b_phys) + 2623 b_pg_offset; 2624 bcopy(a_cp, b_cp, cnt); 2625 mips_dcache_wbinv_range((vm_offset_t)b_cp, cnt); 2626 } else { 2627 a_cp = (char *)pmap_lmem_map2(a_phys, b_phys); 2628 b_cp = (char *)a_cp + PAGE_SIZE; 2629 a_cp += a_pg_offset; 2630 b_cp += b_pg_offset; 2631 bcopy(a_cp, b_cp, cnt); 2632 mips_dcache_wbinv_range((vm_offset_t)b_cp, cnt); 2633 pmap_lmem_unmap(); 2634 } 2635 a_offset += cnt; 2636 b_offset += cnt; 2637 xfersize -= cnt; 2638 } 2639 } 2640 2641 /* 2642 * Returns true if the pmap's pv is one of the first 2643 * 16 pvs linked to from this page. This count may 2644 * be changed upwards or downwards in the future; it 2645 * is only necessary that true be returned for a small 2646 * subset of pmaps for proper page aging. 2647 */ 2648 boolean_t 2649 pmap_page_exists_quick(pmap_t pmap, vm_page_t m) 2650 { 2651 pv_entry_t pv; 2652 int loops = 0; 2653 boolean_t rv; 2654 2655 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 2656 ("pmap_page_exists_quick: page %p is not managed", m)); 2657 rv = FALSE; 2658 rw_wlock(&pvh_global_lock); 2659 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) { 2660 if (PV_PMAP(pv) == pmap) { 2661 rv = TRUE; 2662 break; 2663 } 2664 loops++; 2665 if (loops >= 16) 2666 break; 2667 } 2668 rw_wunlock(&pvh_global_lock); 2669 return (rv); 2670 } 2671 2672 /* 2673 * Remove all pages from specified address space 2674 * this aids process exit speeds. Also, this code 2675 * is special cased for current process only, but 2676 * can have the more generic (and slightly slower) 2677 * mode enabled. This is much faster than pmap_remove 2678 * in the case of running down an entire address space. 2679 */ 2680 void 2681 pmap_remove_pages(pmap_t pmap) 2682 { 2683 pd_entry_t *pde; 2684 pt_entry_t *pte, tpte; 2685 pv_entry_t pv; 2686 vm_page_t m; 2687 struct pv_chunk *pc, *npc; 2688 u_long inuse, bitmask; 2689 int allfree, bit, field, idx; 2690 2691 if (pmap != vmspace_pmap(curthread->td_proc->p_vmspace)) { 2692 printf("warning: pmap_remove_pages called with non-current pmap\n"); 2693 return; 2694 } 2695 rw_wlock(&pvh_global_lock); 2696 PMAP_LOCK(pmap); 2697 TAILQ_FOREACH_SAFE(pc, &pmap->pm_pvchunk, pc_list, npc) { 2698 allfree = 1; 2699 for (field = 0; field < _NPCM; field++) { 2700 inuse = ~pc->pc_map[field] & pc_freemask[field]; 2701 while (inuse != 0) { 2702 bit = ffsl(inuse) - 1; 2703 bitmask = 1UL << bit; 2704 idx = field * sizeof(inuse) * NBBY + bit; 2705 pv = &pc->pc_pventry[idx]; 2706 inuse &= ~bitmask; 2707 2708 pde = pmap_pde(pmap, pv->pv_va); 2709 KASSERT(pde != NULL && *pde != 0, 2710 ("pmap_remove_pages: pde")); 2711 pte = pmap_pde_to_pte(pde, pv->pv_va); 2712 if (!pte_test(pte, PTE_V)) 2713 panic("pmap_remove_pages: bad pte"); 2714 tpte = *pte; 2715 2716 /* 2717 * We cannot remove wired pages from a process' mapping at this time 2718 */ 2719 if (pte_test(&tpte, PTE_W)) { 2720 allfree = 0; 2721 continue; 2722 } 2723 *pte = is_kernel_pmap(pmap) ? PTE_G : 0; 2724 2725 m = PHYS_TO_VM_PAGE(TLBLO_PTE_TO_PA(tpte)); 2726 KASSERT(m != NULL, 2727 ("pmap_remove_pages: bad tpte %#jx", 2728 (uintmax_t)tpte)); 2729 2730 /* 2731 * Update the vm_page_t clean and reference bits. 2732 */ 2733 if (pte_test(&tpte, PTE_D)) 2734 vm_page_dirty(m); 2735 2736 /* Mark free */ 2737 PV_STAT(pv_entry_frees++); 2738 PV_STAT(pv_entry_spare++); 2739 pv_entry_count--; 2740 pc->pc_map[field] |= bitmask; 2741 pmap->pm_stats.resident_count--; 2742 TAILQ_REMOVE(&m->md.pv_list, pv, pv_list); 2743 if (TAILQ_EMPTY(&m->md.pv_list)) 2744 vm_page_aflag_clear(m, PGA_WRITEABLE); 2745 pmap_unuse_pt(pmap, pv->pv_va, *pde); 2746 } 2747 } 2748 if (allfree) { 2749 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list); 2750 free_pv_chunk(pc); 2751 } 2752 } 2753 pmap_invalidate_all(pmap); 2754 PMAP_UNLOCK(pmap); 2755 rw_wunlock(&pvh_global_lock); 2756 } 2757 2758 /* 2759 * pmap_testbit tests bits in pte's 2760 */ 2761 static boolean_t 2762 pmap_testbit(vm_page_t m, int bit) 2763 { 2764 pv_entry_t pv; 2765 pmap_t pmap; 2766 pt_entry_t *pte; 2767 boolean_t rv = FALSE; 2768 2769 if (m->oflags & VPO_UNMANAGED) 2770 return (rv); 2771 2772 rw_assert(&pvh_global_lock, RA_WLOCKED); 2773 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) { 2774 pmap = PV_PMAP(pv); 2775 PMAP_LOCK(pmap); 2776 pte = pmap_pte(pmap, pv->pv_va); 2777 rv = pte_test(pte, bit); 2778 PMAP_UNLOCK(pmap); 2779 if (rv) 2780 break; 2781 } 2782 return (rv); 2783 } 2784 2785 /* 2786 * pmap_page_wired_mappings: 2787 * 2788 * Return the number of managed mappings to the given physical page 2789 * that are wired. 2790 */ 2791 int 2792 pmap_page_wired_mappings(vm_page_t m) 2793 { 2794 pv_entry_t pv; 2795 pmap_t pmap; 2796 pt_entry_t *pte; 2797 int count; 2798 2799 count = 0; 2800 if ((m->oflags & VPO_UNMANAGED) != 0) 2801 return (count); 2802 rw_wlock(&pvh_global_lock); 2803 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) { 2804 pmap = PV_PMAP(pv); 2805 PMAP_LOCK(pmap); 2806 pte = pmap_pte(pmap, pv->pv_va); 2807 if (pte_test(pte, PTE_W)) 2808 count++; 2809 PMAP_UNLOCK(pmap); 2810 } 2811 rw_wunlock(&pvh_global_lock); 2812 return (count); 2813 } 2814 2815 /* 2816 * Clear the write and modified bits in each of the given page's mappings. 2817 */ 2818 void 2819 pmap_remove_write(vm_page_t m) 2820 { 2821 pmap_t pmap; 2822 pt_entry_t pbits, *pte; 2823 pv_entry_t pv; 2824 2825 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 2826 ("pmap_remove_write: page %p is not managed", m)); 2827 2828 /* 2829 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be 2830 * set by another thread while the object is locked. Thus, 2831 * if PGA_WRITEABLE is clear, no page table entries need updating. 2832 */ 2833 VM_OBJECT_ASSERT_WLOCKED(m->object); 2834 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0) 2835 return; 2836 rw_wlock(&pvh_global_lock); 2837 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) { 2838 pmap = PV_PMAP(pv); 2839 PMAP_LOCK(pmap); 2840 pte = pmap_pte(pmap, pv->pv_va); 2841 KASSERT(pte != NULL && pte_test(pte, PTE_V), 2842 ("page on pv_list has no pte")); 2843 pbits = *pte; 2844 if (pte_test(&pbits, PTE_D)) { 2845 pte_clear(&pbits, PTE_D); 2846 vm_page_dirty(m); 2847 } 2848 pte_set(&pbits, PTE_RO); 2849 if (pbits != *pte) { 2850 *pte = pbits; 2851 pmap_update_page(pmap, pv->pv_va, pbits); 2852 } 2853 PMAP_UNLOCK(pmap); 2854 } 2855 vm_page_aflag_clear(m, PGA_WRITEABLE); 2856 rw_wunlock(&pvh_global_lock); 2857 } 2858 2859 /* 2860 * pmap_ts_referenced: 2861 * 2862 * Return the count of reference bits for a page, clearing all of them. 2863 */ 2864 int 2865 pmap_ts_referenced(vm_page_t m) 2866 { 2867 2868 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 2869 ("pmap_ts_referenced: page %p is not managed", m)); 2870 if (m->md.pv_flags & PV_TABLE_REF) { 2871 rw_wlock(&pvh_global_lock); 2872 m->md.pv_flags &= ~PV_TABLE_REF; 2873 rw_wunlock(&pvh_global_lock); 2874 return (1); 2875 } 2876 return (0); 2877 } 2878 2879 /* 2880 * pmap_is_modified: 2881 * 2882 * Return whether or not the specified physical page was modified 2883 * in any physical maps. 2884 */ 2885 boolean_t 2886 pmap_is_modified(vm_page_t m) 2887 { 2888 boolean_t rv; 2889 2890 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 2891 ("pmap_is_modified: page %p is not managed", m)); 2892 2893 /* 2894 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be 2895 * concurrently set while the object is locked. Thus, if PGA_WRITEABLE 2896 * is clear, no PTEs can have PTE_D set. 2897 */ 2898 VM_OBJECT_ASSERT_WLOCKED(m->object); 2899 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0) 2900 return (FALSE); 2901 rw_wlock(&pvh_global_lock); 2902 rv = pmap_testbit(m, PTE_D); 2903 rw_wunlock(&pvh_global_lock); 2904 return (rv); 2905 } 2906 2907 /* N/C */ 2908 2909 /* 2910 * pmap_is_prefaultable: 2911 * 2912 * Return whether or not the specified virtual address is elgible 2913 * for prefault. 2914 */ 2915 boolean_t 2916 pmap_is_prefaultable(pmap_t pmap, vm_offset_t addr) 2917 { 2918 pd_entry_t *pde; 2919 pt_entry_t *pte; 2920 boolean_t rv; 2921 2922 rv = FALSE; 2923 PMAP_LOCK(pmap); 2924 pde = pmap_pde(pmap, addr); 2925 if (pde != NULL && *pde != 0) { 2926 pte = pmap_pde_to_pte(pde, addr); 2927 rv = (*pte == 0); 2928 } 2929 PMAP_UNLOCK(pmap); 2930 return (rv); 2931 } 2932 2933 /* 2934 * Apply the given advice to the specified range of addresses within the 2935 * given pmap. Depending on the advice, clear the referenced and/or 2936 * modified flags in each mapping and set the mapped page's dirty field. 2937 */ 2938 void 2939 pmap_advise(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, int advice) 2940 { 2941 pd_entry_t *pde, *pdpe; 2942 pt_entry_t *pte; 2943 vm_offset_t va, va_next; 2944 vm_paddr_t pa; 2945 vm_page_t m; 2946 2947 if (advice != MADV_DONTNEED && advice != MADV_FREE) 2948 return; 2949 rw_wlock(&pvh_global_lock); 2950 PMAP_LOCK(pmap); 2951 for (; sva < eva; sva = va_next) { 2952 pdpe = pmap_segmap(pmap, sva); 2953 #ifdef __mips_n64 2954 if (*pdpe == 0) { 2955 va_next = (sva + NBSEG) & ~SEGMASK; 2956 if (va_next < sva) 2957 va_next = eva; 2958 continue; 2959 } 2960 #endif 2961 va_next = (sva + NBPDR) & ~PDRMASK; 2962 if (va_next < sva) 2963 va_next = eva; 2964 2965 pde = pmap_pdpe_to_pde(pdpe, sva); 2966 if (*pde == NULL) 2967 continue; 2968 2969 /* 2970 * Limit our scan to either the end of the va represented 2971 * by the current page table page, or to the end of the 2972 * range being write protected. 2973 */ 2974 if (va_next > eva) 2975 va_next = eva; 2976 2977 va = va_next; 2978 for (pte = pmap_pde_to_pte(pde, sva); sva != va_next; pte++, 2979 sva += PAGE_SIZE) { 2980 if (!pte_test(pte, PTE_MANAGED | PTE_V)) { 2981 if (va != va_next) { 2982 pmap_invalidate_range(pmap, va, sva); 2983 va = va_next; 2984 } 2985 continue; 2986 } 2987 pa = TLBLO_PTE_TO_PA(*pte); 2988 m = PHYS_TO_VM_PAGE(pa); 2989 m->md.pv_flags &= ~PV_TABLE_REF; 2990 if (pte_test(pte, PTE_D)) { 2991 if (advice == MADV_DONTNEED) { 2992 /* 2993 * Future calls to pmap_is_modified() 2994 * can be avoided by making the page 2995 * dirty now. 2996 */ 2997 vm_page_dirty(m); 2998 } else { 2999 pte_clear(pte, PTE_D); 3000 if (va == va_next) 3001 va = sva; 3002 } 3003 } else { 3004 /* 3005 * Unless PTE_D is set, any TLB entries 3006 * mapping "sva" don't allow write access, so 3007 * they needn't be invalidated. 3008 */ 3009 if (va != va_next) { 3010 pmap_invalidate_range(pmap, va, sva); 3011 va = va_next; 3012 } 3013 } 3014 } 3015 if (va != va_next) 3016 pmap_invalidate_range(pmap, va, sva); 3017 } 3018 rw_wunlock(&pvh_global_lock); 3019 PMAP_UNLOCK(pmap); 3020 } 3021 3022 /* 3023 * Clear the modify bits on the specified physical page. 3024 */ 3025 void 3026 pmap_clear_modify(vm_page_t m) 3027 { 3028 pmap_t pmap; 3029 pt_entry_t *pte; 3030 pv_entry_t pv; 3031 3032 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 3033 ("pmap_clear_modify: page %p is not managed", m)); 3034 VM_OBJECT_ASSERT_WLOCKED(m->object); 3035 KASSERT(!vm_page_xbusied(m), 3036 ("pmap_clear_modify: page %p is exclusive busied", m)); 3037 3038 /* 3039 * If the page is not PGA_WRITEABLE, then no PTEs can have PTE_D set. 3040 * If the object containing the page is locked and the page is not 3041 * write busied, then PGA_WRITEABLE cannot be concurrently set. 3042 */ 3043 if ((m->aflags & PGA_WRITEABLE) == 0) 3044 return; 3045 rw_wlock(&pvh_global_lock); 3046 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) { 3047 pmap = PV_PMAP(pv); 3048 PMAP_LOCK(pmap); 3049 pte = pmap_pte(pmap, pv->pv_va); 3050 if (pte_test(pte, PTE_D)) { 3051 pte_clear(pte, PTE_D); 3052 pmap_update_page(pmap, pv->pv_va, *pte); 3053 } 3054 PMAP_UNLOCK(pmap); 3055 } 3056 rw_wunlock(&pvh_global_lock); 3057 } 3058 3059 /* 3060 * pmap_is_referenced: 3061 * 3062 * Return whether or not the specified physical page was referenced 3063 * in any physical maps. 3064 */ 3065 boolean_t 3066 pmap_is_referenced(vm_page_t m) 3067 { 3068 3069 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 3070 ("pmap_is_referenced: page %p is not managed", m)); 3071 return ((m->md.pv_flags & PV_TABLE_REF) != 0); 3072 } 3073 3074 /* 3075 * Miscellaneous support routines follow 3076 */ 3077 3078 /* 3079 * Map a set of physical memory pages into the kernel virtual 3080 * address space. Return a pointer to where it is mapped. This 3081 * routine is intended to be used for mapping device memory, 3082 * NOT real memory. 3083 * 3084 * Use XKPHYS uncached for 64 bit, and KSEG1 where possible for 32 bit. 3085 */ 3086 void * 3087 pmap_mapdev(vm_paddr_t pa, vm_size_t size) 3088 { 3089 vm_offset_t va, tmpva, offset; 3090 3091 /* 3092 * KSEG1 maps only first 512M of phys address space. For 3093 * pa > 0x20000000 we should make proper mapping * using pmap_kenter. 3094 */ 3095 if (MIPS_DIRECT_MAPPABLE(pa + size - 1)) 3096 return ((void *)MIPS_PHYS_TO_DIRECT_UNCACHED(pa)); 3097 else { 3098 offset = pa & PAGE_MASK; 3099 size = roundup(size + offset, PAGE_SIZE); 3100 3101 va = kva_alloc(size); 3102 if (!va) 3103 panic("pmap_mapdev: Couldn't alloc kernel virtual memory"); 3104 pa = trunc_page(pa); 3105 for (tmpva = va; size > 0;) { 3106 pmap_kenter_attr(tmpva, pa, PTE_C_UNCACHED); 3107 size -= PAGE_SIZE; 3108 tmpva += PAGE_SIZE; 3109 pa += PAGE_SIZE; 3110 } 3111 } 3112 3113 return ((void *)(va + offset)); 3114 } 3115 3116 void 3117 pmap_unmapdev(vm_offset_t va, vm_size_t size) 3118 { 3119 #ifndef __mips_n64 3120 vm_offset_t base, offset; 3121 3122 /* If the address is within KSEG1 then there is nothing to do */ 3123 if (va >= MIPS_KSEG1_START && va <= MIPS_KSEG1_END) 3124 return; 3125 3126 base = trunc_page(va); 3127 offset = va & PAGE_MASK; 3128 size = roundup(size + offset, PAGE_SIZE); 3129 kva_free(base, size); 3130 #endif 3131 } 3132 3133 /* 3134 * perform the pmap work for mincore 3135 */ 3136 int 3137 pmap_mincore(pmap_t pmap, vm_offset_t addr, vm_paddr_t *locked_pa) 3138 { 3139 pt_entry_t *ptep, pte; 3140 vm_paddr_t pa; 3141 vm_page_t m; 3142 int val; 3143 3144 PMAP_LOCK(pmap); 3145 retry: 3146 ptep = pmap_pte(pmap, addr); 3147 pte = (ptep != NULL) ? *ptep : 0; 3148 if (!pte_test(&pte, PTE_V)) { 3149 val = 0; 3150 goto out; 3151 } 3152 val = MINCORE_INCORE; 3153 if (pte_test(&pte, PTE_D)) 3154 val |= MINCORE_MODIFIED | MINCORE_MODIFIED_OTHER; 3155 pa = TLBLO_PTE_TO_PA(pte); 3156 if (pte_test(&pte, PTE_MANAGED)) { 3157 /* 3158 * This may falsely report the given address as 3159 * MINCORE_REFERENCED. Unfortunately, due to the lack of 3160 * per-PTE reference information, it is impossible to 3161 * determine if the address is MINCORE_REFERENCED. 3162 */ 3163 m = PHYS_TO_VM_PAGE(pa); 3164 if ((m->aflags & PGA_REFERENCED) != 0) 3165 val |= MINCORE_REFERENCED | MINCORE_REFERENCED_OTHER; 3166 } 3167 if ((val & (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER)) != 3168 (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER) && 3169 pte_test(&pte, PTE_MANAGED)) { 3170 /* Ensure that "PHYS_TO_VM_PAGE(pa)->object" doesn't change. */ 3171 if (vm_page_pa_tryrelock(pmap, pa, locked_pa)) 3172 goto retry; 3173 } else 3174 out: 3175 PA_UNLOCK_COND(*locked_pa); 3176 PMAP_UNLOCK(pmap); 3177 return (val); 3178 } 3179 3180 void 3181 pmap_activate(struct thread *td) 3182 { 3183 pmap_t pmap, oldpmap; 3184 struct proc *p = td->td_proc; 3185 u_int cpuid; 3186 3187 critical_enter(); 3188 3189 pmap = vmspace_pmap(p->p_vmspace); 3190 oldpmap = PCPU_GET(curpmap); 3191 cpuid = PCPU_GET(cpuid); 3192 3193 if (oldpmap) 3194 CPU_CLR_ATOMIC(cpuid, &oldpmap->pm_active); 3195 CPU_SET_ATOMIC(cpuid, &pmap->pm_active); 3196 pmap_asid_alloc(pmap); 3197 if (td == curthread) { 3198 PCPU_SET(segbase, pmap->pm_segtab); 3199 mips_wr_entryhi(pmap->pm_asid[cpuid].asid); 3200 } 3201 3202 PCPU_SET(curpmap, pmap); 3203 critical_exit(); 3204 } 3205 3206 void 3207 pmap_sync_icache(pmap_t pm, vm_offset_t va, vm_size_t sz) 3208 { 3209 } 3210 3211 /* 3212 * Increase the starting virtual address of the given mapping if a 3213 * different alignment might result in more superpage mappings. 3214 */ 3215 void 3216 pmap_align_superpage(vm_object_t object, vm_ooffset_t offset, 3217 vm_offset_t *addr, vm_size_t size) 3218 { 3219 vm_offset_t superpage_offset; 3220 3221 if (size < NBSEG) 3222 return; 3223 if (object != NULL && (object->flags & OBJ_COLORED) != 0) 3224 offset += ptoa(object->pg_color); 3225 superpage_offset = offset & SEGMASK; 3226 if (size - ((NBSEG - superpage_offset) & SEGMASK) < NBSEG || 3227 (*addr & SEGMASK) == superpage_offset) 3228 return; 3229 if ((*addr & SEGMASK) < superpage_offset) 3230 *addr = (*addr & ~SEGMASK) + superpage_offset; 3231 else 3232 *addr = ((*addr + SEGMASK) & ~SEGMASK) + superpage_offset; 3233 } 3234 3235 #ifdef DDB 3236 DB_SHOW_COMMAND(ptable, ddb_pid_dump) 3237 { 3238 pmap_t pmap; 3239 struct thread *td = NULL; 3240 struct proc *p; 3241 int i, j, k; 3242 vm_paddr_t pa; 3243 vm_offset_t va; 3244 3245 if (have_addr) { 3246 td = db_lookup_thread(addr, TRUE); 3247 if (td == NULL) { 3248 db_printf("Invalid pid or tid"); 3249 return; 3250 } 3251 p = td->td_proc; 3252 if (p->p_vmspace == NULL) { 3253 db_printf("No vmspace for process"); 3254 return; 3255 } 3256 pmap = vmspace_pmap(p->p_vmspace); 3257 } else 3258 pmap = kernel_pmap; 3259 3260 db_printf("pmap:%p segtab:%p asid:%x generation:%x\n", 3261 pmap, pmap->pm_segtab, pmap->pm_asid[0].asid, 3262 pmap->pm_asid[0].gen); 3263 for (i = 0; i < NPDEPG; i++) { 3264 pd_entry_t *pdpe; 3265 pt_entry_t *pde; 3266 pt_entry_t pte; 3267 3268 pdpe = (pd_entry_t *)pmap->pm_segtab[i]; 3269 if (pdpe == NULL) 3270 continue; 3271 db_printf("[%4d] %p\n", i, pdpe); 3272 #ifdef __mips_n64 3273 for (j = 0; j < NPDEPG; j++) { 3274 pde = (pt_entry_t *)pdpe[j]; 3275 if (pde == NULL) 3276 continue; 3277 db_printf("\t[%4d] %p\n", j, pde); 3278 #else 3279 { 3280 j = 0; 3281 pde = (pt_entry_t *)pdpe; 3282 #endif 3283 for (k = 0; k < NPTEPG; k++) { 3284 pte = pde[k]; 3285 if (pte == 0 || !pte_test(&pte, PTE_V)) 3286 continue; 3287 pa = TLBLO_PTE_TO_PA(pte); 3288 va = ((u_long)i << SEGSHIFT) | (j << PDRSHIFT) | (k << PAGE_SHIFT); 3289 db_printf("\t\t[%04d] va: %p pte: %8jx pa:%jx\n", 3290 k, (void *)va, (uintmax_t)pte, (uintmax_t)pa); 3291 } 3292 } 3293 } 3294 } 3295 #endif 3296 3297 #if defined(DEBUG) 3298 3299 static void pads(pmap_t pm); 3300 void pmap_pvdump(vm_offset_t pa); 3301 3302 /* print address space of pmap*/ 3303 static void 3304 pads(pmap_t pm) 3305 { 3306 unsigned va, i, j; 3307 pt_entry_t *ptep; 3308 3309 if (pm == kernel_pmap) 3310 return; 3311 for (i = 0; i < NPTEPG; i++) 3312 if (pm->pm_segtab[i]) 3313 for (j = 0; j < NPTEPG; j++) { 3314 va = (i << SEGSHIFT) + (j << PAGE_SHIFT); 3315 if (pm == kernel_pmap && va < KERNBASE) 3316 continue; 3317 if (pm != kernel_pmap && 3318 va >= VM_MAXUSER_ADDRESS) 3319 continue; 3320 ptep = pmap_pte(pm, va); 3321 if (pte_test(ptep, PTE_V)) 3322 printf("%x:%x ", va, *(int *)ptep); 3323 } 3324 3325 } 3326 3327 void 3328 pmap_pvdump(vm_offset_t pa) 3329 { 3330 register pv_entry_t pv; 3331 vm_page_t m; 3332 3333 printf("pa %x", pa); 3334 m = PHYS_TO_VM_PAGE(pa); 3335 for (pv = TAILQ_FIRST(&m->md.pv_list); pv; 3336 pv = TAILQ_NEXT(pv, pv_list)) { 3337 printf(" -> pmap %p, va %x", (void *)pv->pv_pmap, pv->pv_va); 3338 pads(pv->pv_pmap); 3339 } 3340 printf(" "); 3341 } 3342 3343 /* N/C */ 3344 #endif 3345 3346 3347 /* 3348 * Allocate TLB address space tag (called ASID or TLBPID) and return it. 3349 * It takes almost as much or more time to search the TLB for a 3350 * specific ASID and flush those entries as it does to flush the entire TLB. 3351 * Therefore, when we allocate a new ASID, we just take the next number. When 3352 * we run out of numbers, we flush the TLB, increment the generation count 3353 * and start over. ASID zero is reserved for kernel use. 3354 */ 3355 static void 3356 pmap_asid_alloc(pmap) 3357 pmap_t pmap; 3358 { 3359 if (pmap->pm_asid[PCPU_GET(cpuid)].asid != PMAP_ASID_RESERVED && 3360 pmap->pm_asid[PCPU_GET(cpuid)].gen == PCPU_GET(asid_generation)); 3361 else { 3362 if (PCPU_GET(next_asid) == pmap_max_asid) { 3363 tlb_invalidate_all_user(NULL); 3364 PCPU_SET(asid_generation, 3365 (PCPU_GET(asid_generation) + 1) & ASIDGEN_MASK); 3366 if (PCPU_GET(asid_generation) == 0) { 3367 PCPU_SET(asid_generation, 1); 3368 } 3369 PCPU_SET(next_asid, 1); /* 0 means invalid */ 3370 } 3371 pmap->pm_asid[PCPU_GET(cpuid)].asid = PCPU_GET(next_asid); 3372 pmap->pm_asid[PCPU_GET(cpuid)].gen = PCPU_GET(asid_generation); 3373 PCPU_SET(next_asid, PCPU_GET(next_asid) + 1); 3374 } 3375 } 3376 3377 static pt_entry_t 3378 init_pte_prot(vm_page_t m, vm_prot_t access, vm_prot_t prot) 3379 { 3380 pt_entry_t rw; 3381 3382 if (!(prot & VM_PROT_WRITE)) 3383 rw = PTE_V | PTE_RO; 3384 else if ((m->oflags & VPO_UNMANAGED) == 0) { 3385 if ((access & VM_PROT_WRITE) != 0) 3386 rw = PTE_V | PTE_D; 3387 else 3388 rw = PTE_V; 3389 } else 3390 /* Needn't emulate a modified bit for unmanaged pages. */ 3391 rw = PTE_V | PTE_D; 3392 return (rw); 3393 } 3394 3395 /* 3396 * pmap_emulate_modified : do dirty bit emulation 3397 * 3398 * On SMP, update just the local TLB, other CPUs will update their 3399 * TLBs from PTE lazily, if they get the exception. 3400 * Returns 0 in case of sucess, 1 if the page is read only and we 3401 * need to fault. 3402 */ 3403 int 3404 pmap_emulate_modified(pmap_t pmap, vm_offset_t va) 3405 { 3406 pt_entry_t *pte; 3407 3408 PMAP_LOCK(pmap); 3409 pte = pmap_pte(pmap, va); 3410 if (pte == NULL) 3411 panic("pmap_emulate_modified: can't find PTE"); 3412 #ifdef SMP 3413 /* It is possible that some other CPU changed m-bit */ 3414 if (!pte_test(pte, PTE_V) || pte_test(pte, PTE_D)) { 3415 tlb_update(pmap, va, *pte); 3416 PMAP_UNLOCK(pmap); 3417 return (0); 3418 } 3419 #else 3420 if (!pte_test(pte, PTE_V) || pte_test(pte, PTE_D)) 3421 panic("pmap_emulate_modified: invalid pte"); 3422 #endif 3423 if (pte_test(pte, PTE_RO)) { 3424 PMAP_UNLOCK(pmap); 3425 return (1); 3426 } 3427 pte_set(pte, PTE_D); 3428 tlb_update(pmap, va, *pte); 3429 if (!pte_test(pte, PTE_MANAGED)) 3430 panic("pmap_emulate_modified: unmanaged page"); 3431 PMAP_UNLOCK(pmap); 3432 return (0); 3433 } 3434 3435 /* 3436 * Routine: pmap_kextract 3437 * Function: 3438 * Extract the physical page address associated 3439 * virtual address. 3440 */ 3441 vm_paddr_t 3442 pmap_kextract(vm_offset_t va) 3443 { 3444 int mapped; 3445 3446 /* 3447 * First, the direct-mapped regions. 3448 */ 3449 #if defined(__mips_n64) 3450 if (va >= MIPS_XKPHYS_START && va < MIPS_XKPHYS_END) 3451 return (MIPS_XKPHYS_TO_PHYS(va)); 3452 #endif 3453 if (va >= MIPS_KSEG0_START && va < MIPS_KSEG0_END) 3454 return (MIPS_KSEG0_TO_PHYS(va)); 3455 3456 if (va >= MIPS_KSEG1_START && va < MIPS_KSEG1_END) 3457 return (MIPS_KSEG1_TO_PHYS(va)); 3458 3459 /* 3460 * User virtual addresses. 3461 */ 3462 if (va < VM_MAXUSER_ADDRESS) { 3463 pt_entry_t *ptep; 3464 3465 if (curproc && curproc->p_vmspace) { 3466 ptep = pmap_pte(&curproc->p_vmspace->vm_pmap, va); 3467 if (ptep) { 3468 return (TLBLO_PTE_TO_PA(*ptep) | 3469 (va & PAGE_MASK)); 3470 } 3471 return (0); 3472 } 3473 } 3474 3475 /* 3476 * Should be kernel virtual here, otherwise fail 3477 */ 3478 mapped = (va >= MIPS_KSEG2_START || va < MIPS_KSEG2_END); 3479 #if defined(__mips_n64) 3480 mapped = mapped || (va >= MIPS_XKSEG_START || va < MIPS_XKSEG_END); 3481 #endif 3482 /* 3483 * Kernel virtual. 3484 */ 3485 3486 if (mapped) { 3487 pt_entry_t *ptep; 3488 3489 /* Is the kernel pmap initialized? */ 3490 if (!CPU_EMPTY(&kernel_pmap->pm_active)) { 3491 /* It's inside the virtual address range */ 3492 ptep = pmap_pte(kernel_pmap, va); 3493 if (ptep) { 3494 return (TLBLO_PTE_TO_PA(*ptep) | 3495 (va & PAGE_MASK)); 3496 } 3497 } 3498 return (0); 3499 } 3500 3501 panic("%s for unknown address space %p.", __func__, (void *)va); 3502 } 3503 3504 3505 void 3506 pmap_flush_pvcache(vm_page_t m) 3507 { 3508 pv_entry_t pv; 3509 3510 if (m != NULL) { 3511 for (pv = TAILQ_FIRST(&m->md.pv_list); pv; 3512 pv = TAILQ_NEXT(pv, pv_list)) { 3513 mips_dcache_wbinv_range_index(pv->pv_va, PAGE_SIZE); 3514 } 3515 } 3516 }
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