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sys/mips/mips/pmap.c
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1 /* 2 * Copyright (c) 1991 Regents of the University of California. 3 * All rights reserved. 4 * Copyright (c) 1994 John S. Dyson 5 * All rights reserved. 6 * Copyright (c) 1994 David Greenman 7 * All rights reserved. 8 * 9 * This code is derived from software contributed to Berkeley by 10 * the Systems Programming Group of the University of Utah Computer 11 * Science Department and William Jolitz of UUNET Technologies Inc. 12 * 13 * Redistribution and use in source and binary forms, with or without 14 * modification, are permitted provided that the following conditions 15 * are met: 16 * 1. Redistributions of source code must retain the above copyright 17 * notice, this list of conditions and the following disclaimer. 18 * 2. Redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution. 21 * 4. Neither the name of the University nor the names of its contributors 22 * may be used to endorse or promote products derived from this software 23 * without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 27 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 28 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 29 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 30 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 31 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 32 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 33 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 34 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 35 * SUCH DAMAGE. 36 * 37 * from: @(#)pmap.c 7.7 (Berkeley) 5/12/91 38 * from: src/sys/i386/i386/pmap.c,v 1.250.2.8 2000/11/21 00:09:14 ps 39 * JNPR: pmap.c,v 1.11.2.1 2007/08/16 11:51:06 girish 40 */ 41 42 /* 43 * Manages physical address maps. 44 * 45 * Since the information managed by this module is 46 * also stored by the logical address mapping module, 47 * this module may throw away valid virtual-to-physical 48 * mappings at almost any time. However, invalidations 49 * of virtual-to-physical mappings must be done as 50 * requested. 51 * 52 * In order to cope with hardware architectures which 53 * make virtual-to-physical map invalidates expensive, 54 * this module may delay invalidate or reduced protection 55 * operations until such time as they are actually 56 * necessary. This module is given full information as 57 * to which processors are currently using which maps, 58 * and to when physical maps must be made correct. 59 */ 60 61 #include <sys/cdefs.h> 62 __FBSDID("$FreeBSD: releng/11.0/sys/mips/mips/pmap.c 298859 2016-04-30 19:29:03Z rwatson $"); 63 64 #include "opt_ddb.h" 65 #include "opt_pmap.h" 66 67 #include <sys/param.h> 68 #include <sys/systm.h> 69 #include <sys/lock.h> 70 #include <sys/mman.h> 71 #include <sys/msgbuf.h> 72 #include <sys/mutex.h> 73 #include <sys/pcpu.h> 74 #include <sys/proc.h> 75 #include <sys/rwlock.h> 76 #include <sys/sched.h> 77 #ifdef SMP 78 #include <sys/smp.h> 79 #else 80 #include <sys/cpuset.h> 81 #endif 82 #include <sys/sysctl.h> 83 #include <sys/vmmeter.h> 84 85 #ifdef DDB 86 #include <ddb/ddb.h> 87 #endif 88 89 #include <vm/vm.h> 90 #include <vm/vm_param.h> 91 #include <vm/vm_kern.h> 92 #include <vm/vm_page.h> 93 #include <vm/vm_map.h> 94 #include <vm/vm_object.h> 95 #include <vm/vm_extern.h> 96 #include <vm/vm_pageout.h> 97 #include <vm/vm_pager.h> 98 #include <vm/uma.h> 99 100 #include <machine/cache.h> 101 #include <machine/md_var.h> 102 #include <machine/tlb.h> 103 104 #undef PMAP_DEBUG 105 106 #if !defined(DIAGNOSTIC) 107 #define PMAP_INLINE __inline 108 #else 109 #define PMAP_INLINE 110 #endif 111 112 #ifdef PV_STATS 113 #define PV_STAT(x) do { x ; } while (0) 114 #else 115 #define PV_STAT(x) do { } while (0) 116 #endif 117 118 /* 119 * Get PDEs and PTEs for user/kernel address space 120 */ 121 #define pmap_seg_index(v) (((v) >> SEGSHIFT) & (NPDEPG - 1)) 122 #define pmap_pde_index(v) (((v) >> PDRSHIFT) & (NPDEPG - 1)) 123 #define pmap_pte_index(v) (((v) >> PAGE_SHIFT) & (NPTEPG - 1)) 124 #define pmap_pde_pindex(v) ((v) >> PDRSHIFT) 125 126 #ifdef __mips_n64 127 #define NUPDE (NPDEPG * NPDEPG) 128 #define NUSERPGTBLS (NUPDE + NPDEPG) 129 #else 130 #define NUPDE (NPDEPG) 131 #define NUSERPGTBLS (NUPDE) 132 #endif 133 134 #define is_kernel_pmap(x) ((x) == kernel_pmap) 135 136 struct pmap kernel_pmap_store; 137 pd_entry_t *kernel_segmap; 138 139 vm_offset_t virtual_avail; /* VA of first avail page (after kernel bss) */ 140 vm_offset_t virtual_end; /* VA of last avail page (end of kernel AS) */ 141 142 static int nkpt; 143 unsigned pmap_max_asid; /* max ASID supported by the system */ 144 145 #define PMAP_ASID_RESERVED 0 146 147 vm_offset_t kernel_vm_end = VM_MIN_KERNEL_ADDRESS; 148 149 static void pmap_asid_alloc(pmap_t pmap); 150 151 static struct rwlock_padalign pvh_global_lock; 152 153 /* 154 * Data for the pv entry allocation mechanism 155 */ 156 static TAILQ_HEAD(pch, pv_chunk) pv_chunks = TAILQ_HEAD_INITIALIZER(pv_chunks); 157 static int pv_entry_count; 158 159 static void free_pv_chunk(struct pv_chunk *pc); 160 static void free_pv_entry(pmap_t pmap, pv_entry_t pv); 161 static pv_entry_t get_pv_entry(pmap_t pmap, boolean_t try); 162 static vm_page_t pmap_pv_reclaim(pmap_t locked_pmap); 163 static void pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va); 164 static pv_entry_t pmap_pvh_remove(struct md_page *pvh, pmap_t pmap, 165 vm_offset_t va); 166 static vm_page_t pmap_alloc_direct_page(unsigned int index, int req); 167 static vm_page_t pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va, 168 vm_page_t m, vm_prot_t prot, vm_page_t mpte); 169 static void pmap_grow_direct_page(int req); 170 static int pmap_remove_pte(struct pmap *pmap, pt_entry_t *ptq, vm_offset_t va, 171 pd_entry_t pde); 172 static void pmap_remove_page(struct pmap *pmap, vm_offset_t va); 173 static void pmap_remove_entry(struct pmap *pmap, vm_page_t m, vm_offset_t va); 174 static boolean_t pmap_try_insert_pv_entry(pmap_t pmap, vm_page_t mpte, 175 vm_offset_t va, vm_page_t m); 176 static void pmap_update_page(pmap_t pmap, vm_offset_t va, pt_entry_t pte); 177 static void pmap_invalidate_all(pmap_t pmap); 178 static void pmap_invalidate_page(pmap_t pmap, vm_offset_t va); 179 static void _pmap_unwire_ptp(pmap_t pmap, vm_offset_t va, vm_page_t m); 180 181 static vm_page_t pmap_allocpte(pmap_t pmap, vm_offset_t va, u_int flags); 182 static vm_page_t _pmap_allocpte(pmap_t pmap, unsigned ptepindex, u_int flags); 183 static int pmap_unuse_pt(pmap_t, vm_offset_t, pd_entry_t); 184 static pt_entry_t init_pte_prot(vm_page_t m, vm_prot_t access, vm_prot_t prot); 185 186 static void pmap_invalidate_page_action(void *arg); 187 static void pmap_invalidate_range_action(void *arg); 188 static void pmap_update_page_action(void *arg); 189 190 #ifndef __mips_n64 191 /* 192 * This structure is for high memory (memory above 512Meg in 32 bit) support. 193 * The highmem area does not have a KSEG0 mapping, and we need a mechanism to 194 * do temporary per-CPU mappings for pmap_zero_page, pmap_copy_page etc. 195 * 196 * At bootup, we reserve 2 virtual pages per CPU for mapping highmem pages. To 197 * access a highmem physical address on a CPU, we map the physical address to 198 * the reserved virtual address for the CPU in the kernel pagetable. This is 199 * done with interrupts disabled(although a spinlock and sched_pin would be 200 * sufficient). 201 */ 202 struct local_sysmaps { 203 vm_offset_t base; 204 uint32_t saved_intr; 205 uint16_t valid1, valid2; 206 }; 207 static struct local_sysmaps sysmap_lmem[MAXCPU]; 208 209 static __inline void 210 pmap_alloc_lmem_map(void) 211 { 212 int i; 213 214 for (i = 0; i < MAXCPU; i++) { 215 sysmap_lmem[i].base = virtual_avail; 216 virtual_avail += PAGE_SIZE * 2; 217 sysmap_lmem[i].valid1 = sysmap_lmem[i].valid2 = 0; 218 } 219 } 220 221 static __inline vm_offset_t 222 pmap_lmem_map1(vm_paddr_t phys) 223 { 224 struct local_sysmaps *sysm; 225 pt_entry_t *pte, npte; 226 vm_offset_t va; 227 uint32_t intr; 228 int cpu; 229 230 intr = intr_disable(); 231 cpu = PCPU_GET(cpuid); 232 sysm = &sysmap_lmem[cpu]; 233 sysm->saved_intr = intr; 234 va = sysm->base; 235 npte = TLBLO_PA_TO_PFN(phys) | PTE_C_CACHE | PTE_D | PTE_V | PTE_G; 236 pte = pmap_pte(kernel_pmap, va); 237 *pte = npte; 238 sysm->valid1 = 1; 239 return (va); 240 } 241 242 static __inline vm_offset_t 243 pmap_lmem_map2(vm_paddr_t phys1, vm_paddr_t phys2) 244 { 245 struct local_sysmaps *sysm; 246 pt_entry_t *pte, npte; 247 vm_offset_t va1, va2; 248 uint32_t intr; 249 int cpu; 250 251 intr = intr_disable(); 252 cpu = PCPU_GET(cpuid); 253 sysm = &sysmap_lmem[cpu]; 254 sysm->saved_intr = intr; 255 va1 = sysm->base; 256 va2 = sysm->base + PAGE_SIZE; 257 npte = TLBLO_PA_TO_PFN(phys1) | PTE_C_CACHE | PTE_D | PTE_V | PTE_G; 258 pte = pmap_pte(kernel_pmap, va1); 259 *pte = npte; 260 npte = TLBLO_PA_TO_PFN(phys2) | PTE_C_CACHE | PTE_D | PTE_V | PTE_G; 261 pte = pmap_pte(kernel_pmap, va2); 262 *pte = npte; 263 sysm->valid1 = 1; 264 sysm->valid2 = 1; 265 return (va1); 266 } 267 268 static __inline void 269 pmap_lmem_unmap(void) 270 { 271 struct local_sysmaps *sysm; 272 pt_entry_t *pte; 273 int cpu; 274 275 cpu = PCPU_GET(cpuid); 276 sysm = &sysmap_lmem[cpu]; 277 pte = pmap_pte(kernel_pmap, sysm->base); 278 *pte = PTE_G; 279 tlb_invalidate_address(kernel_pmap, sysm->base); 280 sysm->valid1 = 0; 281 if (sysm->valid2) { 282 pte = pmap_pte(kernel_pmap, sysm->base + PAGE_SIZE); 283 *pte = PTE_G; 284 tlb_invalidate_address(kernel_pmap, sysm->base + PAGE_SIZE); 285 sysm->valid2 = 0; 286 } 287 intr_restore(sysm->saved_intr); 288 } 289 #else /* __mips_n64 */ 290 291 static __inline void 292 pmap_alloc_lmem_map(void) 293 { 294 } 295 296 static __inline vm_offset_t 297 pmap_lmem_map1(vm_paddr_t phys) 298 { 299 300 return (0); 301 } 302 303 static __inline vm_offset_t 304 pmap_lmem_map2(vm_paddr_t phys1, vm_paddr_t phys2) 305 { 306 307 return (0); 308 } 309 310 static __inline vm_offset_t 311 pmap_lmem_unmap(void) 312 { 313 314 return (0); 315 } 316 #endif /* !__mips_n64 */ 317 318 static __inline int 319 is_cacheable_page(vm_paddr_t pa, vm_page_t m) 320 { 321 322 return ((m->md.pv_flags & PV_MEMATTR_UNCACHEABLE) == 0 && 323 is_cacheable_mem(pa)); 324 325 } 326 327 /* 328 * Page table entry lookup routines. 329 */ 330 static __inline pd_entry_t * 331 pmap_segmap(pmap_t pmap, vm_offset_t va) 332 { 333 334 return (&pmap->pm_segtab[pmap_seg_index(va)]); 335 } 336 337 #ifdef __mips_n64 338 static __inline pd_entry_t * 339 pmap_pdpe_to_pde(pd_entry_t *pdpe, vm_offset_t va) 340 { 341 pd_entry_t *pde; 342 343 pde = (pd_entry_t *)*pdpe; 344 return (&pde[pmap_pde_index(va)]); 345 } 346 347 static __inline pd_entry_t * 348 pmap_pde(pmap_t pmap, vm_offset_t va) 349 { 350 pd_entry_t *pdpe; 351 352 pdpe = pmap_segmap(pmap, va); 353 if (*pdpe == NULL) 354 return (NULL); 355 356 return (pmap_pdpe_to_pde(pdpe, va)); 357 } 358 #else 359 static __inline pd_entry_t * 360 pmap_pdpe_to_pde(pd_entry_t *pdpe, vm_offset_t va) 361 { 362 363 return (pdpe); 364 } 365 366 static __inline 367 pd_entry_t *pmap_pde(pmap_t pmap, vm_offset_t va) 368 { 369 370 return (pmap_segmap(pmap, va)); 371 } 372 #endif 373 374 static __inline pt_entry_t * 375 pmap_pde_to_pte(pd_entry_t *pde, vm_offset_t va) 376 { 377 pt_entry_t *pte; 378 379 pte = (pt_entry_t *)*pde; 380 return (&pte[pmap_pte_index(va)]); 381 } 382 383 pt_entry_t * 384 pmap_pte(pmap_t pmap, vm_offset_t va) 385 { 386 pd_entry_t *pde; 387 388 pde = pmap_pde(pmap, va); 389 if (pde == NULL || *pde == NULL) 390 return (NULL); 391 392 return (pmap_pde_to_pte(pde, va)); 393 } 394 395 vm_offset_t 396 pmap_steal_memory(vm_size_t size) 397 { 398 vm_paddr_t bank_size, pa; 399 vm_offset_t va; 400 401 size = round_page(size); 402 bank_size = phys_avail[1] - phys_avail[0]; 403 while (size > bank_size) { 404 int i; 405 406 for (i = 0; phys_avail[i + 2]; i += 2) { 407 phys_avail[i] = phys_avail[i + 2]; 408 phys_avail[i + 1] = phys_avail[i + 3]; 409 } 410 phys_avail[i] = 0; 411 phys_avail[i + 1] = 0; 412 if (!phys_avail[0]) 413 panic("pmap_steal_memory: out of memory"); 414 bank_size = phys_avail[1] - phys_avail[0]; 415 } 416 417 pa = phys_avail[0]; 418 phys_avail[0] += size; 419 if (MIPS_DIRECT_MAPPABLE(pa) == 0) 420 panic("Out of memory below 512Meg?"); 421 va = MIPS_PHYS_TO_DIRECT(pa); 422 bzero((caddr_t)va, size); 423 return (va); 424 } 425 426 /* 427 * Bootstrap the system enough to run with virtual memory. This 428 * assumes that the phys_avail array has been initialized. 429 */ 430 static void 431 pmap_create_kernel_pagetable(void) 432 { 433 int i, j; 434 vm_offset_t ptaddr; 435 pt_entry_t *pte; 436 #ifdef __mips_n64 437 pd_entry_t *pde; 438 vm_offset_t pdaddr; 439 int npt, npde; 440 #endif 441 442 /* 443 * Allocate segment table for the kernel 444 */ 445 kernel_segmap = (pd_entry_t *)pmap_steal_memory(PAGE_SIZE); 446 447 /* 448 * Allocate second level page tables for the kernel 449 */ 450 #ifdef __mips_n64 451 npde = howmany(NKPT, NPDEPG); 452 pdaddr = pmap_steal_memory(PAGE_SIZE * npde); 453 #endif 454 nkpt = NKPT; 455 ptaddr = pmap_steal_memory(PAGE_SIZE * nkpt); 456 457 /* 458 * The R[4-7]?00 stores only one copy of the Global bit in the 459 * translation lookaside buffer for each 2 page entry. Thus invalid 460 * entrys must have the Global bit set so when Entry LO and Entry HI 461 * G bits are anded together they will produce a global bit to store 462 * in the tlb. 463 */ 464 for (i = 0, pte = (pt_entry_t *)ptaddr; i < (nkpt * NPTEPG); i++, pte++) 465 *pte = PTE_G; 466 467 #ifdef __mips_n64 468 for (i = 0, npt = nkpt; npt > 0; i++) { 469 kernel_segmap[i] = (pd_entry_t)(pdaddr + i * PAGE_SIZE); 470 pde = (pd_entry_t *)kernel_segmap[i]; 471 472 for (j = 0; j < NPDEPG && npt > 0; j++, npt--) 473 pde[j] = (pd_entry_t)(ptaddr + (i * NPDEPG + j) * PAGE_SIZE); 474 } 475 #else 476 for (i = 0, j = pmap_seg_index(VM_MIN_KERNEL_ADDRESS); i < nkpt; i++, j++) 477 kernel_segmap[j] = (pd_entry_t)(ptaddr + (i * PAGE_SIZE)); 478 #endif 479 480 PMAP_LOCK_INIT(kernel_pmap); 481 kernel_pmap->pm_segtab = kernel_segmap; 482 CPU_FILL(&kernel_pmap->pm_active); 483 TAILQ_INIT(&kernel_pmap->pm_pvchunk); 484 kernel_pmap->pm_asid[0].asid = PMAP_ASID_RESERVED; 485 kernel_pmap->pm_asid[0].gen = 0; 486 kernel_vm_end += nkpt * NPTEPG * PAGE_SIZE; 487 } 488 489 void 490 pmap_bootstrap(void) 491 { 492 int i; 493 int need_local_mappings = 0; 494 495 /* Sort. */ 496 again: 497 for (i = 0; phys_avail[i + 1] != 0; i += 2) { 498 /* 499 * Keep the memory aligned on page boundary. 500 */ 501 phys_avail[i] = round_page(phys_avail[i]); 502 phys_avail[i + 1] = trunc_page(phys_avail[i + 1]); 503 504 if (i < 2) 505 continue; 506 if (phys_avail[i - 2] > phys_avail[i]) { 507 vm_paddr_t ptemp[2]; 508 509 ptemp[0] = phys_avail[i + 0]; 510 ptemp[1] = phys_avail[i + 1]; 511 512 phys_avail[i + 0] = phys_avail[i - 2]; 513 phys_avail[i + 1] = phys_avail[i - 1]; 514 515 phys_avail[i - 2] = ptemp[0]; 516 phys_avail[i - 1] = ptemp[1]; 517 goto again; 518 } 519 } 520 521 /* 522 * In 32 bit, we may have memory which cannot be mapped directly. 523 * This memory will need temporary mapping before it can be 524 * accessed. 525 */ 526 if (!MIPS_DIRECT_MAPPABLE(phys_avail[i - 1] - 1)) 527 need_local_mappings = 1; 528 529 /* 530 * Copy the phys_avail[] array before we start stealing memory from it. 531 */ 532 for (i = 0; phys_avail[i + 1] != 0; i += 2) { 533 physmem_desc[i] = phys_avail[i]; 534 physmem_desc[i + 1] = phys_avail[i + 1]; 535 } 536 537 Maxmem = atop(phys_avail[i - 1]); 538 539 if (bootverbose) { 540 printf("Physical memory chunk(s):\n"); 541 for (i = 0; phys_avail[i + 1] != 0; i += 2) { 542 vm_paddr_t size; 543 544 size = phys_avail[i + 1] - phys_avail[i]; 545 printf("%#08jx - %#08jx, %ju bytes (%ju pages)\n", 546 (uintmax_t) phys_avail[i], 547 (uintmax_t) phys_avail[i + 1] - 1, 548 (uintmax_t) size, (uintmax_t) size / PAGE_SIZE); 549 } 550 printf("Maxmem is 0x%0jx\n", ptoa((uintmax_t)Maxmem)); 551 } 552 /* 553 * Steal the message buffer from the beginning of memory. 554 */ 555 msgbufp = (struct msgbuf *)pmap_steal_memory(msgbufsize); 556 msgbufinit(msgbufp, msgbufsize); 557 558 /* 559 * Steal thread0 kstack. 560 */ 561 kstack0 = pmap_steal_memory(KSTACK_PAGES << PAGE_SHIFT); 562 563 virtual_avail = VM_MIN_KERNEL_ADDRESS; 564 virtual_end = VM_MAX_KERNEL_ADDRESS; 565 566 #ifdef SMP 567 /* 568 * Steal some virtual address space to map the pcpu area. 569 */ 570 virtual_avail = roundup2(virtual_avail, PAGE_SIZE * 2); 571 pcpup = (struct pcpu *)virtual_avail; 572 virtual_avail += PAGE_SIZE * 2; 573 574 /* 575 * Initialize the wired TLB entry mapping the pcpu region for 576 * the BSP at 'pcpup'. Up until this point we were operating 577 * with the 'pcpup' for the BSP pointing to a virtual address 578 * in KSEG0 so there was no need for a TLB mapping. 579 */ 580 mips_pcpu_tlb_init(PCPU_ADDR(0)); 581 582 if (bootverbose) 583 printf("pcpu is available at virtual address %p.\n", pcpup); 584 #endif 585 586 if (need_local_mappings) 587 pmap_alloc_lmem_map(); 588 pmap_create_kernel_pagetable(); 589 pmap_max_asid = VMNUM_PIDS; 590 mips_wr_entryhi(0); 591 mips_wr_pagemask(0); 592 593 /* 594 * Initialize the global pv list lock. 595 */ 596 rw_init(&pvh_global_lock, "pmap pv global"); 597 } 598 599 /* 600 * Initialize a vm_page's machine-dependent fields. 601 */ 602 void 603 pmap_page_init(vm_page_t m) 604 { 605 606 TAILQ_INIT(&m->md.pv_list); 607 m->md.pv_flags = 0; 608 } 609 610 /* 611 * Initialize the pmap module. 612 * Called by vm_init, to initialize any structures that the pmap 613 * system needs to map virtual memory. 614 */ 615 void 616 pmap_init(void) 617 { 618 } 619 620 /*************************************************** 621 * Low level helper routines..... 622 ***************************************************/ 623 624 #ifdef SMP 625 static __inline void 626 pmap_call_on_active_cpus(pmap_t pmap, void (*fn)(void *), void *arg) 627 { 628 int cpuid, cpu, self; 629 cpuset_t active_cpus; 630 631 sched_pin(); 632 if (is_kernel_pmap(pmap)) { 633 smp_rendezvous(NULL, fn, NULL, arg); 634 goto out; 635 } 636 /* Force ASID update on inactive CPUs */ 637 CPU_FOREACH(cpu) { 638 if (!CPU_ISSET(cpu, &pmap->pm_active)) 639 pmap->pm_asid[cpu].gen = 0; 640 } 641 cpuid = PCPU_GET(cpuid); 642 /* 643 * XXX: barrier/locking for active? 644 * 645 * Take a snapshot of active here, any further changes are ignored. 646 * tlb update/invalidate should be harmless on inactive CPUs 647 */ 648 active_cpus = pmap->pm_active; 649 self = CPU_ISSET(cpuid, &active_cpus); 650 CPU_CLR(cpuid, &active_cpus); 651 /* Optimize for the case where this cpu is the only active one */ 652 if (CPU_EMPTY(&active_cpus)) { 653 if (self) 654 fn(arg); 655 } else { 656 if (self) 657 CPU_SET(cpuid, &active_cpus); 658 smp_rendezvous_cpus(active_cpus, NULL, fn, NULL, arg); 659 } 660 out: 661 sched_unpin(); 662 } 663 #else /* !SMP */ 664 static __inline void 665 pmap_call_on_active_cpus(pmap_t pmap, void (*fn)(void *), void *arg) 666 { 667 int cpuid; 668 669 if (is_kernel_pmap(pmap)) { 670 fn(arg); 671 return; 672 } 673 cpuid = PCPU_GET(cpuid); 674 if (!CPU_ISSET(cpuid, &pmap->pm_active)) 675 pmap->pm_asid[cpuid].gen = 0; 676 else 677 fn(arg); 678 } 679 #endif /* SMP */ 680 681 static void 682 pmap_invalidate_all(pmap_t pmap) 683 { 684 685 pmap_call_on_active_cpus(pmap, 686 (void (*)(void *))tlb_invalidate_all_user, pmap); 687 } 688 689 struct pmap_invalidate_page_arg { 690 pmap_t pmap; 691 vm_offset_t va; 692 }; 693 694 static void 695 pmap_invalidate_page_action(void *arg) 696 { 697 struct pmap_invalidate_page_arg *p = arg; 698 699 tlb_invalidate_address(p->pmap, p->va); 700 } 701 702 static void 703 pmap_invalidate_page(pmap_t pmap, vm_offset_t va) 704 { 705 struct pmap_invalidate_page_arg arg; 706 707 arg.pmap = pmap; 708 arg.va = va; 709 pmap_call_on_active_cpus(pmap, pmap_invalidate_page_action, &arg); 710 } 711 712 struct pmap_invalidate_range_arg { 713 pmap_t pmap; 714 vm_offset_t sva; 715 vm_offset_t eva; 716 }; 717 718 static void 719 pmap_invalidate_range_action(void *arg) 720 { 721 struct pmap_invalidate_range_arg *p = arg; 722 723 tlb_invalidate_range(p->pmap, p->sva, p->eva); 724 } 725 726 static void 727 pmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva) 728 { 729 struct pmap_invalidate_range_arg arg; 730 731 arg.pmap = pmap; 732 arg.sva = sva; 733 arg.eva = eva; 734 pmap_call_on_active_cpus(pmap, pmap_invalidate_range_action, &arg); 735 } 736 737 struct pmap_update_page_arg { 738 pmap_t pmap; 739 vm_offset_t va; 740 pt_entry_t pte; 741 }; 742 743 static void 744 pmap_update_page_action(void *arg) 745 { 746 struct pmap_update_page_arg *p = arg; 747 748 tlb_update(p->pmap, p->va, p->pte); 749 } 750 751 static void 752 pmap_update_page(pmap_t pmap, vm_offset_t va, pt_entry_t pte) 753 { 754 struct pmap_update_page_arg arg; 755 756 arg.pmap = pmap; 757 arg.va = va; 758 arg.pte = pte; 759 pmap_call_on_active_cpus(pmap, pmap_update_page_action, &arg); 760 } 761 762 /* 763 * Routine: pmap_extract 764 * Function: 765 * Extract the physical page address associated 766 * with the given map/virtual_address pair. 767 */ 768 vm_paddr_t 769 pmap_extract(pmap_t pmap, vm_offset_t va) 770 { 771 pt_entry_t *pte; 772 vm_offset_t retval = 0; 773 774 PMAP_LOCK(pmap); 775 pte = pmap_pte(pmap, va); 776 if (pte) { 777 retval = TLBLO_PTE_TO_PA(*pte) | (va & PAGE_MASK); 778 } 779 PMAP_UNLOCK(pmap); 780 return (retval); 781 } 782 783 /* 784 * Routine: pmap_extract_and_hold 785 * Function: 786 * Atomically extract and hold the physical page 787 * with the given pmap and virtual address pair 788 * if that mapping permits the given protection. 789 */ 790 vm_page_t 791 pmap_extract_and_hold(pmap_t pmap, vm_offset_t va, vm_prot_t prot) 792 { 793 pt_entry_t pte, *ptep; 794 vm_paddr_t pa, pte_pa; 795 vm_page_t m; 796 797 m = NULL; 798 pa = 0; 799 PMAP_LOCK(pmap); 800 retry: 801 ptep = pmap_pte(pmap, va); 802 if (ptep != NULL) { 803 pte = *ptep; 804 if (pte_test(&pte, PTE_V) && (!pte_test(&pte, PTE_RO) || 805 (prot & VM_PROT_WRITE) == 0)) { 806 pte_pa = TLBLO_PTE_TO_PA(pte); 807 if (vm_page_pa_tryrelock(pmap, pte_pa, &pa)) 808 goto retry; 809 m = PHYS_TO_VM_PAGE(pte_pa); 810 vm_page_hold(m); 811 } 812 } 813 PA_UNLOCK_COND(pa); 814 PMAP_UNLOCK(pmap); 815 return (m); 816 } 817 818 /*************************************************** 819 * Low level mapping routines..... 820 ***************************************************/ 821 822 /* 823 * add a wired page to the kva 824 */ 825 void 826 pmap_kenter_attr(vm_offset_t va, vm_paddr_t pa, int attr) 827 { 828 pt_entry_t *pte; 829 pt_entry_t opte, npte; 830 831 #ifdef PMAP_DEBUG 832 printf("pmap_kenter: va: %p -> pa: %p\n", (void *)va, (void *)pa); 833 #endif 834 835 pte = pmap_pte(kernel_pmap, va); 836 opte = *pte; 837 npte = TLBLO_PA_TO_PFN(pa) | attr | PTE_D | PTE_V | PTE_G; 838 *pte = npte; 839 if (pte_test(&opte, PTE_V) && opte != npte) 840 pmap_update_page(kernel_pmap, va, npte); 841 } 842 843 void 844 pmap_kenter(vm_offset_t va, vm_paddr_t pa) 845 { 846 847 KASSERT(is_cacheable_mem(pa), 848 ("pmap_kenter: memory at 0x%lx is not cacheable", (u_long)pa)); 849 850 pmap_kenter_attr(va, pa, PTE_C_CACHE); 851 } 852 853 /* 854 * remove a page from the kernel pagetables 855 */ 856 /* PMAP_INLINE */ void 857 pmap_kremove(vm_offset_t va) 858 { 859 pt_entry_t *pte; 860 861 /* 862 * Write back all caches from the page being destroyed 863 */ 864 mips_dcache_wbinv_range_index(va, PAGE_SIZE); 865 866 pte = pmap_pte(kernel_pmap, va); 867 *pte = PTE_G; 868 pmap_invalidate_page(kernel_pmap, va); 869 } 870 871 /* 872 * Used to map a range of physical addresses into kernel 873 * virtual address space. 874 * 875 * The value passed in '*virt' is a suggested virtual address for 876 * the mapping. Architectures which can support a direct-mapped 877 * physical to virtual region can return the appropriate address 878 * within that region, leaving '*virt' unchanged. Other 879 * architectures should map the pages starting at '*virt' and 880 * update '*virt' with the first usable address after the mapped 881 * region. 882 * 883 * Use XKPHYS for 64 bit, and KSEG0 where possible for 32 bit. 884 */ 885 vm_offset_t 886 pmap_map(vm_offset_t *virt, vm_paddr_t start, vm_paddr_t end, int prot) 887 { 888 vm_offset_t va, sva; 889 890 if (MIPS_DIRECT_MAPPABLE(end - 1)) 891 return (MIPS_PHYS_TO_DIRECT(start)); 892 893 va = sva = *virt; 894 while (start < end) { 895 pmap_kenter(va, start); 896 va += PAGE_SIZE; 897 start += PAGE_SIZE; 898 } 899 *virt = va; 900 return (sva); 901 } 902 903 /* 904 * Add a list of wired pages to the kva 905 * this routine is only used for temporary 906 * kernel mappings that do not need to have 907 * page modification or references recorded. 908 * Note that old mappings are simply written 909 * over. The page *must* be wired. 910 */ 911 void 912 pmap_qenter(vm_offset_t va, vm_page_t *m, int count) 913 { 914 int i; 915 vm_offset_t origva = va; 916 917 for (i = 0; i < count; i++) { 918 pmap_flush_pvcache(m[i]); 919 pmap_kenter(va, VM_PAGE_TO_PHYS(m[i])); 920 va += PAGE_SIZE; 921 } 922 923 mips_dcache_wbinv_range_index(origva, PAGE_SIZE*count); 924 } 925 926 /* 927 * this routine jerks page mappings from the 928 * kernel -- it is meant only for temporary mappings. 929 */ 930 void 931 pmap_qremove(vm_offset_t va, int count) 932 { 933 pt_entry_t *pte; 934 vm_offset_t origva; 935 936 if (count < 1) 937 return; 938 mips_dcache_wbinv_range_index(va, PAGE_SIZE * count); 939 origva = va; 940 do { 941 pte = pmap_pte(kernel_pmap, va); 942 *pte = PTE_G; 943 va += PAGE_SIZE; 944 } while (--count > 0); 945 pmap_invalidate_range(kernel_pmap, origva, va); 946 } 947 948 /*************************************************** 949 * Page table page management routines..... 950 ***************************************************/ 951 952 /* 953 * Decrements a page table page's wire count, which is used to record the 954 * number of valid page table entries within the page. If the wire count 955 * drops to zero, then the page table page is unmapped. Returns TRUE if the 956 * page table page was unmapped and FALSE otherwise. 957 */ 958 static PMAP_INLINE boolean_t 959 pmap_unwire_ptp(pmap_t pmap, vm_offset_t va, vm_page_t m) 960 { 961 962 --m->wire_count; 963 if (m->wire_count == 0) { 964 _pmap_unwire_ptp(pmap, va, m); 965 return (TRUE); 966 } else 967 return (FALSE); 968 } 969 970 static void 971 _pmap_unwire_ptp(pmap_t pmap, vm_offset_t va, vm_page_t m) 972 { 973 pd_entry_t *pde; 974 975 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 976 /* 977 * unmap the page table page 978 */ 979 #ifdef __mips_n64 980 if (m->pindex < NUPDE) 981 pde = pmap_pde(pmap, va); 982 else 983 pde = pmap_segmap(pmap, va); 984 #else 985 pde = pmap_pde(pmap, va); 986 #endif 987 *pde = 0; 988 pmap->pm_stats.resident_count--; 989 990 #ifdef __mips_n64 991 if (m->pindex < NUPDE) { 992 pd_entry_t *pdp; 993 vm_page_t pdpg; 994 995 /* 996 * Recursively decrement next level pagetable refcount 997 */ 998 pdp = (pd_entry_t *)*pmap_segmap(pmap, va); 999 pdpg = PHYS_TO_VM_PAGE(MIPS_DIRECT_TO_PHYS(pdp)); 1000 pmap_unwire_ptp(pmap, va, pdpg); 1001 } 1002 #endif 1003 1004 /* 1005 * If the page is finally unwired, simply free it. 1006 */ 1007 vm_page_free_zero(m); 1008 atomic_subtract_int(&vm_cnt.v_wire_count, 1); 1009 } 1010 1011 /* 1012 * After removing a page table entry, this routine is used to 1013 * conditionally free the page, and manage the hold/wire counts. 1014 */ 1015 static int 1016 pmap_unuse_pt(pmap_t pmap, vm_offset_t va, pd_entry_t pde) 1017 { 1018 vm_page_t mpte; 1019 1020 if (va >= VM_MAXUSER_ADDRESS) 1021 return (0); 1022 KASSERT(pde != 0, ("pmap_unuse_pt: pde != 0")); 1023 mpte = PHYS_TO_VM_PAGE(MIPS_DIRECT_TO_PHYS(pde)); 1024 return (pmap_unwire_ptp(pmap, va, mpte)); 1025 } 1026 1027 void 1028 pmap_pinit0(pmap_t pmap) 1029 { 1030 int i; 1031 1032 PMAP_LOCK_INIT(pmap); 1033 pmap->pm_segtab = kernel_segmap; 1034 CPU_ZERO(&pmap->pm_active); 1035 for (i = 0; i < MAXCPU; i++) { 1036 pmap->pm_asid[i].asid = PMAP_ASID_RESERVED; 1037 pmap->pm_asid[i].gen = 0; 1038 } 1039 PCPU_SET(curpmap, pmap); 1040 TAILQ_INIT(&pmap->pm_pvchunk); 1041 bzero(&pmap->pm_stats, sizeof pmap->pm_stats); 1042 } 1043 1044 static void 1045 pmap_grow_direct_page(int req) 1046 { 1047 1048 #ifdef __mips_n64 1049 VM_WAIT; 1050 #else 1051 if (!vm_page_reclaim_contig(req, 1, 0, MIPS_KSEG0_LARGEST_PHYS, 1052 PAGE_SIZE, 0)) 1053 VM_WAIT; 1054 #endif 1055 } 1056 1057 static vm_page_t 1058 pmap_alloc_direct_page(unsigned int index, int req) 1059 { 1060 vm_page_t m; 1061 1062 m = vm_page_alloc_freelist(VM_FREELIST_DIRECT, req | VM_ALLOC_WIRED | 1063 VM_ALLOC_ZERO); 1064 if (m == NULL) 1065 return (NULL); 1066 1067 if ((m->flags & PG_ZERO) == 0) 1068 pmap_zero_page(m); 1069 1070 m->pindex = index; 1071 return (m); 1072 } 1073 1074 /* 1075 * Initialize a preallocated and zeroed pmap structure, 1076 * such as one in a vmspace structure. 1077 */ 1078 int 1079 pmap_pinit(pmap_t pmap) 1080 { 1081 vm_offset_t ptdva; 1082 vm_page_t ptdpg; 1083 int i, req_class; 1084 1085 /* 1086 * allocate the page directory page 1087 */ 1088 req_class = VM_ALLOC_NORMAL; 1089 while ((ptdpg = pmap_alloc_direct_page(NUSERPGTBLS, req_class)) == 1090 NULL) 1091 pmap_grow_direct_page(req_class); 1092 1093 ptdva = MIPS_PHYS_TO_DIRECT(VM_PAGE_TO_PHYS(ptdpg)); 1094 pmap->pm_segtab = (pd_entry_t *)ptdva; 1095 CPU_ZERO(&pmap->pm_active); 1096 for (i = 0; i < MAXCPU; i++) { 1097 pmap->pm_asid[i].asid = PMAP_ASID_RESERVED; 1098 pmap->pm_asid[i].gen = 0; 1099 } 1100 TAILQ_INIT(&pmap->pm_pvchunk); 1101 bzero(&pmap->pm_stats, sizeof pmap->pm_stats); 1102 1103 return (1); 1104 } 1105 1106 /* 1107 * this routine is called if the page table page is not 1108 * mapped correctly. 1109 */ 1110 static vm_page_t 1111 _pmap_allocpte(pmap_t pmap, unsigned ptepindex, u_int flags) 1112 { 1113 vm_offset_t pageva; 1114 vm_page_t m; 1115 int req_class; 1116 1117 /* 1118 * Find or fabricate a new pagetable page 1119 */ 1120 req_class = VM_ALLOC_NORMAL; 1121 if ((m = pmap_alloc_direct_page(ptepindex, req_class)) == NULL) { 1122 if ((flags & PMAP_ENTER_NOSLEEP) == 0) { 1123 PMAP_UNLOCK(pmap); 1124 rw_wunlock(&pvh_global_lock); 1125 pmap_grow_direct_page(req_class); 1126 rw_wlock(&pvh_global_lock); 1127 PMAP_LOCK(pmap); 1128 } 1129 1130 /* 1131 * Indicate the need to retry. While waiting, the page 1132 * table page may have been allocated. 1133 */ 1134 return (NULL); 1135 } 1136 1137 /* 1138 * Map the pagetable page into the process address space, if it 1139 * isn't already there. 1140 */ 1141 pageva = MIPS_PHYS_TO_DIRECT(VM_PAGE_TO_PHYS(m)); 1142 1143 #ifdef __mips_n64 1144 if (ptepindex >= NUPDE) { 1145 pmap->pm_segtab[ptepindex - NUPDE] = (pd_entry_t)pageva; 1146 } else { 1147 pd_entry_t *pdep, *pde; 1148 int segindex = ptepindex >> (SEGSHIFT - PDRSHIFT); 1149 int pdeindex = ptepindex & (NPDEPG - 1); 1150 vm_page_t pg; 1151 1152 pdep = &pmap->pm_segtab[segindex]; 1153 if (*pdep == NULL) { 1154 /* recurse for allocating page dir */ 1155 if (_pmap_allocpte(pmap, NUPDE + segindex, 1156 flags) == NULL) { 1157 /* alloc failed, release current */ 1158 --m->wire_count; 1159 atomic_subtract_int(&vm_cnt.v_wire_count, 1); 1160 vm_page_free_zero(m); 1161 return (NULL); 1162 } 1163 } else { 1164 pg = PHYS_TO_VM_PAGE(MIPS_DIRECT_TO_PHYS(*pdep)); 1165 pg->wire_count++; 1166 } 1167 /* Next level entry */ 1168 pde = (pd_entry_t *)*pdep; 1169 pde[pdeindex] = (pd_entry_t)pageva; 1170 } 1171 #else 1172 pmap->pm_segtab[ptepindex] = (pd_entry_t)pageva; 1173 #endif 1174 pmap->pm_stats.resident_count++; 1175 return (m); 1176 } 1177 1178 static vm_page_t 1179 pmap_allocpte(pmap_t pmap, vm_offset_t va, u_int flags) 1180 { 1181 unsigned ptepindex; 1182 pd_entry_t *pde; 1183 vm_page_t m; 1184 1185 /* 1186 * Calculate pagetable page index 1187 */ 1188 ptepindex = pmap_pde_pindex(va); 1189 retry: 1190 /* 1191 * Get the page directory entry 1192 */ 1193 pde = pmap_pde(pmap, va); 1194 1195 /* 1196 * If the page table page is mapped, we just increment the hold 1197 * count, and activate it. 1198 */ 1199 if (pde != NULL && *pde != NULL) { 1200 m = PHYS_TO_VM_PAGE(MIPS_DIRECT_TO_PHYS(*pde)); 1201 m->wire_count++; 1202 } else { 1203 /* 1204 * Here if the pte page isn't mapped, or if it has been 1205 * deallocated. 1206 */ 1207 m = _pmap_allocpte(pmap, ptepindex, flags); 1208 if (m == NULL && (flags & PMAP_ENTER_NOSLEEP) == 0) 1209 goto retry; 1210 } 1211 return (m); 1212 } 1213 1214 1215 /*************************************************** 1216 * Pmap allocation/deallocation routines. 1217 ***************************************************/ 1218 1219 /* 1220 * Release any resources held by the given physical map. 1221 * Called when a pmap initialized by pmap_pinit is being released. 1222 * Should only be called if the map contains no valid mappings. 1223 */ 1224 void 1225 pmap_release(pmap_t pmap) 1226 { 1227 vm_offset_t ptdva; 1228 vm_page_t ptdpg; 1229 1230 KASSERT(pmap->pm_stats.resident_count == 0, 1231 ("pmap_release: pmap resident count %ld != 0", 1232 pmap->pm_stats.resident_count)); 1233 1234 ptdva = (vm_offset_t)pmap->pm_segtab; 1235 ptdpg = PHYS_TO_VM_PAGE(MIPS_DIRECT_TO_PHYS(ptdva)); 1236 1237 ptdpg->wire_count--; 1238 atomic_subtract_int(&vm_cnt.v_wire_count, 1); 1239 vm_page_free_zero(ptdpg); 1240 } 1241 1242 /* 1243 * grow the number of kernel page table entries, if needed 1244 */ 1245 void 1246 pmap_growkernel(vm_offset_t addr) 1247 { 1248 vm_page_t nkpg; 1249 pd_entry_t *pde, *pdpe; 1250 pt_entry_t *pte; 1251 int i, req_class; 1252 1253 mtx_assert(&kernel_map->system_mtx, MA_OWNED); 1254 req_class = VM_ALLOC_INTERRUPT; 1255 addr = roundup2(addr, NBSEG); 1256 if (addr - 1 >= kernel_map->max_offset) 1257 addr = kernel_map->max_offset; 1258 while (kernel_vm_end < addr) { 1259 pdpe = pmap_segmap(kernel_pmap, kernel_vm_end); 1260 #ifdef __mips_n64 1261 if (*pdpe == 0) { 1262 /* new intermediate page table entry */ 1263 nkpg = pmap_alloc_direct_page(nkpt, req_class); 1264 if (nkpg == NULL) 1265 panic("pmap_growkernel: no memory to grow kernel"); 1266 *pdpe = (pd_entry_t)MIPS_PHYS_TO_DIRECT(VM_PAGE_TO_PHYS(nkpg)); 1267 continue; /* try again */ 1268 } 1269 #endif 1270 pde = pmap_pdpe_to_pde(pdpe, kernel_vm_end); 1271 if (*pde != 0) { 1272 kernel_vm_end = (kernel_vm_end + NBPDR) & ~PDRMASK; 1273 if (kernel_vm_end - 1 >= kernel_map->max_offset) { 1274 kernel_vm_end = kernel_map->max_offset; 1275 break; 1276 } 1277 continue; 1278 } 1279 1280 /* 1281 * This index is bogus, but out of the way 1282 */ 1283 nkpg = pmap_alloc_direct_page(nkpt, req_class); 1284 #ifndef __mips_n64 1285 if (nkpg == NULL && vm_page_reclaim_contig(req_class, 1, 1286 0, MIPS_KSEG0_LARGEST_PHYS, PAGE_SIZE, 0)) 1287 nkpg = pmap_alloc_direct_page(nkpt, req_class); 1288 #endif 1289 if (nkpg == NULL) 1290 panic("pmap_growkernel: no memory to grow kernel"); 1291 nkpt++; 1292 *pde = (pd_entry_t)MIPS_PHYS_TO_DIRECT(VM_PAGE_TO_PHYS(nkpg)); 1293 1294 /* 1295 * The R[4-7]?00 stores only one copy of the Global bit in 1296 * the translation lookaside buffer for each 2 page entry. 1297 * Thus invalid entrys must have the Global bit set so when 1298 * Entry LO and Entry HI G bits are anded together they will 1299 * produce a global bit to store in the tlb. 1300 */ 1301 pte = (pt_entry_t *)*pde; 1302 for (i = 0; i < NPTEPG; i++) 1303 pte[i] = PTE_G; 1304 1305 kernel_vm_end = (kernel_vm_end + NBPDR) & ~PDRMASK; 1306 if (kernel_vm_end - 1 >= kernel_map->max_offset) { 1307 kernel_vm_end = kernel_map->max_offset; 1308 break; 1309 } 1310 } 1311 } 1312 1313 /*************************************************** 1314 * page management routines. 1315 ***************************************************/ 1316 1317 CTASSERT(sizeof(struct pv_chunk) == PAGE_SIZE); 1318 #ifdef __mips_n64 1319 CTASSERT(_NPCM == 3); 1320 CTASSERT(_NPCPV == 168); 1321 #else 1322 CTASSERT(_NPCM == 11); 1323 CTASSERT(_NPCPV == 336); 1324 #endif 1325 1326 static __inline struct pv_chunk * 1327 pv_to_chunk(pv_entry_t pv) 1328 { 1329 1330 return ((struct pv_chunk *)((uintptr_t)pv & ~(uintptr_t)PAGE_MASK)); 1331 } 1332 1333 #define PV_PMAP(pv) (pv_to_chunk(pv)->pc_pmap) 1334 1335 #ifdef __mips_n64 1336 #define PC_FREE0_1 0xfffffffffffffffful 1337 #define PC_FREE2 0x000000fffffffffful 1338 #else 1339 #define PC_FREE0_9 0xfffffffful /* Free values for index 0 through 9 */ 1340 #define PC_FREE10 0x0000fffful /* Free values for index 10 */ 1341 #endif 1342 1343 static const u_long pc_freemask[_NPCM] = { 1344 #ifdef __mips_n64 1345 PC_FREE0_1, PC_FREE0_1, PC_FREE2 1346 #else 1347 PC_FREE0_9, PC_FREE0_9, PC_FREE0_9, 1348 PC_FREE0_9, PC_FREE0_9, PC_FREE0_9, 1349 PC_FREE0_9, PC_FREE0_9, PC_FREE0_9, 1350 PC_FREE0_9, PC_FREE10 1351 #endif 1352 }; 1353 1354 static SYSCTL_NODE(_vm, OID_AUTO, pmap, CTLFLAG_RD, 0, "VM/pmap parameters"); 1355 1356 SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_count, CTLFLAG_RD, &pv_entry_count, 0, 1357 "Current number of pv entries"); 1358 1359 #ifdef PV_STATS 1360 static int pc_chunk_count, pc_chunk_allocs, pc_chunk_frees, pc_chunk_tryfail; 1361 1362 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_count, CTLFLAG_RD, &pc_chunk_count, 0, 1363 "Current number of pv entry chunks"); 1364 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_allocs, CTLFLAG_RD, &pc_chunk_allocs, 0, 1365 "Current number of pv entry chunks allocated"); 1366 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_frees, CTLFLAG_RD, &pc_chunk_frees, 0, 1367 "Current number of pv entry chunks frees"); 1368 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_tryfail, CTLFLAG_RD, &pc_chunk_tryfail, 0, 1369 "Number of times tried to get a chunk page but failed."); 1370 1371 static long pv_entry_frees, pv_entry_allocs; 1372 static int pv_entry_spare; 1373 1374 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_frees, CTLFLAG_RD, &pv_entry_frees, 0, 1375 "Current number of pv entry frees"); 1376 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_allocs, CTLFLAG_RD, &pv_entry_allocs, 0, 1377 "Current number of pv entry allocs"); 1378 SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_spare, CTLFLAG_RD, &pv_entry_spare, 0, 1379 "Current number of spare pv entries"); 1380 #endif 1381 1382 /* 1383 * We are in a serious low memory condition. Resort to 1384 * drastic measures to free some pages so we can allocate 1385 * another pv entry chunk. 1386 */ 1387 static vm_page_t 1388 pmap_pv_reclaim(pmap_t locked_pmap) 1389 { 1390 struct pch newtail; 1391 struct pv_chunk *pc; 1392 pd_entry_t *pde; 1393 pmap_t pmap; 1394 pt_entry_t *pte, oldpte; 1395 pv_entry_t pv; 1396 vm_offset_t va; 1397 vm_page_t m, m_pc; 1398 u_long inuse; 1399 int bit, field, freed, idx; 1400 1401 PMAP_LOCK_ASSERT(locked_pmap, MA_OWNED); 1402 pmap = NULL; 1403 m_pc = NULL; 1404 TAILQ_INIT(&newtail); 1405 while ((pc = TAILQ_FIRST(&pv_chunks)) != NULL) { 1406 TAILQ_REMOVE(&pv_chunks, pc, pc_lru); 1407 if (pmap != pc->pc_pmap) { 1408 if (pmap != NULL) { 1409 pmap_invalidate_all(pmap); 1410 if (pmap != locked_pmap) 1411 PMAP_UNLOCK(pmap); 1412 } 1413 pmap = pc->pc_pmap; 1414 /* Avoid deadlock and lock recursion. */ 1415 if (pmap > locked_pmap) 1416 PMAP_LOCK(pmap); 1417 else if (pmap != locked_pmap && !PMAP_TRYLOCK(pmap)) { 1418 pmap = NULL; 1419 TAILQ_INSERT_TAIL(&newtail, pc, pc_lru); 1420 continue; 1421 } 1422 } 1423 1424 /* 1425 * Destroy every non-wired, 4 KB page mapping in the chunk. 1426 */ 1427 freed = 0; 1428 for (field = 0; field < _NPCM; field++) { 1429 for (inuse = ~pc->pc_map[field] & pc_freemask[field]; 1430 inuse != 0; inuse &= ~(1UL << bit)) { 1431 bit = ffsl(inuse) - 1; 1432 idx = field * sizeof(inuse) * NBBY + bit; 1433 pv = &pc->pc_pventry[idx]; 1434 va = pv->pv_va; 1435 pde = pmap_pde(pmap, va); 1436 KASSERT(pde != NULL && *pde != 0, 1437 ("pmap_pv_reclaim: pde")); 1438 pte = pmap_pde_to_pte(pde, va); 1439 oldpte = *pte; 1440 if (pte_test(&oldpte, PTE_W)) 1441 continue; 1442 if (is_kernel_pmap(pmap)) 1443 *pte = PTE_G; 1444 else 1445 *pte = 0; 1446 m = PHYS_TO_VM_PAGE(TLBLO_PTE_TO_PA(oldpte)); 1447 if (pte_test(&oldpte, PTE_D)) 1448 vm_page_dirty(m); 1449 if (m->md.pv_flags & PV_TABLE_REF) 1450 vm_page_aflag_set(m, PGA_REFERENCED); 1451 m->md.pv_flags &= ~PV_TABLE_REF; 1452 TAILQ_REMOVE(&m->md.pv_list, pv, pv_list); 1453 if (TAILQ_EMPTY(&m->md.pv_list)) 1454 vm_page_aflag_clear(m, PGA_WRITEABLE); 1455 pc->pc_map[field] |= 1UL << bit; 1456 pmap_unuse_pt(pmap, va, *pde); 1457 freed++; 1458 } 1459 } 1460 if (freed == 0) { 1461 TAILQ_INSERT_TAIL(&newtail, pc, pc_lru); 1462 continue; 1463 } 1464 /* Every freed mapping is for a 4 KB page. */ 1465 pmap->pm_stats.resident_count -= freed; 1466 PV_STAT(pv_entry_frees += freed); 1467 PV_STAT(pv_entry_spare += freed); 1468 pv_entry_count -= freed; 1469 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list); 1470 for (field = 0; field < _NPCM; field++) 1471 if (pc->pc_map[field] != pc_freemask[field]) { 1472 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, 1473 pc_list); 1474 TAILQ_INSERT_TAIL(&newtail, pc, pc_lru); 1475 1476 /* 1477 * One freed pv entry in locked_pmap is 1478 * sufficient. 1479 */ 1480 if (pmap == locked_pmap) 1481 goto out; 1482 break; 1483 } 1484 if (field == _NPCM) { 1485 PV_STAT(pv_entry_spare -= _NPCPV); 1486 PV_STAT(pc_chunk_count--); 1487 PV_STAT(pc_chunk_frees++); 1488 /* Entire chunk is free; return it. */ 1489 m_pc = PHYS_TO_VM_PAGE(MIPS_DIRECT_TO_PHYS( 1490 (vm_offset_t)pc)); 1491 break; 1492 } 1493 } 1494 out: 1495 TAILQ_CONCAT(&pv_chunks, &newtail, pc_lru); 1496 if (pmap != NULL) { 1497 pmap_invalidate_all(pmap); 1498 if (pmap != locked_pmap) 1499 PMAP_UNLOCK(pmap); 1500 } 1501 return (m_pc); 1502 } 1503 1504 /* 1505 * free the pv_entry back to the free list 1506 */ 1507 static void 1508 free_pv_entry(pmap_t pmap, pv_entry_t pv) 1509 { 1510 struct pv_chunk *pc; 1511 int bit, field, idx; 1512 1513 rw_assert(&pvh_global_lock, RA_WLOCKED); 1514 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 1515 PV_STAT(pv_entry_frees++); 1516 PV_STAT(pv_entry_spare++); 1517 pv_entry_count--; 1518 pc = pv_to_chunk(pv); 1519 idx = pv - &pc->pc_pventry[0]; 1520 field = idx / (sizeof(u_long) * NBBY); 1521 bit = idx % (sizeof(u_long) * NBBY); 1522 pc->pc_map[field] |= 1ul << bit; 1523 for (idx = 0; idx < _NPCM; idx++) 1524 if (pc->pc_map[idx] != pc_freemask[idx]) { 1525 /* 1526 * 98% of the time, pc is already at the head of the 1527 * list. If it isn't already, move it to the head. 1528 */ 1529 if (__predict_false(TAILQ_FIRST(&pmap->pm_pvchunk) != 1530 pc)) { 1531 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list); 1532 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, 1533 pc_list); 1534 } 1535 return; 1536 } 1537 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list); 1538 free_pv_chunk(pc); 1539 } 1540 1541 static void 1542 free_pv_chunk(struct pv_chunk *pc) 1543 { 1544 vm_page_t m; 1545 1546 TAILQ_REMOVE(&pv_chunks, pc, pc_lru); 1547 PV_STAT(pv_entry_spare -= _NPCPV); 1548 PV_STAT(pc_chunk_count--); 1549 PV_STAT(pc_chunk_frees++); 1550 /* entire chunk is free, return it */ 1551 m = PHYS_TO_VM_PAGE(MIPS_DIRECT_TO_PHYS((vm_offset_t)pc)); 1552 vm_page_unwire(m, PQ_NONE); 1553 vm_page_free(m); 1554 } 1555 1556 /* 1557 * get a new pv_entry, allocating a block from the system 1558 * when needed. 1559 */ 1560 static pv_entry_t 1561 get_pv_entry(pmap_t pmap, boolean_t try) 1562 { 1563 struct pv_chunk *pc; 1564 pv_entry_t pv; 1565 vm_page_t m; 1566 int bit, field, idx; 1567 1568 rw_assert(&pvh_global_lock, RA_WLOCKED); 1569 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 1570 PV_STAT(pv_entry_allocs++); 1571 pv_entry_count++; 1572 retry: 1573 pc = TAILQ_FIRST(&pmap->pm_pvchunk); 1574 if (pc != NULL) { 1575 for (field = 0; field < _NPCM; field++) { 1576 if (pc->pc_map[field]) { 1577 bit = ffsl(pc->pc_map[field]) - 1; 1578 break; 1579 } 1580 } 1581 if (field < _NPCM) { 1582 idx = field * sizeof(pc->pc_map[field]) * NBBY + bit; 1583 pv = &pc->pc_pventry[idx]; 1584 pc->pc_map[field] &= ~(1ul << bit); 1585 /* If this was the last item, move it to tail */ 1586 for (field = 0; field < _NPCM; field++) 1587 if (pc->pc_map[field] != 0) { 1588 PV_STAT(pv_entry_spare--); 1589 return (pv); /* not full, return */ 1590 } 1591 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list); 1592 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc, pc_list); 1593 PV_STAT(pv_entry_spare--); 1594 return (pv); 1595 } 1596 } 1597 /* No free items, allocate another chunk */ 1598 m = vm_page_alloc_freelist(VM_FREELIST_DIRECT, VM_ALLOC_NORMAL | 1599 VM_ALLOC_WIRED); 1600 if (m == NULL) { 1601 if (try) { 1602 pv_entry_count--; 1603 PV_STAT(pc_chunk_tryfail++); 1604 return (NULL); 1605 } 1606 m = pmap_pv_reclaim(pmap); 1607 if (m == NULL) 1608 goto retry; 1609 } 1610 PV_STAT(pc_chunk_count++); 1611 PV_STAT(pc_chunk_allocs++); 1612 pc = (struct pv_chunk *)MIPS_PHYS_TO_DIRECT(VM_PAGE_TO_PHYS(m)); 1613 pc->pc_pmap = pmap; 1614 pc->pc_map[0] = pc_freemask[0] & ~1ul; /* preallocated bit 0 */ 1615 for (field = 1; field < _NPCM; field++) 1616 pc->pc_map[field] = pc_freemask[field]; 1617 TAILQ_INSERT_TAIL(&pv_chunks, pc, pc_lru); 1618 pv = &pc->pc_pventry[0]; 1619 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list); 1620 PV_STAT(pv_entry_spare += _NPCPV - 1); 1621 return (pv); 1622 } 1623 1624 static pv_entry_t 1625 pmap_pvh_remove(struct md_page *pvh, pmap_t pmap, vm_offset_t va) 1626 { 1627 pv_entry_t pv; 1628 1629 rw_assert(&pvh_global_lock, RA_WLOCKED); 1630 TAILQ_FOREACH(pv, &pvh->pv_list, pv_list) { 1631 if (pmap == PV_PMAP(pv) && va == pv->pv_va) { 1632 TAILQ_REMOVE(&pvh->pv_list, pv, pv_list); 1633 break; 1634 } 1635 } 1636 return (pv); 1637 } 1638 1639 static void 1640 pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va) 1641 { 1642 pv_entry_t pv; 1643 1644 pv = pmap_pvh_remove(pvh, pmap, va); 1645 KASSERT(pv != NULL, ("pmap_pvh_free: pv not found, pa %lx va %lx", 1646 (u_long)VM_PAGE_TO_PHYS(__containerof(pvh, struct vm_page, md)), 1647 (u_long)va)); 1648 free_pv_entry(pmap, pv); 1649 } 1650 1651 static void 1652 pmap_remove_entry(pmap_t pmap, vm_page_t m, vm_offset_t va) 1653 { 1654 1655 rw_assert(&pvh_global_lock, RA_WLOCKED); 1656 pmap_pvh_free(&m->md, pmap, va); 1657 if (TAILQ_EMPTY(&m->md.pv_list)) 1658 vm_page_aflag_clear(m, PGA_WRITEABLE); 1659 } 1660 1661 /* 1662 * Conditionally create a pv entry. 1663 */ 1664 static boolean_t 1665 pmap_try_insert_pv_entry(pmap_t pmap, vm_page_t mpte, vm_offset_t va, 1666 vm_page_t m) 1667 { 1668 pv_entry_t pv; 1669 1670 rw_assert(&pvh_global_lock, RA_WLOCKED); 1671 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 1672 if ((pv = get_pv_entry(pmap, TRUE)) != NULL) { 1673 pv->pv_va = va; 1674 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_list); 1675 return (TRUE); 1676 } else 1677 return (FALSE); 1678 } 1679 1680 /* 1681 * pmap_remove_pte: do the things to unmap a page in a process 1682 */ 1683 static int 1684 pmap_remove_pte(struct pmap *pmap, pt_entry_t *ptq, vm_offset_t va, 1685 pd_entry_t pde) 1686 { 1687 pt_entry_t oldpte; 1688 vm_page_t m; 1689 vm_paddr_t pa; 1690 1691 rw_assert(&pvh_global_lock, RA_WLOCKED); 1692 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 1693 1694 /* 1695 * Write back all cache lines from the page being unmapped. 1696 */ 1697 mips_dcache_wbinv_range_index(va, PAGE_SIZE); 1698 1699 oldpte = *ptq; 1700 if (is_kernel_pmap(pmap)) 1701 *ptq = PTE_G; 1702 else 1703 *ptq = 0; 1704 1705 if (pte_test(&oldpte, PTE_W)) 1706 pmap->pm_stats.wired_count -= 1; 1707 1708 pmap->pm_stats.resident_count -= 1; 1709 1710 if (pte_test(&oldpte, PTE_MANAGED)) { 1711 pa = TLBLO_PTE_TO_PA(oldpte); 1712 m = PHYS_TO_VM_PAGE(pa); 1713 if (pte_test(&oldpte, PTE_D)) { 1714 KASSERT(!pte_test(&oldpte, PTE_RO), 1715 ("%s: modified page not writable: va: %p, pte: %#jx", 1716 __func__, (void *)va, (uintmax_t)oldpte)); 1717 vm_page_dirty(m); 1718 } 1719 if (m->md.pv_flags & PV_TABLE_REF) 1720 vm_page_aflag_set(m, PGA_REFERENCED); 1721 m->md.pv_flags &= ~PV_TABLE_REF; 1722 1723 pmap_remove_entry(pmap, m, va); 1724 } 1725 return (pmap_unuse_pt(pmap, va, pde)); 1726 } 1727 1728 /* 1729 * Remove a single page from a process address space 1730 */ 1731 static void 1732 pmap_remove_page(struct pmap *pmap, vm_offset_t va) 1733 { 1734 pd_entry_t *pde; 1735 pt_entry_t *ptq; 1736 1737 rw_assert(&pvh_global_lock, RA_WLOCKED); 1738 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 1739 pde = pmap_pde(pmap, va); 1740 if (pde == NULL || *pde == 0) 1741 return; 1742 ptq = pmap_pde_to_pte(pde, va); 1743 1744 /* 1745 * If there is no pte for this address, just skip it! 1746 */ 1747 if (!pte_test(ptq, PTE_V)) 1748 return; 1749 1750 (void)pmap_remove_pte(pmap, ptq, va, *pde); 1751 pmap_invalidate_page(pmap, va); 1752 } 1753 1754 /* 1755 * Remove the given range of addresses from the specified map. 1756 * 1757 * It is assumed that the start and end are properly 1758 * rounded to the page size. 1759 */ 1760 void 1761 pmap_remove(pmap_t pmap, vm_offset_t sva, vm_offset_t eva) 1762 { 1763 pd_entry_t *pde, *pdpe; 1764 pt_entry_t *pte; 1765 vm_offset_t va, va_next; 1766 1767 /* 1768 * Perform an unsynchronized read. This is, however, safe. 1769 */ 1770 if (pmap->pm_stats.resident_count == 0) 1771 return; 1772 1773 rw_wlock(&pvh_global_lock); 1774 PMAP_LOCK(pmap); 1775 1776 /* 1777 * special handling of removing one page. a very common operation 1778 * and easy to short circuit some code. 1779 */ 1780 if ((sva + PAGE_SIZE) == eva) { 1781 pmap_remove_page(pmap, sva); 1782 goto out; 1783 } 1784 for (; sva < eva; sva = va_next) { 1785 pdpe = pmap_segmap(pmap, sva); 1786 #ifdef __mips_n64 1787 if (*pdpe == 0) { 1788 va_next = (sva + NBSEG) & ~SEGMASK; 1789 if (va_next < sva) 1790 va_next = eva; 1791 continue; 1792 } 1793 #endif 1794 va_next = (sva + NBPDR) & ~PDRMASK; 1795 if (va_next < sva) 1796 va_next = eva; 1797 1798 pde = pmap_pdpe_to_pde(pdpe, sva); 1799 if (*pde == NULL) 1800 continue; 1801 1802 /* 1803 * Limit our scan to either the end of the va represented 1804 * by the current page table page, or to the end of the 1805 * range being removed. 1806 */ 1807 if (va_next > eva) 1808 va_next = eva; 1809 1810 va = va_next; 1811 for (pte = pmap_pde_to_pte(pde, sva); sva != va_next; pte++, 1812 sva += PAGE_SIZE) { 1813 if (!pte_test(pte, PTE_V)) { 1814 if (va != va_next) { 1815 pmap_invalidate_range(pmap, va, sva); 1816 va = va_next; 1817 } 1818 continue; 1819 } 1820 if (va == va_next) 1821 va = sva; 1822 if (pmap_remove_pte(pmap, pte, sva, *pde)) { 1823 sva += PAGE_SIZE; 1824 break; 1825 } 1826 } 1827 if (va != va_next) 1828 pmap_invalidate_range(pmap, va, sva); 1829 } 1830 out: 1831 rw_wunlock(&pvh_global_lock); 1832 PMAP_UNLOCK(pmap); 1833 } 1834 1835 /* 1836 * Routine: pmap_remove_all 1837 * Function: 1838 * Removes this physical page from 1839 * all physical maps in which it resides. 1840 * Reflects back modify bits to the pager. 1841 * 1842 * Notes: 1843 * Original versions of this routine were very 1844 * inefficient because they iteratively called 1845 * pmap_remove (slow...) 1846 */ 1847 1848 void 1849 pmap_remove_all(vm_page_t m) 1850 { 1851 pv_entry_t pv; 1852 pmap_t pmap; 1853 pd_entry_t *pde; 1854 pt_entry_t *pte, tpte; 1855 1856 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1857 ("pmap_remove_all: page %p is not managed", m)); 1858 rw_wlock(&pvh_global_lock); 1859 1860 if (m->md.pv_flags & PV_TABLE_REF) 1861 vm_page_aflag_set(m, PGA_REFERENCED); 1862 1863 while ((pv = TAILQ_FIRST(&m->md.pv_list)) != NULL) { 1864 pmap = PV_PMAP(pv); 1865 PMAP_LOCK(pmap); 1866 1867 /* 1868 * If it's last mapping writeback all caches from 1869 * the page being destroyed 1870 */ 1871 if (TAILQ_NEXT(pv, pv_list) == NULL) 1872 mips_dcache_wbinv_range_index(pv->pv_va, PAGE_SIZE); 1873 1874 pmap->pm_stats.resident_count--; 1875 1876 pde = pmap_pde(pmap, pv->pv_va); 1877 KASSERT(pde != NULL && *pde != 0, ("pmap_remove_all: pde")); 1878 pte = pmap_pde_to_pte(pde, pv->pv_va); 1879 1880 tpte = *pte; 1881 if (is_kernel_pmap(pmap)) 1882 *pte = PTE_G; 1883 else 1884 *pte = 0; 1885 1886 if (pte_test(&tpte, PTE_W)) 1887 pmap->pm_stats.wired_count--; 1888 1889 /* 1890 * Update the vm_page_t clean and reference bits. 1891 */ 1892 if (pte_test(&tpte, PTE_D)) { 1893 KASSERT(!pte_test(&tpte, PTE_RO), 1894 ("%s: modified page not writable: va: %p, pte: %#jx", 1895 __func__, (void *)pv->pv_va, (uintmax_t)tpte)); 1896 vm_page_dirty(m); 1897 } 1898 pmap_invalidate_page(pmap, pv->pv_va); 1899 1900 TAILQ_REMOVE(&m->md.pv_list, pv, pv_list); 1901 pmap_unuse_pt(pmap, pv->pv_va, *pde); 1902 free_pv_entry(pmap, pv); 1903 PMAP_UNLOCK(pmap); 1904 } 1905 1906 vm_page_aflag_clear(m, PGA_WRITEABLE); 1907 m->md.pv_flags &= ~PV_TABLE_REF; 1908 rw_wunlock(&pvh_global_lock); 1909 } 1910 1911 /* 1912 * Set the physical protection on the 1913 * specified range of this map as requested. 1914 */ 1915 void 1916 pmap_protect(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, vm_prot_t prot) 1917 { 1918 pt_entry_t pbits, *pte; 1919 pd_entry_t *pde, *pdpe; 1920 vm_offset_t va, va_next; 1921 vm_paddr_t pa; 1922 vm_page_t m; 1923 1924 if ((prot & VM_PROT_READ) == VM_PROT_NONE) { 1925 pmap_remove(pmap, sva, eva); 1926 return; 1927 } 1928 if (prot & VM_PROT_WRITE) 1929 return; 1930 1931 PMAP_LOCK(pmap); 1932 for (; sva < eva; sva = va_next) { 1933 pdpe = pmap_segmap(pmap, sva); 1934 #ifdef __mips_n64 1935 if (*pdpe == 0) { 1936 va_next = (sva + NBSEG) & ~SEGMASK; 1937 if (va_next < sva) 1938 va_next = eva; 1939 continue; 1940 } 1941 #endif 1942 va_next = (sva + NBPDR) & ~PDRMASK; 1943 if (va_next < sva) 1944 va_next = eva; 1945 1946 pde = pmap_pdpe_to_pde(pdpe, sva); 1947 if (*pde == NULL) 1948 continue; 1949 1950 /* 1951 * Limit our scan to either the end of the va represented 1952 * by the current page table page, or to the end of the 1953 * range being write protected. 1954 */ 1955 if (va_next > eva) 1956 va_next = eva; 1957 1958 va = va_next; 1959 for (pte = pmap_pde_to_pte(pde, sva); sva != va_next; pte++, 1960 sva += PAGE_SIZE) { 1961 pbits = *pte; 1962 if (!pte_test(&pbits, PTE_V) || pte_test(&pbits, 1963 PTE_RO)) { 1964 if (va != va_next) { 1965 pmap_invalidate_range(pmap, va, sva); 1966 va = va_next; 1967 } 1968 continue; 1969 } 1970 pte_set(&pbits, PTE_RO); 1971 if (pte_test(&pbits, PTE_D)) { 1972 pte_clear(&pbits, PTE_D); 1973 if (pte_test(&pbits, PTE_MANAGED)) { 1974 pa = TLBLO_PTE_TO_PA(pbits); 1975 m = PHYS_TO_VM_PAGE(pa); 1976 vm_page_dirty(m); 1977 } 1978 if (va == va_next) 1979 va = sva; 1980 } else { 1981 /* 1982 * Unless PTE_D is set, any TLB entries 1983 * mapping "sva" don't allow write access, so 1984 * they needn't be invalidated. 1985 */ 1986 if (va != va_next) { 1987 pmap_invalidate_range(pmap, va, sva); 1988 va = va_next; 1989 } 1990 } 1991 *pte = pbits; 1992 } 1993 if (va != va_next) 1994 pmap_invalidate_range(pmap, va, sva); 1995 } 1996 PMAP_UNLOCK(pmap); 1997 } 1998 1999 /* 2000 * Insert the given physical page (p) at 2001 * the specified virtual address (v) in the 2002 * target physical map with the protection requested. 2003 * 2004 * If specified, the page will be wired down, meaning 2005 * that the related pte can not be reclaimed. 2006 * 2007 * NB: This is the only routine which MAY NOT lazy-evaluate 2008 * or lose information. That is, this routine must actually 2009 * insert this page into the given map NOW. 2010 */ 2011 int 2012 pmap_enter(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot, 2013 u_int flags, int8_t psind __unused) 2014 { 2015 vm_paddr_t pa, opa; 2016 pt_entry_t *pte; 2017 pt_entry_t origpte, newpte; 2018 pv_entry_t pv; 2019 vm_page_t mpte, om; 2020 2021 va &= ~PAGE_MASK; 2022 KASSERT(va <= VM_MAX_KERNEL_ADDRESS, ("pmap_enter: toobig")); 2023 KASSERT((m->oflags & VPO_UNMANAGED) != 0 || va < kmi.clean_sva || 2024 va >= kmi.clean_eva, 2025 ("pmap_enter: managed mapping within the clean submap")); 2026 if ((m->oflags & VPO_UNMANAGED) == 0 && !vm_page_xbusied(m)) 2027 VM_OBJECT_ASSERT_LOCKED(m->object); 2028 pa = VM_PAGE_TO_PHYS(m); 2029 newpte = TLBLO_PA_TO_PFN(pa) | init_pte_prot(m, flags, prot); 2030 if ((flags & PMAP_ENTER_WIRED) != 0) 2031 newpte |= PTE_W; 2032 if (is_kernel_pmap(pmap)) 2033 newpte |= PTE_G; 2034 if (is_cacheable_page(pa, m)) 2035 newpte |= PTE_C_CACHE; 2036 else 2037 newpte |= PTE_C_UNCACHED; 2038 2039 mpte = NULL; 2040 2041 rw_wlock(&pvh_global_lock); 2042 PMAP_LOCK(pmap); 2043 2044 /* 2045 * In the case that a page table page is not resident, we are 2046 * creating it here. 2047 */ 2048 if (va < VM_MAXUSER_ADDRESS) { 2049 mpte = pmap_allocpte(pmap, va, flags); 2050 if (mpte == NULL) { 2051 KASSERT((flags & PMAP_ENTER_NOSLEEP) != 0, 2052 ("pmap_allocpte failed with sleep allowed")); 2053 rw_wunlock(&pvh_global_lock); 2054 PMAP_UNLOCK(pmap); 2055 return (KERN_RESOURCE_SHORTAGE); 2056 } 2057 } 2058 pte = pmap_pte(pmap, va); 2059 2060 /* 2061 * Page Directory table entry not valid, we need a new PT page 2062 */ 2063 if (pte == NULL) { 2064 panic("pmap_enter: invalid page directory, pdir=%p, va=%p", 2065 (void *)pmap->pm_segtab, (void *)va); 2066 } 2067 om = NULL; 2068 origpte = *pte; 2069 opa = TLBLO_PTE_TO_PA(origpte); 2070 2071 /* 2072 * Mapping has not changed, must be protection or wiring change. 2073 */ 2074 if (pte_test(&origpte, PTE_V) && opa == pa) { 2075 /* 2076 * Wiring change, just update stats. We don't worry about 2077 * wiring PT pages as they remain resident as long as there 2078 * are valid mappings in them. Hence, if a user page is 2079 * wired, the PT page will be also. 2080 */ 2081 if (pte_test(&newpte, PTE_W) && !pte_test(&origpte, PTE_W)) 2082 pmap->pm_stats.wired_count++; 2083 else if (!pte_test(&newpte, PTE_W) && pte_test(&origpte, 2084 PTE_W)) 2085 pmap->pm_stats.wired_count--; 2086 2087 KASSERT(!pte_test(&origpte, PTE_D | PTE_RO), 2088 ("%s: modified page not writable: va: %p, pte: %#jx", 2089 __func__, (void *)va, (uintmax_t)origpte)); 2090 2091 /* 2092 * Remove extra pte reference 2093 */ 2094 if (mpte) 2095 mpte->wire_count--; 2096 2097 if (pte_test(&origpte, PTE_MANAGED)) { 2098 m->md.pv_flags |= PV_TABLE_REF; 2099 om = m; 2100 newpte |= PTE_MANAGED; 2101 if (!pte_test(&newpte, PTE_RO)) 2102 vm_page_aflag_set(m, PGA_WRITEABLE); 2103 } 2104 goto validate; 2105 } 2106 2107 pv = NULL; 2108 2109 /* 2110 * Mapping has changed, invalidate old range and fall through to 2111 * handle validating new mapping. 2112 */ 2113 if (opa) { 2114 if (pte_test(&origpte, PTE_W)) 2115 pmap->pm_stats.wired_count--; 2116 2117 if (pte_test(&origpte, PTE_MANAGED)) { 2118 om = PHYS_TO_VM_PAGE(opa); 2119 pv = pmap_pvh_remove(&om->md, pmap, va); 2120 } 2121 if (mpte != NULL) { 2122 mpte->wire_count--; 2123 KASSERT(mpte->wire_count > 0, 2124 ("pmap_enter: missing reference to page table page," 2125 " va: %p", (void *)va)); 2126 } 2127 } else 2128 pmap->pm_stats.resident_count++; 2129 2130 /* 2131 * Enter on the PV list if part of our managed memory. 2132 */ 2133 if ((m->oflags & VPO_UNMANAGED) == 0) { 2134 m->md.pv_flags |= PV_TABLE_REF; 2135 if (pv == NULL) 2136 pv = get_pv_entry(pmap, FALSE); 2137 pv->pv_va = va; 2138 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_list); 2139 newpte |= PTE_MANAGED; 2140 if (!pte_test(&newpte, PTE_RO)) 2141 vm_page_aflag_set(m, PGA_WRITEABLE); 2142 } else if (pv != NULL) 2143 free_pv_entry(pmap, pv); 2144 2145 /* 2146 * Increment counters 2147 */ 2148 if (pte_test(&newpte, PTE_W)) 2149 pmap->pm_stats.wired_count++; 2150 2151 validate: 2152 2153 #ifdef PMAP_DEBUG 2154 printf("pmap_enter: va: %p -> pa: %p\n", (void *)va, (void *)pa); 2155 #endif 2156 2157 /* 2158 * if the mapping or permission bits are different, we need to 2159 * update the pte. 2160 */ 2161 if (origpte != newpte) { 2162 *pte = newpte; 2163 if (pte_test(&origpte, PTE_V)) { 2164 if (pte_test(&origpte, PTE_MANAGED) && opa != pa) { 2165 if (om->md.pv_flags & PV_TABLE_REF) 2166 vm_page_aflag_set(om, PGA_REFERENCED); 2167 om->md.pv_flags &= ~PV_TABLE_REF; 2168 } 2169 if (pte_test(&origpte, PTE_D)) { 2170 KASSERT(!pte_test(&origpte, PTE_RO), 2171 ("pmap_enter: modified page not writable:" 2172 " va: %p, pte: %#jx", (void *)va, (uintmax_t)origpte)); 2173 if (pte_test(&origpte, PTE_MANAGED)) 2174 vm_page_dirty(om); 2175 } 2176 if (pte_test(&origpte, PTE_MANAGED) && 2177 TAILQ_EMPTY(&om->md.pv_list)) 2178 vm_page_aflag_clear(om, PGA_WRITEABLE); 2179 pmap_update_page(pmap, va, newpte); 2180 } 2181 } 2182 2183 /* 2184 * Sync I & D caches for executable pages. Do this only if the 2185 * target pmap belongs to the current process. Otherwise, an 2186 * unresolvable TLB miss may occur. 2187 */ 2188 if (!is_kernel_pmap(pmap) && (pmap == &curproc->p_vmspace->vm_pmap) && 2189 (prot & VM_PROT_EXECUTE)) { 2190 mips_icache_sync_range(va, PAGE_SIZE); 2191 mips_dcache_wbinv_range(va, PAGE_SIZE); 2192 } 2193 rw_wunlock(&pvh_global_lock); 2194 PMAP_UNLOCK(pmap); 2195 return (KERN_SUCCESS); 2196 } 2197 2198 /* 2199 * this code makes some *MAJOR* assumptions: 2200 * 1. Current pmap & pmap exists. 2201 * 2. Not wired. 2202 * 3. Read access. 2203 * 4. No page table pages. 2204 * but is *MUCH* faster than pmap_enter... 2205 */ 2206 2207 void 2208 pmap_enter_quick(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot) 2209 { 2210 2211 rw_wlock(&pvh_global_lock); 2212 PMAP_LOCK(pmap); 2213 (void)pmap_enter_quick_locked(pmap, va, m, prot, NULL); 2214 rw_wunlock(&pvh_global_lock); 2215 PMAP_UNLOCK(pmap); 2216 } 2217 2218 static vm_page_t 2219 pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va, vm_page_t m, 2220 vm_prot_t prot, vm_page_t mpte) 2221 { 2222 pt_entry_t *pte; 2223 vm_paddr_t pa; 2224 2225 KASSERT(va < kmi.clean_sva || va >= kmi.clean_eva || 2226 (m->oflags & VPO_UNMANAGED) != 0, 2227 ("pmap_enter_quick_locked: managed mapping within the clean submap")); 2228 rw_assert(&pvh_global_lock, RA_WLOCKED); 2229 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 2230 2231 /* 2232 * In the case that a page table page is not resident, we are 2233 * creating it here. 2234 */ 2235 if (va < VM_MAXUSER_ADDRESS) { 2236 pd_entry_t *pde; 2237 unsigned ptepindex; 2238 2239 /* 2240 * Calculate pagetable page index 2241 */ 2242 ptepindex = pmap_pde_pindex(va); 2243 if (mpte && (mpte->pindex == ptepindex)) { 2244 mpte->wire_count++; 2245 } else { 2246 /* 2247 * Get the page directory entry 2248 */ 2249 pde = pmap_pde(pmap, va); 2250 2251 /* 2252 * If the page table page is mapped, we just 2253 * increment the hold count, and activate it. 2254 */ 2255 if (pde && *pde != 0) { 2256 mpte = PHYS_TO_VM_PAGE( 2257 MIPS_DIRECT_TO_PHYS(*pde)); 2258 mpte->wire_count++; 2259 } else { 2260 mpte = _pmap_allocpte(pmap, ptepindex, 2261 PMAP_ENTER_NOSLEEP); 2262 if (mpte == NULL) 2263 return (mpte); 2264 } 2265 } 2266 } else { 2267 mpte = NULL; 2268 } 2269 2270 pte = pmap_pte(pmap, va); 2271 if (pte_test(pte, PTE_V)) { 2272 if (mpte != NULL) { 2273 mpte->wire_count--; 2274 mpte = NULL; 2275 } 2276 return (mpte); 2277 } 2278 2279 /* 2280 * Enter on the PV list if part of our managed memory. 2281 */ 2282 if ((m->oflags & VPO_UNMANAGED) == 0 && 2283 !pmap_try_insert_pv_entry(pmap, mpte, va, m)) { 2284 if (mpte != NULL) { 2285 pmap_unwire_ptp(pmap, va, mpte); 2286 mpte = NULL; 2287 } 2288 return (mpte); 2289 } 2290 2291 /* 2292 * Increment counters 2293 */ 2294 pmap->pm_stats.resident_count++; 2295 2296 pa = VM_PAGE_TO_PHYS(m); 2297 2298 /* 2299 * Now validate mapping with RO protection 2300 */ 2301 *pte = PTE_RO | TLBLO_PA_TO_PFN(pa) | PTE_V; 2302 if ((m->oflags & VPO_UNMANAGED) == 0) 2303 *pte |= PTE_MANAGED; 2304 2305 if (is_cacheable_page(pa, m)) 2306 *pte |= PTE_C_CACHE; 2307 else 2308 *pte |= PTE_C_UNCACHED; 2309 2310 if (is_kernel_pmap(pmap)) 2311 *pte |= PTE_G; 2312 else { 2313 /* 2314 * Sync I & D caches. Do this only if the target pmap 2315 * belongs to the current process. Otherwise, an 2316 * unresolvable TLB miss may occur. */ 2317 if (pmap == &curproc->p_vmspace->vm_pmap) { 2318 va &= ~PAGE_MASK; 2319 mips_icache_sync_range(va, PAGE_SIZE); 2320 mips_dcache_wbinv_range(va, PAGE_SIZE); 2321 } 2322 } 2323 return (mpte); 2324 } 2325 2326 /* 2327 * Make a temporary mapping for a physical address. This is only intended 2328 * to be used for panic dumps. 2329 * 2330 * Use XKPHYS for 64 bit, and KSEG0 where possible for 32 bit. 2331 */ 2332 void * 2333 pmap_kenter_temporary(vm_paddr_t pa, int i) 2334 { 2335 vm_offset_t va; 2336 2337 if (i != 0) 2338 printf("%s: ERROR!!! More than one page of virtual address mapping not supported\n", 2339 __func__); 2340 2341 if (MIPS_DIRECT_MAPPABLE(pa)) { 2342 va = MIPS_PHYS_TO_DIRECT(pa); 2343 } else { 2344 #ifndef __mips_n64 /* XXX : to be converted to new style */ 2345 int cpu; 2346 register_t intr; 2347 struct local_sysmaps *sysm; 2348 pt_entry_t *pte, npte; 2349 2350 /* If this is used other than for dumps, we may need to leave 2351 * interrupts disasbled on return. If crash dumps don't work when 2352 * we get to this point, we might want to consider this (leaving things 2353 * disabled as a starting point ;-) 2354 */ 2355 intr = intr_disable(); 2356 cpu = PCPU_GET(cpuid); 2357 sysm = &sysmap_lmem[cpu]; 2358 /* Since this is for the debugger, no locks or any other fun */ 2359 npte = TLBLO_PA_TO_PFN(pa) | PTE_C_CACHE | PTE_D | PTE_V | 2360 PTE_G; 2361 pte = pmap_pte(kernel_pmap, sysm->base); 2362 *pte = npte; 2363 sysm->valid1 = 1; 2364 pmap_update_page(kernel_pmap, sysm->base, npte); 2365 va = sysm->base; 2366 intr_restore(intr); 2367 #endif 2368 } 2369 return ((void *)va); 2370 } 2371 2372 void 2373 pmap_kenter_temporary_free(vm_paddr_t pa) 2374 { 2375 #ifndef __mips_n64 /* XXX : to be converted to new style */ 2376 int cpu; 2377 register_t intr; 2378 struct local_sysmaps *sysm; 2379 #endif 2380 2381 if (MIPS_DIRECT_MAPPABLE(pa)) { 2382 /* nothing to do for this case */ 2383 return; 2384 } 2385 #ifndef __mips_n64 /* XXX : to be converted to new style */ 2386 cpu = PCPU_GET(cpuid); 2387 sysm = &sysmap_lmem[cpu]; 2388 if (sysm->valid1) { 2389 pt_entry_t *pte; 2390 2391 intr = intr_disable(); 2392 pte = pmap_pte(kernel_pmap, sysm->base); 2393 *pte = PTE_G; 2394 pmap_invalidate_page(kernel_pmap, sysm->base); 2395 intr_restore(intr); 2396 sysm->valid1 = 0; 2397 } 2398 #endif 2399 } 2400 2401 /* 2402 * Maps a sequence of resident pages belonging to the same object. 2403 * The sequence begins with the given page m_start. This page is 2404 * mapped at the given virtual address start. Each subsequent page is 2405 * mapped at a virtual address that is offset from start by the same 2406 * amount as the page is offset from m_start within the object. The 2407 * last page in the sequence is the page with the largest offset from 2408 * m_start that can be mapped at a virtual address less than the given 2409 * virtual address end. Not every virtual page between start and end 2410 * is mapped; only those for which a resident page exists with the 2411 * corresponding offset from m_start are mapped. 2412 */ 2413 void 2414 pmap_enter_object(pmap_t pmap, vm_offset_t start, vm_offset_t end, 2415 vm_page_t m_start, vm_prot_t prot) 2416 { 2417 vm_page_t m, mpte; 2418 vm_pindex_t diff, psize; 2419 2420 VM_OBJECT_ASSERT_LOCKED(m_start->object); 2421 2422 psize = atop(end - start); 2423 mpte = NULL; 2424 m = m_start; 2425 rw_wlock(&pvh_global_lock); 2426 PMAP_LOCK(pmap); 2427 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) { 2428 mpte = pmap_enter_quick_locked(pmap, start + ptoa(diff), m, 2429 prot, mpte); 2430 m = TAILQ_NEXT(m, listq); 2431 } 2432 rw_wunlock(&pvh_global_lock); 2433 PMAP_UNLOCK(pmap); 2434 } 2435 2436 /* 2437 * pmap_object_init_pt preloads the ptes for a given object 2438 * into the specified pmap. This eliminates the blast of soft 2439 * faults on process startup and immediately after an mmap. 2440 */ 2441 void 2442 pmap_object_init_pt(pmap_t pmap, vm_offset_t addr, 2443 vm_object_t object, vm_pindex_t pindex, vm_size_t size) 2444 { 2445 VM_OBJECT_ASSERT_WLOCKED(object); 2446 KASSERT(object->type == OBJT_DEVICE || object->type == OBJT_SG, 2447 ("pmap_object_init_pt: non-device object")); 2448 } 2449 2450 /* 2451 * Clear the wired attribute from the mappings for the specified range of 2452 * addresses in the given pmap. Every valid mapping within that range 2453 * must have the wired attribute set. In contrast, invalid mappings 2454 * cannot have the wired attribute set, so they are ignored. 2455 * 2456 * The wired attribute of the page table entry is not a hardware feature, 2457 * so there is no need to invalidate any TLB entries. 2458 */ 2459 void 2460 pmap_unwire(pmap_t pmap, vm_offset_t sva, vm_offset_t eva) 2461 { 2462 pd_entry_t *pde, *pdpe; 2463 pt_entry_t *pte; 2464 vm_offset_t va_next; 2465 2466 PMAP_LOCK(pmap); 2467 for (; sva < eva; sva = va_next) { 2468 pdpe = pmap_segmap(pmap, sva); 2469 #ifdef __mips_n64 2470 if (*pdpe == NULL) { 2471 va_next = (sva + NBSEG) & ~SEGMASK; 2472 if (va_next < sva) 2473 va_next = eva; 2474 continue; 2475 } 2476 #endif 2477 va_next = (sva + NBPDR) & ~PDRMASK; 2478 if (va_next < sva) 2479 va_next = eva; 2480 pde = pmap_pdpe_to_pde(pdpe, sva); 2481 if (*pde == NULL) 2482 continue; 2483 if (va_next > eva) 2484 va_next = eva; 2485 for (pte = pmap_pde_to_pte(pde, sva); sva != va_next; pte++, 2486 sva += PAGE_SIZE) { 2487 if (!pte_test(pte, PTE_V)) 2488 continue; 2489 if (!pte_test(pte, PTE_W)) 2490 panic("pmap_unwire: pte %#jx is missing PG_W", 2491 (uintmax_t)*pte); 2492 pte_clear(pte, PTE_W); 2493 pmap->pm_stats.wired_count--; 2494 } 2495 } 2496 PMAP_UNLOCK(pmap); 2497 } 2498 2499 /* 2500 * Copy the range specified by src_addr/len 2501 * from the source map to the range dst_addr/len 2502 * in the destination map. 2503 * 2504 * This routine is only advisory and need not do anything. 2505 */ 2506 2507 void 2508 pmap_copy(pmap_t dst_pmap, pmap_t src_pmap, vm_offset_t dst_addr, 2509 vm_size_t len, vm_offset_t src_addr) 2510 { 2511 } 2512 2513 /* 2514 * pmap_zero_page zeros the specified hardware page by mapping 2515 * the page into KVM and using bzero to clear its contents. 2516 * 2517 * Use XKPHYS for 64 bit, and KSEG0 where possible for 32 bit. 2518 */ 2519 void 2520 pmap_zero_page(vm_page_t m) 2521 { 2522 vm_offset_t va; 2523 vm_paddr_t phys = VM_PAGE_TO_PHYS(m); 2524 2525 if (MIPS_DIRECT_MAPPABLE(phys)) { 2526 va = MIPS_PHYS_TO_DIRECT(phys); 2527 bzero((caddr_t)va, PAGE_SIZE); 2528 mips_dcache_wbinv_range(va, PAGE_SIZE); 2529 } else { 2530 va = pmap_lmem_map1(phys); 2531 bzero((caddr_t)va, PAGE_SIZE); 2532 mips_dcache_wbinv_range(va, PAGE_SIZE); 2533 pmap_lmem_unmap(); 2534 } 2535 } 2536 2537 /* 2538 * pmap_zero_page_area zeros the specified hardware page by mapping 2539 * the page into KVM and using bzero to clear its contents. 2540 * 2541 * off and size may not cover an area beyond a single hardware page. 2542 */ 2543 void 2544 pmap_zero_page_area(vm_page_t m, int off, int size) 2545 { 2546 vm_offset_t va; 2547 vm_paddr_t phys = VM_PAGE_TO_PHYS(m); 2548 2549 if (MIPS_DIRECT_MAPPABLE(phys)) { 2550 va = MIPS_PHYS_TO_DIRECT(phys); 2551 bzero((char *)(caddr_t)va + off, size); 2552 mips_dcache_wbinv_range(va + off, size); 2553 } else { 2554 va = pmap_lmem_map1(phys); 2555 bzero((char *)va + off, size); 2556 mips_dcache_wbinv_range(va + off, size); 2557 pmap_lmem_unmap(); 2558 } 2559 } 2560 2561 void 2562 pmap_zero_page_idle(vm_page_t m) 2563 { 2564 vm_offset_t va; 2565 vm_paddr_t phys = VM_PAGE_TO_PHYS(m); 2566 2567 if (MIPS_DIRECT_MAPPABLE(phys)) { 2568 va = MIPS_PHYS_TO_DIRECT(phys); 2569 bzero((caddr_t)va, PAGE_SIZE); 2570 mips_dcache_wbinv_range(va, PAGE_SIZE); 2571 } else { 2572 va = pmap_lmem_map1(phys); 2573 bzero((caddr_t)va, PAGE_SIZE); 2574 mips_dcache_wbinv_range(va, PAGE_SIZE); 2575 pmap_lmem_unmap(); 2576 } 2577 } 2578 2579 /* 2580 * pmap_copy_page copies the specified (machine independent) 2581 * page by mapping the page into virtual memory and using 2582 * bcopy to copy the page, one machine dependent page at a 2583 * time. 2584 * 2585 * Use XKPHYS for 64 bit, and KSEG0 where possible for 32 bit. 2586 */ 2587 void 2588 pmap_copy_page(vm_page_t src, vm_page_t dst) 2589 { 2590 vm_offset_t va_src, va_dst; 2591 vm_paddr_t phys_src = VM_PAGE_TO_PHYS(src); 2592 vm_paddr_t phys_dst = VM_PAGE_TO_PHYS(dst); 2593 2594 if (MIPS_DIRECT_MAPPABLE(phys_src) && MIPS_DIRECT_MAPPABLE(phys_dst)) { 2595 /* easy case, all can be accessed via KSEG0 */ 2596 /* 2597 * Flush all caches for VA that are mapped to this page 2598 * to make sure that data in SDRAM is up to date 2599 */ 2600 pmap_flush_pvcache(src); 2601 mips_dcache_wbinv_range_index( 2602 MIPS_PHYS_TO_DIRECT(phys_dst), PAGE_SIZE); 2603 va_src = MIPS_PHYS_TO_DIRECT(phys_src); 2604 va_dst = MIPS_PHYS_TO_DIRECT(phys_dst); 2605 bcopy((caddr_t)va_src, (caddr_t)va_dst, PAGE_SIZE); 2606 mips_dcache_wbinv_range(va_dst, PAGE_SIZE); 2607 } else { 2608 va_src = pmap_lmem_map2(phys_src, phys_dst); 2609 va_dst = va_src + PAGE_SIZE; 2610 bcopy((void *)va_src, (void *)va_dst, PAGE_SIZE); 2611 mips_dcache_wbinv_range(va_dst, PAGE_SIZE); 2612 pmap_lmem_unmap(); 2613 } 2614 } 2615 2616 int unmapped_buf_allowed; 2617 2618 void 2619 pmap_copy_pages(vm_page_t ma[], vm_offset_t a_offset, vm_page_t mb[], 2620 vm_offset_t b_offset, int xfersize) 2621 { 2622 char *a_cp, *b_cp; 2623 vm_page_t a_m, b_m; 2624 vm_offset_t a_pg_offset, b_pg_offset; 2625 vm_paddr_t a_phys, b_phys; 2626 int cnt; 2627 2628 while (xfersize > 0) { 2629 a_pg_offset = a_offset & PAGE_MASK; 2630 cnt = min(xfersize, PAGE_SIZE - a_pg_offset); 2631 a_m = ma[a_offset >> PAGE_SHIFT]; 2632 a_phys = VM_PAGE_TO_PHYS(a_m); 2633 b_pg_offset = b_offset & PAGE_MASK; 2634 cnt = min(cnt, PAGE_SIZE - b_pg_offset); 2635 b_m = mb[b_offset >> PAGE_SHIFT]; 2636 b_phys = VM_PAGE_TO_PHYS(b_m); 2637 if (MIPS_DIRECT_MAPPABLE(a_phys) && 2638 MIPS_DIRECT_MAPPABLE(b_phys)) { 2639 pmap_flush_pvcache(a_m); 2640 mips_dcache_wbinv_range_index( 2641 MIPS_PHYS_TO_DIRECT(b_phys), PAGE_SIZE); 2642 a_cp = (char *)MIPS_PHYS_TO_DIRECT(a_phys) + 2643 a_pg_offset; 2644 b_cp = (char *)MIPS_PHYS_TO_DIRECT(b_phys) + 2645 b_pg_offset; 2646 bcopy(a_cp, b_cp, cnt); 2647 mips_dcache_wbinv_range((vm_offset_t)b_cp, cnt); 2648 } else { 2649 a_cp = (char *)pmap_lmem_map2(a_phys, b_phys); 2650 b_cp = (char *)a_cp + PAGE_SIZE; 2651 a_cp += a_pg_offset; 2652 b_cp += b_pg_offset; 2653 bcopy(a_cp, b_cp, cnt); 2654 mips_dcache_wbinv_range((vm_offset_t)b_cp, cnt); 2655 pmap_lmem_unmap(); 2656 } 2657 a_offset += cnt; 2658 b_offset += cnt; 2659 xfersize -= cnt; 2660 } 2661 } 2662 2663 vm_offset_t 2664 pmap_quick_enter_page(vm_page_t m) 2665 { 2666 #if defined(__mips_n64) 2667 return MIPS_PHYS_TO_DIRECT(VM_PAGE_TO_PHYS(m)); 2668 #else 2669 vm_paddr_t pa; 2670 struct local_sysmaps *sysm; 2671 pt_entry_t *pte; 2672 2673 pa = VM_PAGE_TO_PHYS(m); 2674 2675 if (MIPS_DIRECT_MAPPABLE(pa)) { 2676 if (m->md.pv_flags & PV_MEMATTR_UNCACHEABLE) 2677 return (MIPS_PHYS_TO_DIRECT_UNCACHED(pa)); 2678 else 2679 return (MIPS_PHYS_TO_DIRECT(pa)); 2680 } 2681 critical_enter(); 2682 sysm = &sysmap_lmem[PCPU_GET(cpuid)]; 2683 2684 KASSERT(sysm->valid1 == 0, ("pmap_quick_enter_page: PTE busy")); 2685 2686 pte = pmap_pte(kernel_pmap, sysm->base); 2687 *pte = TLBLO_PA_TO_PFN(pa) | PTE_D | PTE_V | PTE_G | 2688 (is_cacheable_page(pa, m) ? PTE_C_CACHE : PTE_C_UNCACHED); 2689 sysm->valid1 = 1; 2690 2691 return (sysm->base); 2692 #endif 2693 } 2694 2695 void 2696 pmap_quick_remove_page(vm_offset_t addr) 2697 { 2698 mips_dcache_wbinv_range(addr, PAGE_SIZE); 2699 2700 #if !defined(__mips_n64) 2701 struct local_sysmaps *sysm; 2702 pt_entry_t *pte; 2703 2704 if (addr >= MIPS_KSEG0_START && addr < MIPS_KSEG0_END) 2705 return; 2706 2707 sysm = &sysmap_lmem[PCPU_GET(cpuid)]; 2708 2709 KASSERT(sysm->valid1 != 0, 2710 ("pmap_quick_remove_page: PTE not in use")); 2711 KASSERT(sysm->base == addr, 2712 ("pmap_quick_remove_page: invalid address")); 2713 2714 pte = pmap_pte(kernel_pmap, addr); 2715 *pte = PTE_G; 2716 tlb_invalidate_address(kernel_pmap, addr); 2717 sysm->valid1 = 0; 2718 critical_exit(); 2719 #endif 2720 } 2721 2722 /* 2723 * Returns true if the pmap's pv is one of the first 2724 * 16 pvs linked to from this page. This count may 2725 * be changed upwards or downwards in the future; it 2726 * is only necessary that true be returned for a small 2727 * subset of pmaps for proper page aging. 2728 */ 2729 boolean_t 2730 pmap_page_exists_quick(pmap_t pmap, vm_page_t m) 2731 { 2732 pv_entry_t pv; 2733 int loops = 0; 2734 boolean_t rv; 2735 2736 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 2737 ("pmap_page_exists_quick: page %p is not managed", m)); 2738 rv = FALSE; 2739 rw_wlock(&pvh_global_lock); 2740 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) { 2741 if (PV_PMAP(pv) == pmap) { 2742 rv = TRUE; 2743 break; 2744 } 2745 loops++; 2746 if (loops >= 16) 2747 break; 2748 } 2749 rw_wunlock(&pvh_global_lock); 2750 return (rv); 2751 } 2752 2753 /* 2754 * Remove all pages from specified address space 2755 * this aids process exit speeds. Also, this code 2756 * is special cased for current process only, but 2757 * can have the more generic (and slightly slower) 2758 * mode enabled. This is much faster than pmap_remove 2759 * in the case of running down an entire address space. 2760 */ 2761 void 2762 pmap_remove_pages(pmap_t pmap) 2763 { 2764 pd_entry_t *pde; 2765 pt_entry_t *pte, tpte; 2766 pv_entry_t pv; 2767 vm_page_t m; 2768 struct pv_chunk *pc, *npc; 2769 u_long inuse, bitmask; 2770 int allfree, bit, field, idx; 2771 2772 if (pmap != vmspace_pmap(curthread->td_proc->p_vmspace)) { 2773 printf("warning: pmap_remove_pages called with non-current pmap\n"); 2774 return; 2775 } 2776 rw_wlock(&pvh_global_lock); 2777 PMAP_LOCK(pmap); 2778 TAILQ_FOREACH_SAFE(pc, &pmap->pm_pvchunk, pc_list, npc) { 2779 allfree = 1; 2780 for (field = 0; field < _NPCM; field++) { 2781 inuse = ~pc->pc_map[field] & pc_freemask[field]; 2782 while (inuse != 0) { 2783 bit = ffsl(inuse) - 1; 2784 bitmask = 1UL << bit; 2785 idx = field * sizeof(inuse) * NBBY + bit; 2786 pv = &pc->pc_pventry[idx]; 2787 inuse &= ~bitmask; 2788 2789 pde = pmap_pde(pmap, pv->pv_va); 2790 KASSERT(pde != NULL && *pde != 0, 2791 ("pmap_remove_pages: pde")); 2792 pte = pmap_pde_to_pte(pde, pv->pv_va); 2793 if (!pte_test(pte, PTE_V)) 2794 panic("pmap_remove_pages: bad pte"); 2795 tpte = *pte; 2796 2797 /* 2798 * We cannot remove wired pages from a process' mapping at this time 2799 */ 2800 if (pte_test(&tpte, PTE_W)) { 2801 allfree = 0; 2802 continue; 2803 } 2804 *pte = is_kernel_pmap(pmap) ? PTE_G : 0; 2805 2806 m = PHYS_TO_VM_PAGE(TLBLO_PTE_TO_PA(tpte)); 2807 KASSERT(m != NULL, 2808 ("pmap_remove_pages: bad tpte %#jx", 2809 (uintmax_t)tpte)); 2810 2811 /* 2812 * Update the vm_page_t clean and reference bits. 2813 */ 2814 if (pte_test(&tpte, PTE_D)) 2815 vm_page_dirty(m); 2816 2817 /* Mark free */ 2818 PV_STAT(pv_entry_frees++); 2819 PV_STAT(pv_entry_spare++); 2820 pv_entry_count--; 2821 pc->pc_map[field] |= bitmask; 2822 pmap->pm_stats.resident_count--; 2823 TAILQ_REMOVE(&m->md.pv_list, pv, pv_list); 2824 if (TAILQ_EMPTY(&m->md.pv_list)) 2825 vm_page_aflag_clear(m, PGA_WRITEABLE); 2826 pmap_unuse_pt(pmap, pv->pv_va, *pde); 2827 } 2828 } 2829 if (allfree) { 2830 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list); 2831 free_pv_chunk(pc); 2832 } 2833 } 2834 pmap_invalidate_all(pmap); 2835 PMAP_UNLOCK(pmap); 2836 rw_wunlock(&pvh_global_lock); 2837 } 2838 2839 /* 2840 * pmap_testbit tests bits in pte's 2841 */ 2842 static boolean_t 2843 pmap_testbit(vm_page_t m, int bit) 2844 { 2845 pv_entry_t pv; 2846 pmap_t pmap; 2847 pt_entry_t *pte; 2848 boolean_t rv = FALSE; 2849 2850 if (m->oflags & VPO_UNMANAGED) 2851 return (rv); 2852 2853 rw_assert(&pvh_global_lock, RA_WLOCKED); 2854 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) { 2855 pmap = PV_PMAP(pv); 2856 PMAP_LOCK(pmap); 2857 pte = pmap_pte(pmap, pv->pv_va); 2858 rv = pte_test(pte, bit); 2859 PMAP_UNLOCK(pmap); 2860 if (rv) 2861 break; 2862 } 2863 return (rv); 2864 } 2865 2866 /* 2867 * pmap_page_wired_mappings: 2868 * 2869 * Return the number of managed mappings to the given physical page 2870 * that are wired. 2871 */ 2872 int 2873 pmap_page_wired_mappings(vm_page_t m) 2874 { 2875 pv_entry_t pv; 2876 pmap_t pmap; 2877 pt_entry_t *pte; 2878 int count; 2879 2880 count = 0; 2881 if ((m->oflags & VPO_UNMANAGED) != 0) 2882 return (count); 2883 rw_wlock(&pvh_global_lock); 2884 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) { 2885 pmap = PV_PMAP(pv); 2886 PMAP_LOCK(pmap); 2887 pte = pmap_pte(pmap, pv->pv_va); 2888 if (pte_test(pte, PTE_W)) 2889 count++; 2890 PMAP_UNLOCK(pmap); 2891 } 2892 rw_wunlock(&pvh_global_lock); 2893 return (count); 2894 } 2895 2896 /* 2897 * Clear the write and modified bits in each of the given page's mappings. 2898 */ 2899 void 2900 pmap_remove_write(vm_page_t m) 2901 { 2902 pmap_t pmap; 2903 pt_entry_t pbits, *pte; 2904 pv_entry_t pv; 2905 2906 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 2907 ("pmap_remove_write: page %p is not managed", m)); 2908 2909 /* 2910 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be 2911 * set by another thread while the object is locked. Thus, 2912 * if PGA_WRITEABLE is clear, no page table entries need updating. 2913 */ 2914 VM_OBJECT_ASSERT_WLOCKED(m->object); 2915 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0) 2916 return; 2917 rw_wlock(&pvh_global_lock); 2918 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) { 2919 pmap = PV_PMAP(pv); 2920 PMAP_LOCK(pmap); 2921 pte = pmap_pte(pmap, pv->pv_va); 2922 KASSERT(pte != NULL && pte_test(pte, PTE_V), 2923 ("page on pv_list has no pte")); 2924 pbits = *pte; 2925 if (pte_test(&pbits, PTE_D)) { 2926 pte_clear(&pbits, PTE_D); 2927 vm_page_dirty(m); 2928 } 2929 pte_set(&pbits, PTE_RO); 2930 if (pbits != *pte) { 2931 *pte = pbits; 2932 pmap_update_page(pmap, pv->pv_va, pbits); 2933 } 2934 PMAP_UNLOCK(pmap); 2935 } 2936 vm_page_aflag_clear(m, PGA_WRITEABLE); 2937 rw_wunlock(&pvh_global_lock); 2938 } 2939 2940 /* 2941 * pmap_ts_referenced: 2942 * 2943 * Return the count of reference bits for a page, clearing all of them. 2944 */ 2945 int 2946 pmap_ts_referenced(vm_page_t m) 2947 { 2948 2949 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 2950 ("pmap_ts_referenced: page %p is not managed", m)); 2951 if (m->md.pv_flags & PV_TABLE_REF) { 2952 rw_wlock(&pvh_global_lock); 2953 m->md.pv_flags &= ~PV_TABLE_REF; 2954 rw_wunlock(&pvh_global_lock); 2955 return (1); 2956 } 2957 return (0); 2958 } 2959 2960 /* 2961 * pmap_is_modified: 2962 * 2963 * Return whether or not the specified physical page was modified 2964 * in any physical maps. 2965 */ 2966 boolean_t 2967 pmap_is_modified(vm_page_t m) 2968 { 2969 boolean_t rv; 2970 2971 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 2972 ("pmap_is_modified: page %p is not managed", m)); 2973 2974 /* 2975 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be 2976 * concurrently set while the object is locked. Thus, if PGA_WRITEABLE 2977 * is clear, no PTEs can have PTE_D set. 2978 */ 2979 VM_OBJECT_ASSERT_WLOCKED(m->object); 2980 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0) 2981 return (FALSE); 2982 rw_wlock(&pvh_global_lock); 2983 rv = pmap_testbit(m, PTE_D); 2984 rw_wunlock(&pvh_global_lock); 2985 return (rv); 2986 } 2987 2988 /* N/C */ 2989 2990 /* 2991 * pmap_is_prefaultable: 2992 * 2993 * Return whether or not the specified virtual address is elgible 2994 * for prefault. 2995 */ 2996 boolean_t 2997 pmap_is_prefaultable(pmap_t pmap, vm_offset_t addr) 2998 { 2999 pd_entry_t *pde; 3000 pt_entry_t *pte; 3001 boolean_t rv; 3002 3003 rv = FALSE; 3004 PMAP_LOCK(pmap); 3005 pde = pmap_pde(pmap, addr); 3006 if (pde != NULL && *pde != 0) { 3007 pte = pmap_pde_to_pte(pde, addr); 3008 rv = (*pte == 0); 3009 } 3010 PMAP_UNLOCK(pmap); 3011 return (rv); 3012 } 3013 3014 /* 3015 * Apply the given advice to the specified range of addresses within the 3016 * given pmap. Depending on the advice, clear the referenced and/or 3017 * modified flags in each mapping and set the mapped page's dirty field. 3018 */ 3019 void 3020 pmap_advise(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, int advice) 3021 { 3022 pd_entry_t *pde, *pdpe; 3023 pt_entry_t *pte; 3024 vm_offset_t va, va_next; 3025 vm_paddr_t pa; 3026 vm_page_t m; 3027 3028 if (advice != MADV_DONTNEED && advice != MADV_FREE) 3029 return; 3030 rw_wlock(&pvh_global_lock); 3031 PMAP_LOCK(pmap); 3032 for (; sva < eva; sva = va_next) { 3033 pdpe = pmap_segmap(pmap, sva); 3034 #ifdef __mips_n64 3035 if (*pdpe == 0) { 3036 va_next = (sva + NBSEG) & ~SEGMASK; 3037 if (va_next < sva) 3038 va_next = eva; 3039 continue; 3040 } 3041 #endif 3042 va_next = (sva + NBPDR) & ~PDRMASK; 3043 if (va_next < sva) 3044 va_next = eva; 3045 3046 pde = pmap_pdpe_to_pde(pdpe, sva); 3047 if (*pde == NULL) 3048 continue; 3049 3050 /* 3051 * Limit our scan to either the end of the va represented 3052 * by the current page table page, or to the end of the 3053 * range being write protected. 3054 */ 3055 if (va_next > eva) 3056 va_next = eva; 3057 3058 va = va_next; 3059 for (pte = pmap_pde_to_pte(pde, sva); sva != va_next; pte++, 3060 sva += PAGE_SIZE) { 3061 if (!pte_test(pte, PTE_MANAGED | PTE_V)) { 3062 if (va != va_next) { 3063 pmap_invalidate_range(pmap, va, sva); 3064 va = va_next; 3065 } 3066 continue; 3067 } 3068 pa = TLBLO_PTE_TO_PA(*pte); 3069 m = PHYS_TO_VM_PAGE(pa); 3070 m->md.pv_flags &= ~PV_TABLE_REF; 3071 if (pte_test(pte, PTE_D)) { 3072 if (advice == MADV_DONTNEED) { 3073 /* 3074 * Future calls to pmap_is_modified() 3075 * can be avoided by making the page 3076 * dirty now. 3077 */ 3078 vm_page_dirty(m); 3079 } else { 3080 pte_clear(pte, PTE_D); 3081 if (va == va_next) 3082 va = sva; 3083 } 3084 } else { 3085 /* 3086 * Unless PTE_D is set, any TLB entries 3087 * mapping "sva" don't allow write access, so 3088 * they needn't be invalidated. 3089 */ 3090 if (va != va_next) { 3091 pmap_invalidate_range(pmap, va, sva); 3092 va = va_next; 3093 } 3094 } 3095 } 3096 if (va != va_next) 3097 pmap_invalidate_range(pmap, va, sva); 3098 } 3099 rw_wunlock(&pvh_global_lock); 3100 PMAP_UNLOCK(pmap); 3101 } 3102 3103 /* 3104 * Clear the modify bits on the specified physical page. 3105 */ 3106 void 3107 pmap_clear_modify(vm_page_t m) 3108 { 3109 pmap_t pmap; 3110 pt_entry_t *pte; 3111 pv_entry_t pv; 3112 3113 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 3114 ("pmap_clear_modify: page %p is not managed", m)); 3115 VM_OBJECT_ASSERT_WLOCKED(m->object); 3116 KASSERT(!vm_page_xbusied(m), 3117 ("pmap_clear_modify: page %p is exclusive busied", m)); 3118 3119 /* 3120 * If the page is not PGA_WRITEABLE, then no PTEs can have PTE_D set. 3121 * If the object containing the page is locked and the page is not 3122 * write busied, then PGA_WRITEABLE cannot be concurrently set. 3123 */ 3124 if ((m->aflags & PGA_WRITEABLE) == 0) 3125 return; 3126 rw_wlock(&pvh_global_lock); 3127 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) { 3128 pmap = PV_PMAP(pv); 3129 PMAP_LOCK(pmap); 3130 pte = pmap_pte(pmap, pv->pv_va); 3131 if (pte_test(pte, PTE_D)) { 3132 pte_clear(pte, PTE_D); 3133 pmap_update_page(pmap, pv->pv_va, *pte); 3134 } 3135 PMAP_UNLOCK(pmap); 3136 } 3137 rw_wunlock(&pvh_global_lock); 3138 } 3139 3140 /* 3141 * pmap_is_referenced: 3142 * 3143 * Return whether or not the specified physical page was referenced 3144 * in any physical maps. 3145 */ 3146 boolean_t 3147 pmap_is_referenced(vm_page_t m) 3148 { 3149 3150 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 3151 ("pmap_is_referenced: page %p is not managed", m)); 3152 return ((m->md.pv_flags & PV_TABLE_REF) != 0); 3153 } 3154 3155 /* 3156 * Miscellaneous support routines follow 3157 */ 3158 3159 /* 3160 * Map a set of physical memory pages into the kernel virtual 3161 * address space. Return a pointer to where it is mapped. This 3162 * routine is intended to be used for mapping device memory, 3163 * NOT real memory. 3164 * 3165 * Use XKPHYS uncached for 64 bit, and KSEG1 where possible for 32 bit. 3166 */ 3167 void * 3168 pmap_mapdev(vm_paddr_t pa, vm_size_t size) 3169 { 3170 vm_offset_t va, tmpva, offset; 3171 3172 /* 3173 * KSEG1 maps only first 512M of phys address space. For 3174 * pa > 0x20000000 we should make proper mapping * using pmap_kenter. 3175 */ 3176 if (MIPS_DIRECT_MAPPABLE(pa + size - 1)) 3177 return ((void *)MIPS_PHYS_TO_DIRECT_UNCACHED(pa)); 3178 else { 3179 offset = pa & PAGE_MASK; 3180 size = roundup(size + offset, PAGE_SIZE); 3181 3182 va = kva_alloc(size); 3183 if (!va) 3184 panic("pmap_mapdev: Couldn't alloc kernel virtual memory"); 3185 pa = trunc_page(pa); 3186 for (tmpva = va; size > 0;) { 3187 pmap_kenter_attr(tmpva, pa, PTE_C_UNCACHED); 3188 size -= PAGE_SIZE; 3189 tmpva += PAGE_SIZE; 3190 pa += PAGE_SIZE; 3191 } 3192 } 3193 3194 return ((void *)(va + offset)); 3195 } 3196 3197 void 3198 pmap_unmapdev(vm_offset_t va, vm_size_t size) 3199 { 3200 #ifndef __mips_n64 3201 vm_offset_t base, offset; 3202 3203 /* If the address is within KSEG1 then there is nothing to do */ 3204 if (va >= MIPS_KSEG1_START && va <= MIPS_KSEG1_END) 3205 return; 3206 3207 base = trunc_page(va); 3208 offset = va & PAGE_MASK; 3209 size = roundup(size + offset, PAGE_SIZE); 3210 kva_free(base, size); 3211 #endif 3212 } 3213 3214 /* 3215 * perform the pmap work for mincore 3216 */ 3217 int 3218 pmap_mincore(pmap_t pmap, vm_offset_t addr, vm_paddr_t *locked_pa) 3219 { 3220 pt_entry_t *ptep, pte; 3221 vm_paddr_t pa; 3222 vm_page_t m; 3223 int val; 3224 3225 PMAP_LOCK(pmap); 3226 retry: 3227 ptep = pmap_pte(pmap, addr); 3228 pte = (ptep != NULL) ? *ptep : 0; 3229 if (!pte_test(&pte, PTE_V)) { 3230 val = 0; 3231 goto out; 3232 } 3233 val = MINCORE_INCORE; 3234 if (pte_test(&pte, PTE_D)) 3235 val |= MINCORE_MODIFIED | MINCORE_MODIFIED_OTHER; 3236 pa = TLBLO_PTE_TO_PA(pte); 3237 if (pte_test(&pte, PTE_MANAGED)) { 3238 /* 3239 * This may falsely report the given address as 3240 * MINCORE_REFERENCED. Unfortunately, due to the lack of 3241 * per-PTE reference information, it is impossible to 3242 * determine if the address is MINCORE_REFERENCED. 3243 */ 3244 m = PHYS_TO_VM_PAGE(pa); 3245 if ((m->aflags & PGA_REFERENCED) != 0) 3246 val |= MINCORE_REFERENCED | MINCORE_REFERENCED_OTHER; 3247 } 3248 if ((val & (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER)) != 3249 (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER) && 3250 pte_test(&pte, PTE_MANAGED)) { 3251 /* Ensure that "PHYS_TO_VM_PAGE(pa)->object" doesn't change. */ 3252 if (vm_page_pa_tryrelock(pmap, pa, locked_pa)) 3253 goto retry; 3254 } else 3255 out: 3256 PA_UNLOCK_COND(*locked_pa); 3257 PMAP_UNLOCK(pmap); 3258 return (val); 3259 } 3260 3261 void 3262 pmap_activate(struct thread *td) 3263 { 3264 pmap_t pmap, oldpmap; 3265 struct proc *p = td->td_proc; 3266 u_int cpuid; 3267 3268 critical_enter(); 3269 3270 pmap = vmspace_pmap(p->p_vmspace); 3271 oldpmap = PCPU_GET(curpmap); 3272 cpuid = PCPU_GET(cpuid); 3273 3274 if (oldpmap) 3275 CPU_CLR_ATOMIC(cpuid, &oldpmap->pm_active); 3276 CPU_SET_ATOMIC(cpuid, &pmap->pm_active); 3277 pmap_asid_alloc(pmap); 3278 if (td == curthread) { 3279 PCPU_SET(segbase, pmap->pm_segtab); 3280 mips_wr_entryhi(pmap->pm_asid[cpuid].asid); 3281 } 3282 3283 PCPU_SET(curpmap, pmap); 3284 critical_exit(); 3285 } 3286 3287 void 3288 pmap_sync_icache(pmap_t pm, vm_offset_t va, vm_size_t sz) 3289 { 3290 } 3291 3292 /* 3293 * Increase the starting virtual address of the given mapping if a 3294 * different alignment might result in more superpage mappings. 3295 */ 3296 void 3297 pmap_align_superpage(vm_object_t object, vm_ooffset_t offset, 3298 vm_offset_t *addr, vm_size_t size) 3299 { 3300 vm_offset_t superpage_offset; 3301 3302 if (size < PDRSIZE) 3303 return; 3304 if (object != NULL && (object->flags & OBJ_COLORED) != 0) 3305 offset += ptoa(object->pg_color); 3306 superpage_offset = offset & PDRMASK; 3307 if (size - ((PDRSIZE - superpage_offset) & PDRMASK) < PDRSIZE || 3308 (*addr & PDRMASK) == superpage_offset) 3309 return; 3310 if ((*addr & PDRMASK) < superpage_offset) 3311 *addr = (*addr & ~PDRMASK) + superpage_offset; 3312 else 3313 *addr = ((*addr + PDRMASK) & ~PDRMASK) + superpage_offset; 3314 } 3315 3316 #ifdef DDB 3317 DB_SHOW_COMMAND(ptable, ddb_pid_dump) 3318 { 3319 pmap_t pmap; 3320 struct thread *td = NULL; 3321 struct proc *p; 3322 int i, j, k; 3323 vm_paddr_t pa; 3324 vm_offset_t va; 3325 3326 if (have_addr) { 3327 td = db_lookup_thread(addr, true); 3328 if (td == NULL) { 3329 db_printf("Invalid pid or tid"); 3330 return; 3331 } 3332 p = td->td_proc; 3333 if (p->p_vmspace == NULL) { 3334 db_printf("No vmspace for process"); 3335 return; 3336 } 3337 pmap = vmspace_pmap(p->p_vmspace); 3338 } else 3339 pmap = kernel_pmap; 3340 3341 db_printf("pmap:%p segtab:%p asid:%x generation:%x\n", 3342 pmap, pmap->pm_segtab, pmap->pm_asid[0].asid, 3343 pmap->pm_asid[0].gen); 3344 for (i = 0; i < NPDEPG; i++) { 3345 pd_entry_t *pdpe; 3346 pt_entry_t *pde; 3347 pt_entry_t pte; 3348 3349 pdpe = (pd_entry_t *)pmap->pm_segtab[i]; 3350 if (pdpe == NULL) 3351 continue; 3352 db_printf("[%4d] %p\n", i, pdpe); 3353 #ifdef __mips_n64 3354 for (j = 0; j < NPDEPG; j++) { 3355 pde = (pt_entry_t *)pdpe[j]; 3356 if (pde == NULL) 3357 continue; 3358 db_printf("\t[%4d] %p\n", j, pde); 3359 #else 3360 { 3361 j = 0; 3362 pde = (pt_entry_t *)pdpe; 3363 #endif 3364 for (k = 0; k < NPTEPG; k++) { 3365 pte = pde[k]; 3366 if (pte == 0 || !pte_test(&pte, PTE_V)) 3367 continue; 3368 pa = TLBLO_PTE_TO_PA(pte); 3369 va = ((u_long)i << SEGSHIFT) | (j << PDRSHIFT) | (k << PAGE_SHIFT); 3370 db_printf("\t\t[%04d] va: %p pte: %8jx pa:%jx\n", 3371 k, (void *)va, (uintmax_t)pte, (uintmax_t)pa); 3372 } 3373 } 3374 } 3375 } 3376 #endif 3377 3378 /* 3379 * Allocate TLB address space tag (called ASID or TLBPID) and return it. 3380 * It takes almost as much or more time to search the TLB for a 3381 * specific ASID and flush those entries as it does to flush the entire TLB. 3382 * Therefore, when we allocate a new ASID, we just take the next number. When 3383 * we run out of numbers, we flush the TLB, increment the generation count 3384 * and start over. ASID zero is reserved for kernel use. 3385 */ 3386 static void 3387 pmap_asid_alloc(pmap) 3388 pmap_t pmap; 3389 { 3390 if (pmap->pm_asid[PCPU_GET(cpuid)].asid != PMAP_ASID_RESERVED && 3391 pmap->pm_asid[PCPU_GET(cpuid)].gen == PCPU_GET(asid_generation)); 3392 else { 3393 if (PCPU_GET(next_asid) == pmap_max_asid) { 3394 tlb_invalidate_all_user(NULL); 3395 PCPU_SET(asid_generation, 3396 (PCPU_GET(asid_generation) + 1) & ASIDGEN_MASK); 3397 if (PCPU_GET(asid_generation) == 0) { 3398 PCPU_SET(asid_generation, 1); 3399 } 3400 PCPU_SET(next_asid, 1); /* 0 means invalid */ 3401 } 3402 pmap->pm_asid[PCPU_GET(cpuid)].asid = PCPU_GET(next_asid); 3403 pmap->pm_asid[PCPU_GET(cpuid)].gen = PCPU_GET(asid_generation); 3404 PCPU_SET(next_asid, PCPU_GET(next_asid) + 1); 3405 } 3406 } 3407 3408 static pt_entry_t 3409 init_pte_prot(vm_page_t m, vm_prot_t access, vm_prot_t prot) 3410 { 3411 pt_entry_t rw; 3412 3413 if (!(prot & VM_PROT_WRITE)) 3414 rw = PTE_V | PTE_RO; 3415 else if ((m->oflags & VPO_UNMANAGED) == 0) { 3416 if ((access & VM_PROT_WRITE) != 0) 3417 rw = PTE_V | PTE_D; 3418 else 3419 rw = PTE_V; 3420 } else 3421 /* Needn't emulate a modified bit for unmanaged pages. */ 3422 rw = PTE_V | PTE_D; 3423 return (rw); 3424 } 3425 3426 /* 3427 * pmap_emulate_modified : do dirty bit emulation 3428 * 3429 * On SMP, update just the local TLB, other CPUs will update their 3430 * TLBs from PTE lazily, if they get the exception. 3431 * Returns 0 in case of sucess, 1 if the page is read only and we 3432 * need to fault. 3433 */ 3434 int 3435 pmap_emulate_modified(pmap_t pmap, vm_offset_t va) 3436 { 3437 pt_entry_t *pte; 3438 3439 PMAP_LOCK(pmap); 3440 pte = pmap_pte(pmap, va); 3441 if (pte == NULL) 3442 panic("pmap_emulate_modified: can't find PTE"); 3443 #ifdef SMP 3444 /* It is possible that some other CPU changed m-bit */ 3445 if (!pte_test(pte, PTE_V) || pte_test(pte, PTE_D)) { 3446 tlb_update(pmap, va, *pte); 3447 PMAP_UNLOCK(pmap); 3448 return (0); 3449 } 3450 #else 3451 if (!pte_test(pte, PTE_V) || pte_test(pte, PTE_D)) 3452 panic("pmap_emulate_modified: invalid pte"); 3453 #endif 3454 if (pte_test(pte, PTE_RO)) { 3455 PMAP_UNLOCK(pmap); 3456 return (1); 3457 } 3458 pte_set(pte, PTE_D); 3459 tlb_update(pmap, va, *pte); 3460 if (!pte_test(pte, PTE_MANAGED)) 3461 panic("pmap_emulate_modified: unmanaged page"); 3462 PMAP_UNLOCK(pmap); 3463 return (0); 3464 } 3465 3466 /* 3467 * Routine: pmap_kextract 3468 * Function: 3469 * Extract the physical page address associated 3470 * virtual address. 3471 */ 3472 vm_paddr_t 3473 pmap_kextract(vm_offset_t va) 3474 { 3475 int mapped; 3476 3477 /* 3478 * First, the direct-mapped regions. 3479 */ 3480 #if defined(__mips_n64) 3481 if (va >= MIPS_XKPHYS_START && va < MIPS_XKPHYS_END) 3482 return (MIPS_XKPHYS_TO_PHYS(va)); 3483 #endif 3484 if (va >= MIPS_KSEG0_START && va < MIPS_KSEG0_END) 3485 return (MIPS_KSEG0_TO_PHYS(va)); 3486 3487 if (va >= MIPS_KSEG1_START && va < MIPS_KSEG1_END) 3488 return (MIPS_KSEG1_TO_PHYS(va)); 3489 3490 /* 3491 * User virtual addresses. 3492 */ 3493 if (va < VM_MAXUSER_ADDRESS) { 3494 pt_entry_t *ptep; 3495 3496 if (curproc && curproc->p_vmspace) { 3497 ptep = pmap_pte(&curproc->p_vmspace->vm_pmap, va); 3498 if (ptep) { 3499 return (TLBLO_PTE_TO_PA(*ptep) | 3500 (va & PAGE_MASK)); 3501 } 3502 return (0); 3503 } 3504 } 3505 3506 /* 3507 * Should be kernel virtual here, otherwise fail 3508 */ 3509 mapped = (va >= MIPS_KSEG2_START || va < MIPS_KSEG2_END); 3510 #if defined(__mips_n64) 3511 mapped = mapped || (va >= MIPS_XKSEG_START || va < MIPS_XKSEG_END); 3512 #endif 3513 /* 3514 * Kernel virtual. 3515 */ 3516 3517 if (mapped) { 3518 pt_entry_t *ptep; 3519 3520 /* Is the kernel pmap initialized? */ 3521 if (!CPU_EMPTY(&kernel_pmap->pm_active)) { 3522 /* It's inside the virtual address range */ 3523 ptep = pmap_pte(kernel_pmap, va); 3524 if (ptep) { 3525 return (TLBLO_PTE_TO_PA(*ptep) | 3526 (va & PAGE_MASK)); 3527 } 3528 } 3529 return (0); 3530 } 3531 3532 panic("%s for unknown address space %p.", __func__, (void *)va); 3533 } 3534 3535 3536 void 3537 pmap_flush_pvcache(vm_page_t m) 3538 { 3539 pv_entry_t pv; 3540 3541 if (m != NULL) { 3542 for (pv = TAILQ_FIRST(&m->md.pv_list); pv; 3543 pv = TAILQ_NEXT(pv, pv_list)) { 3544 mips_dcache_wbinv_range_index(pv->pv_va, PAGE_SIZE); 3545 } 3546 } 3547 } 3548 3549 void 3550 pmap_page_set_memattr(vm_page_t m, vm_memattr_t ma) 3551 { 3552 3553 /* 3554 * It appears that this function can only be called before any mappings 3555 * for the page are established. If this ever changes, this code will 3556 * need to walk the pv_list and make each of the existing mappings 3557 * uncacheable, being careful to sync caches and PTEs (and maybe 3558 * invalidate TLB?) for any current mapping it modifies. 3559 */ 3560 if (TAILQ_FIRST(&m->md.pv_list) != NULL) 3561 panic("Can't change memattr on page with existing mappings"); 3562 3563 /* 3564 * The only memattr we support is UNCACHEABLE, translate the (semi-)MI 3565 * representation of that into our internal flag in the page MD struct. 3566 */ 3567 if (ma == VM_MEMATTR_UNCACHEABLE) 3568 m->md.pv_flags |= PV_MEMATTR_UNCACHEABLE; 3569 else 3570 m->md.pv_flags &= ~PV_MEMATTR_UNCACHEABLE; 3571 }
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