psraccess.S

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    1 /*      $OpenBSD$ */
    2 /*
    3  * Copyright (c) 2001 Opsycon AB  (www.opsycon.se / www.opsycon.com)
    4  *
    5  * Redistribution and use in source and binary forms, with or without
    6  * modification, are permitted provided that the following conditions
    7  * are met:
    8  * 1. Redistributions of source code must retain the above copyright
    9  *    notice, this list of conditions and the following disclaimer.
   10  * 2. Redistributions in binary form must reproduce the above copyright
   11  *    notice, this list of conditions and the following disclaimer in the
   12  *    documentation and/or other materials provided with the distribution.
   13  * 3. All advertising materials mentioning features or use of this software
   14  *    must display the following acknowledgement:
   15  *      This product includes software developed by Opsycon AB, Sweden.
   16  * 4. The name of the author may not be used to endorse or promote products
   17  *    derived from this software without specific prior written permission.
   18  *
   19  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
   20  * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
   21  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   22  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
   23  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
   24  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
   25  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
   26  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
   27  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   28  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   29  * SUCH DAMAGE.
   30  *
   31  *      JNPR: psraccess.S,v 1.4.2.1 2007/09/10 10:36:50 girish
   32  * $FreeBSD: releng/8.0/sys/mips/mips/psraccess.S 178172 2008-04-13 07:27:37Z imp $
   33  *
   34  */
   35 
   36 /*
   37  *  Low level code to manage processor specific registers.
   38  */
   39 
   40 #include <machine/asm.h>
   41 #include <machine/cpu.h>
   42 #include <machine/regnum.h>
   43 
   44 #include "assym.s"
   45 
   46 /*
   47  * FREEBSD_DEVELOPERS_FIXME
   48  * Some MIPS CPU may need delays using nops between executing CP0 Instructions
   49  */
   50 #define MIPS_CPU_NOP_DELAY      nop;nop;nop;nop;nop;nop;nop;nop;nop;nop;
   51 
   52         .set    noreorder               # Noreorder is default style!
   53 
   54 /*
   55  * Set/clear software interrupt.
   56  */
   57 
   58 LEAF(setsoftintr0)
   59         mfc0    v0, COP_0_CAUSE_REG     # read cause register
   60         nop
   61         or      v0, v0, SOFT_INT_MASK_0 # set soft clock interrupt
   62         mtc0    v0, COP_0_CAUSE_REG     # save it
   63         j       ra
   64         nop
   65 END(setsoftintr0)
   66 
   67 LEAF(clearsoftintr0)
   68         mfc0    v0, COP_0_CAUSE_REG     # read cause register
   69         nop
   70         and     v0, v0, ~SOFT_INT_MASK_0  # clear soft clock interrupt
   71         mtc0    v0, COP_0_CAUSE_REG     # save it
   72         j       ra
   73         nop
   74 END(clearsoftintr0)
   75 
   76 LEAF(setsoftintr1)
   77         mfc0    v0, COP_0_CAUSE_REG     # read cause register
   78         nop
   79         or      v0, v0, SOFT_INT_MASK_1 # set soft net interrupt
   80         mtc0    v0, COP_0_CAUSE_REG     # save it
   81         j       ra
   82         nop
   83 END(setsoftintr1)
   84 
   85 LEAF(clearsoftintr1)
   86         mfc0    v0, COP_0_CAUSE_REG     # read cause register
   87         nop
   88         and     v0, v0, ~SOFT_INT_MASK_1  # clear soft net interrupt
   89         mtc0    v0, COP_0_CAUSE_REG     # save it
   90         j       ra
   91         nop
   92 END(clearsoftintr1)
   93 
   94 /*
   95  * Set/change interrupt priority routines.
   96  * These routines return the previous state.
   97  */
   98 LEAF(restoreintr)
   99         mfc0    t0,COP_0_STATUS_REG
  100         and     t1,t0,SR_INT_ENAB
  101         beq     a0,t1,1f
  102         xor     t0,SR_INT_ENAB
  103   
  104         .set    noreorder
  105 
  106         mtc0    t0,COP_0_STATUS_REG
  107         nop
  108         nop
  109         nop
  110         nop
  111 1:
  112         j       ra
  113         nop
  114 END(restoreintr)
  115 
  116 /*
  117  * Set/change interrupt priority routines.
  118  * These routines return the previous state.
  119  */
  120  
  121 LEAF(enableintr)
  122 #ifdef TARGET_OCTEON
  123         .set mips64r2
  124         ei     v0
  125         and     v0, SR_INT_ENAB         # return old interrupt enable bit
  126         .set    mips0
  127 #else           
  128         mfc0    v0, COP_0_STATUS_REG    # read status register
  129         nop
  130         or      v1, v0, SR_INT_ENAB
  131         mtc0    v1, COP_0_STATUS_REG    # enable all interrupts
  132         and     v0, SR_INT_ENAB         # return old interrupt enable
  133 #endif  
  134         j       ra
  135         nop
  136 END(enableintr)
  137 
  138 
  139 LEAF(disableintr)
  140 #ifdef TARGET_OCTEON
  141         .set mips64r2
  142         di     v0
  143         and     v0, SR_INT_ENAB         # return old interrupt enable bit
  144         .set    mips0
  145 #else           
  146         mfc0    v0, COP_0_STATUS_REG    # read status register
  147         nop
  148         and     v1, v0, ~SR_INT_ENAB
  149         mtc0    v1, COP_0_STATUS_REG    # disable all interrupts
  150         MIPS_CPU_NOP_DELAY
  151         and     v0, SR_INT_ENAB         # return old interrupt enable
  152 #endif  
  153         j       ra
  154         nop
  155 END(disableintr)
  156 
  157 LEAF(set_intr_mask)
  158         li      t0, SR_INT_MASK         # 1 means masked so invert.
  159         not     a0, a0                  # 1 means masked so invert.
  160         and     a0, t0                  # 1 means masked so invert.
  161         mfc0    v0, COP_0_STATUS_REG
  162         li      v1, ~SR_INT_MASK
  163         and     v1, v0
  164         or      v1, a0
  165         mtc0    v1, COP_0_STATUS_REG
  166         MIPS_CPU_NOP_DELAY
  167         move    v0, v1
  168         jr      ra
  169         nop
  170 
  171 END(set_intr_mask)
  172 
  173 LEAF(get_intr_mask)
  174         li      a0, 0
  175         mfc0    v0, COP_0_STATUS_REG
  176         li      v1, SR_INT_MASK
  177         and     v0, v1
  178         or      v0, a0
  179         jr      ra
  180         nop
  181 
  182 END(get_intr_mask)
  183 
  184 /*
  185  * u_int32_t mips_cp0_config1_read(void)
  186  *
  187  *      Return the current value of the CP0 Config (Select 1) register.
  188  */
  189 LEAF(mips_cp0_config1_read)
  190         .set    push
  191         .set    mips32
  192         mfc0    v0, COP_0_CONFIG, 1
  193         j       ra
  194         nop
  195         .set    pop
  196 END(mips_cp0_config1_read)

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