tick.c

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    1 /*-
    2  * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
    3  *
    4  * Copyright (c) 2006-2007 Bruce M. Simpson.
    5  * Copyright (c) 2003-2004 Juli Mallett.
    6  * All rights reserved.
    7  *
    8  * Redistribution and use in source and binary forms, with or without
    9  * modification, are permitted provided that the following conditions
   10  * are met:
   11  * 1. Redistributions of source code must retain the above copyright
   12  *      notice, this list of conditions and the following disclaimer.
   13  * 2. Redistributions in binary form must reproduce the above copyright
   14  *      notice, this list of conditions and the following disclaimer in the
   15  *      documentation and/or other materials provided with the distribution.
   16  *
   17  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
   18  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   19  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   20  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
   21  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
   22  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
   23  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
   24  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
   25  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   26  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   27  * SUCH DAMAGE.
   28  */
   29 
   30 /*
   31  * Simple driver for the 32-bit interval counter built in to all
   32  * MIPS32 CPUs.
   33  */
   34 
   35 #include <sys/cdefs.h>
   36 __FBSDID("$FreeBSD: releng/12.0/sys/mips/mips/tick.c 336007 2018-07-05 17:13:37Z andrew $");
   37 
   38 #include <sys/param.h>
   39 #include <sys/systm.h>
   40 #include <sys/sysctl.h>
   41 #include <sys/bus.h>
   42 #include <sys/kernel.h>
   43 #include <sys/module.h>
   44 #include <sys/rman.h>
   45 #include <sys/power.h>
   46 #include <sys/smp.h>
   47 #include <sys/time.h>
   48 #include <sys/timeet.h>
   49 #include <sys/timetc.h>
   50 
   51 #include <machine/hwfunc.h>
   52 #include <machine/clock.h>
   53 #include <machine/locore.h>
   54 #include <machine/md_var.h>
   55 
   56 #ifdef INTRNG
   57 #include <machine/intr.h>
   58 #endif
   59 
   60 uint64_t counter_freq;
   61 
   62 struct timecounter *platform_timecounter;
   63 
   64 DPCPU_DEFINE_STATIC(uint32_t, cycles_per_tick);
   65 static uint32_t cycles_per_usec;
   66 
   67 DPCPU_DEFINE_STATIC(volatile uint32_t, counter_upper);
   68 DPCPU_DEFINE_STATIC(volatile uint32_t, counter_lower_last);
   69 DPCPU_DEFINE_STATIC(uint32_t, compare_ticks);
   70 DPCPU_DEFINE_STATIC(uint32_t, lost_ticks);
   71 
   72 struct clock_softc {
   73         int intr_rid;
   74         struct resource *intr_res;
   75         void *intr_handler;
   76         struct timecounter tc;
   77         struct eventtimer et;
   78 };
   79 static struct clock_softc *softc;
   80 
   81 /*
   82  * Device methods
   83  */
   84 static int clock_probe(device_t);
   85 static void clock_identify(driver_t *, device_t);
   86 static int clock_attach(device_t);
   87 static unsigned counter_get_timecount(struct timecounter *tc);
   88 
   89 void 
   90 mips_timer_early_init(uint64_t clock_hz)
   91 {
   92         /* Initialize clock early so that we can use DELAY sooner */
   93         counter_freq = clock_hz;
   94         cycles_per_usec = (clock_hz / (1000 * 1000));
   95 }
   96 
   97 void
   98 platform_initclocks(void)
   99 {
  100 
  101         if (platform_timecounter != NULL)
  102                 tc_init(platform_timecounter);
  103 }
  104 
  105 static uint64_t
  106 tick_ticker(void)
  107 {
  108         uint64_t ret;
  109         uint32_t ticktock;
  110         uint32_t t_lower_last, t_upper;
  111 
  112         /*
  113          * Disable preemption because we are working with cpu specific data.
  114          */
  115         critical_enter();
  116 
  117         /*
  118          * Note that even though preemption is disabled, interrupts are
  119          * still enabled. In particular there is a race with clock_intr()
  120          * reading the values of 'counter_upper' and 'counter_lower_last'.
  121          *
  122          * XXX this depends on clock_intr() being executed periodically
  123          * so that 'counter_upper' and 'counter_lower_last' are not stale.
  124          */
  125         do {
  126                 t_upper = DPCPU_GET(counter_upper);
  127                 t_lower_last = DPCPU_GET(counter_lower_last);
  128         } while (t_upper != DPCPU_GET(counter_upper));
  129 
  130         ticktock = mips_rd_count();
  131 
  132         critical_exit();
  133 
  134         /* COUNT register wrapped around */
  135         if (ticktock < t_lower_last)
  136                 t_upper++;
  137 
  138         ret = ((uint64_t)t_upper << 32) | ticktock;
  139         return (ret);
  140 }
  141 
  142 void
  143 mips_timer_init_params(uint64_t platform_counter_freq, int double_count)
  144 {
  145 
  146         /*
  147          * XXX: Do not use printf here: uart code 8250 may use DELAY so this
  148          * function should  be called before cninit.
  149          */
  150         counter_freq = platform_counter_freq;
  151         /*
  152          * XXX: Some MIPS32 cores update the Count register only every two
  153          * pipeline cycles.
  154          * We know this because of status registers in CP0, make it automatic.
  155          */
  156         if (double_count != 0)
  157                 counter_freq /= 2;
  158 
  159         cycles_per_usec = counter_freq / (1 * 1000 * 1000);
  160         set_cputicker(tick_ticker, counter_freq, 1);
  161 }
  162 
  163 static int
  164 sysctl_machdep_counter_freq(SYSCTL_HANDLER_ARGS)
  165 {
  166         int error;
  167         uint64_t freq;
  168 
  169         if (softc == NULL)
  170                 return (EOPNOTSUPP);
  171         freq = counter_freq;
  172         error = sysctl_handle_64(oidp, &freq, sizeof(freq), req);
  173         if (error == 0 && req->newptr != NULL) {
  174                 counter_freq = freq;
  175                 softc->et.et_frequency = counter_freq;
  176                 softc->tc.tc_frequency = counter_freq;
  177         }
  178         return (error);
  179 }
  180 
  181 SYSCTL_PROC(_machdep, OID_AUTO, counter_freq, CTLTYPE_U64 | CTLFLAG_RW,
  182     NULL, 0, sysctl_machdep_counter_freq, "QU",
  183     "Timecounter frequency in Hz");
  184 
  185 static unsigned
  186 counter_get_timecount(struct timecounter *tc)
  187 {
  188 
  189         return (mips_rd_count());
  190 }
  191 
  192 /*
  193  * Wait for about n microseconds (at least!).
  194  */
  195 void
  196 DELAY(int n)
  197 {
  198         uint32_t cur, last, delta, usecs;
  199 
  200         TSENTER();
  201         /*
  202          * This works by polling the timer and counting the number of
  203          * microseconds that go by.
  204          */
  205         last = mips_rd_count();
  206         delta = usecs = 0;
  207 
  208         while (n > usecs) {
  209                 cur = mips_rd_count();
  210 
  211                 /* Check to see if the timer has wrapped around. */
  212                 if (cur < last)
  213                         delta += cur + (0xffffffff - last) + 1;
  214                 else
  215                         delta += cur - last;
  216 
  217                 last = cur;
  218 
  219                 if (delta >= cycles_per_usec) {
  220                         usecs += delta / cycles_per_usec;
  221                         delta %= cycles_per_usec;
  222                 }
  223         }
  224         TSEXIT();
  225 }
  226 
  227 static int
  228 clock_start(struct eventtimer *et, sbintime_t first, sbintime_t period)
  229 {
  230         uint32_t fdiv, div, next;
  231 
  232         if (period != 0) {
  233                 div = (et->et_frequency * period) >> 32;
  234         } else
  235                 div = 0;
  236         if (first != 0)
  237                 fdiv = (et->et_frequency * first) >> 32;
  238         else 
  239                 fdiv = div;
  240         DPCPU_SET(cycles_per_tick, div);
  241         next = mips_rd_count() + fdiv;
  242         DPCPU_SET(compare_ticks, next);
  243         mips_wr_compare(next);
  244         return (0);
  245 }
  246 
  247 static int
  248 clock_stop(struct eventtimer *et)
  249 {
  250 
  251         DPCPU_SET(cycles_per_tick, 0);
  252         mips_wr_compare(0xffffffff);
  253         return (0);
  254 }
  255 
  256 /*
  257  * Device section of file below
  258  */
  259 static int
  260 clock_intr(void *arg)
  261 {
  262         struct clock_softc *sc = (struct clock_softc *)arg;
  263         uint32_t cycles_per_tick;
  264         uint32_t count, compare_last, compare_next, lost_ticks;
  265 
  266         cycles_per_tick = DPCPU_GET(cycles_per_tick);
  267         /*
  268          * Set next clock edge.
  269          */
  270         count = mips_rd_count();
  271         compare_last = DPCPU_GET(compare_ticks);
  272         if (cycles_per_tick > 0) {
  273                 compare_next = count + cycles_per_tick;
  274                 DPCPU_SET(compare_ticks, compare_next);
  275                 mips_wr_compare(compare_next);
  276         } else  /* In one-shot mode timer should be stopped after the event. */
  277                 mips_wr_compare(0xffffffff);
  278 
  279         /* COUNT register wrapped around */
  280         if (count < DPCPU_GET(counter_lower_last)) {
  281                 DPCPU_SET(counter_upper, DPCPU_GET(counter_upper) + 1);
  282         }
  283         DPCPU_SET(counter_lower_last, count);
  284 
  285         if (cycles_per_tick > 0) {
  286 
  287                 /*
  288                  * Account for the "lost time" between when the timer interrupt
  289                  * fired and when 'clock_intr' actually started executing.
  290                  */
  291                 lost_ticks = DPCPU_GET(lost_ticks);
  292                 lost_ticks += count - compare_last;
  293         
  294                 /*
  295                  * If the COUNT and COMPARE registers are no longer in sync
  296                  * then make up some reasonable value for the 'lost_ticks'.
  297                  *
  298                  * This could happen, for e.g., after we resume normal
  299                  * operations after exiting the debugger.
  300                  */
  301                 if (lost_ticks > 2 * cycles_per_tick)
  302                         lost_ticks = cycles_per_tick;
  303 
  304                 while (lost_ticks >= cycles_per_tick) {
  305                         if (sc->et.et_active)
  306                                 sc->et.et_event_cb(&sc->et, sc->et.et_arg);
  307                         lost_ticks -= cycles_per_tick;
  308                 }
  309                 DPCPU_SET(lost_ticks, lost_ticks);
  310         }
  311         if (sc->et.et_active)
  312                 sc->et.et_event_cb(&sc->et, sc->et.et_arg);
  313         return (FILTER_HANDLED);
  314 }
  315 
  316 static int
  317 clock_probe(device_t dev)
  318 {
  319 
  320         device_set_desc(dev, "Generic MIPS32 ticker");
  321         return (BUS_PROBE_NOWILDCARD);
  322 }
  323 
  324 static void
  325 clock_identify(driver_t * drv, device_t parent)
  326 {
  327 
  328         BUS_ADD_CHILD(parent, 0, "clock", 0);
  329 }
  330 
  331 static int
  332 clock_attach(device_t dev)
  333 {
  334         struct clock_softc *sc;
  335 #ifndef INTRNG
  336         int error;
  337 #endif
  338 
  339         if (device_get_unit(dev) != 0)
  340                 panic("can't attach more clocks");
  341 
  342         softc = sc = device_get_softc(dev);
  343 #ifdef INTRNG
  344         cpu_establish_hardintr("clock", clock_intr, NULL, sc, 5, INTR_TYPE_CLK,
  345             NULL);
  346 #else
  347         sc->intr_rid = 0;
  348         sc->intr_res = bus_alloc_resource(dev,
  349             SYS_RES_IRQ, &sc->intr_rid, 5, 5, 1, RF_ACTIVE);
  350         if (sc->intr_res == NULL) {
  351                 device_printf(dev, "failed to allocate irq\n");
  352                 return (ENXIO);
  353         }
  354         error = bus_setup_intr(dev, sc->intr_res, INTR_TYPE_CLK,
  355             clock_intr, NULL, sc, &sc->intr_handler);
  356         if (error != 0) {
  357                 device_printf(dev, "bus_setup_intr returned %d\n", error);
  358                 return (error);
  359         }
  360 #endif
  361 
  362         sc->tc.tc_get_timecount = counter_get_timecount;
  363         sc->tc.tc_counter_mask = 0xffffffff;
  364         sc->tc.tc_frequency = counter_freq;
  365         sc->tc.tc_name = "MIPS32";
  366         sc->tc.tc_quality = 800;
  367         sc->tc.tc_priv = sc;
  368         tc_init(&sc->tc);
  369         sc->et.et_name = "MIPS32";
  370         sc->et.et_flags = ET_FLAGS_PERIODIC | ET_FLAGS_ONESHOT |
  371             ET_FLAGS_PERCPU;
  372         sc->et.et_quality = 800;
  373         sc->et.et_frequency = counter_freq;
  374         sc->et.et_min_period = 0x00004000LLU; /* To be safe. */
  375         sc->et.et_max_period = (0xfffffffeLLU << 32) / sc->et.et_frequency;
  376         sc->et.et_start = clock_start;
  377         sc->et.et_stop = clock_stop;
  378         sc->et.et_priv = sc;
  379         et_register(&sc->et);
  380         return (0);
  381 }
  382 
  383 static device_method_t clock_methods[] = {
  384         /* Device interface */
  385         DEVMETHOD(device_probe, clock_probe),
  386         DEVMETHOD(device_identify, clock_identify),
  387         DEVMETHOD(device_attach, clock_attach),
  388         DEVMETHOD(device_detach, bus_generic_detach),
  389         DEVMETHOD(device_shutdown, bus_generic_shutdown),
  390 
  391         {0, 0}
  392 };
  393 
  394 static driver_t clock_driver = {
  395         "clock",
  396         clock_methods,
  397         sizeof(struct clock_softc),
  398 };
  399 
  400 static devclass_t clock_devclass;
  401 
  402 DRIVER_MODULE(clock, nexus, clock_driver, clock_devclass, 0, 0);
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FreeBSD/Linux Kernel Cross Reference sys/mips/mips/tick.c

FreeBSD/Linux Kernel Cross Reference
sys/mips/mips/tick.c
