The Design and Implementation of the FreeBSD Operating System, Second Edition
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FreeBSD/Linux Kernel Cross Reference
sys/mips/mips/vm_machdep.c

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    1 /*-
    2  * Copyright (c) 1982, 1986 The Regents of the University of California.
    3  * Copyright (c) 1989, 1990 William Jolitz
    4  * Copyright (c) 1994 John Dyson
    5  * All rights reserved.
    6  *
    7  * This code is derived from software contributed to Berkeley by
    8  * the Systems Programming Group of the University of Utah Computer
    9  * Science Department, and William Jolitz.
   10  *
   11  * Redistribution and use in source and binary forms, with or without
   12  * modification, are permitted provided that the following conditions
   13  * are met:
   14  * 1. Redistributions of source code must retain the above copyright
   15  *    notice, this list of conditions and the following disclaimer.
   16  * 2. Redistributions in binary form must reproduce the above copyright
   17  *    notice, this list of conditions and the following disclaimer in the
   18  *    documentation and/or other materials provided with the distribution.
   19  * 4. Neither the name of the University nor the names of its contributors
   20  *    may be used to endorse or promote products derived from this software
   21  *    without specific prior written permission.
   22  *
   23  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
   24  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   25  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   26  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
   27  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
   28  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
   29  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
   30  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
   31  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   32  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   33  * SUCH DAMAGE.
   34  *
   35  *      from: @(#)vm_machdep.c  7.3 (Berkeley) 5/13/91
   36  *      Utah $Hdr: vm_machdep.c 1.16.1.1 89/06/23$
   37  *      from: src/sys/i386/i386/vm_machdep.c,v 1.132.2.2 2000/08/26 04:19:26 yokota
   38  *      JNPR: vm_machdep.c,v 1.8.2.2 2007/08/16 15:59:17 girish
   39  */
   40 
   41 #include <sys/cdefs.h>
   42 __FBSDID("$FreeBSD: releng/11.1/sys/mips/mips/vm_machdep.c 301961 2016-06-16 12:05:44Z kib $");
   43 
   44 #include "opt_compat.h"
   45 #include "opt_ddb.h"
   46 
   47 #include <sys/param.h>
   48 #include <sys/systm.h>
   49 #include <sys/malloc.h>
   50 #include <sys/proc.h>
   51 #include <sys/syscall.h>
   52 #include <sys/sysent.h>
   53 #include <sys/buf.h>
   54 #include <sys/vnode.h>
   55 #include <sys/vmmeter.h>
   56 #include <sys/kernel.h>
   57 #include <sys/sysctl.h>
   58 #include <sys/unistd.h>
   59 
   60 #include <machine/cache.h>
   61 #include <machine/clock.h>
   62 #include <machine/cpu.h>
   63 #include <machine/md_var.h>
   64 #include <machine/pcb.h>
   65 
   66 #include <vm/vm.h>
   67 #include <vm/vm_extern.h>
   68 #include <vm/pmap.h>
   69 #include <vm/vm_kern.h>
   70 #include <vm/vm_map.h>
   71 #include <vm/vm_page.h>
   72 #include <vm/vm_pageout.h>
   73 #include <vm/vm_param.h>
   74 #include <vm/uma.h>
   75 #include <vm/uma_int.h>
   76 
   77 #include <sys/user.h>
   78 #include <sys/mbuf.h>
   79 
   80 /* Duplicated from asm.h */
   81 #if defined(__mips_o32)
   82 #define SZREG   4
   83 #else
   84 #define SZREG   8
   85 #endif
   86 #if defined(__mips_o32) || defined(__mips_o64)
   87 #define CALLFRAME_SIZ   (SZREG * (4 + 2))
   88 #elif defined(__mips_n32) || defined(__mips_n64)
   89 #define CALLFRAME_SIZ   (SZREG * 4)
   90 #endif
   91 
   92 /*
   93  * Finish a fork operation, with process p2 nearly set up.
   94  * Copy and update the pcb, set up the stack so that the child
   95  * ready to run and return to user mode.
   96  */
   97 void
   98 cpu_fork(register struct thread *td1,register struct proc *p2,
   99     struct thread *td2,int flags)
  100 {
  101         register struct proc *p1;
  102         struct pcb *pcb2;
  103 
  104         p1 = td1->td_proc;
  105         if ((flags & RFPROC) == 0)
  106                 return;
  107         /* It is assumed that the vm_thread_alloc called
  108          * cpu_thread_alloc() before cpu_fork is called.
  109          */
  110 
  111         /* Point the pcb to the top of the stack */
  112         pcb2 = td2->td_pcb;
  113 
  114         /* Copy p1's pcb, note that in this case
  115          * our pcb also includes the td_frame being copied
  116          * too. The older mips2 code did an additional copy
  117          * of the td_frame, for us that's not needed any
  118          * longer (this copy does them both) 
  119          */
  120         bcopy(td1->td_pcb, pcb2, sizeof(*pcb2));
  121 
  122         /* Point mdproc and then copy over td1's contents
  123          * md_proc is empty for MIPS
  124          */
  125         td2->td_md.md_flags = td1->td_md.md_flags & MDTD_FPUSED;
  126 
  127         /*
  128          * Set up return-value registers as fork() libc stub expects.
  129          */
  130         td2->td_frame->v0 = 0;
  131         td2->td_frame->v1 = 1;
  132         td2->td_frame->a3 = 0;
  133 
  134         if (td1 == PCPU_GET(fpcurthread))
  135                 MipsSaveCurFPState(td1);
  136 
  137         pcb2->pcb_context[PCB_REG_RA] = (register_t)(intptr_t)fork_trampoline;
  138         /* Make sp 64-bit aligned */
  139         pcb2->pcb_context[PCB_REG_SP] = (register_t)(((vm_offset_t)td2->td_pcb &
  140             ~(sizeof(__int64_t) - 1)) - CALLFRAME_SIZ);
  141         pcb2->pcb_context[PCB_REG_S0] = (register_t)(intptr_t)fork_return;
  142         pcb2->pcb_context[PCB_REG_S1] = (register_t)(intptr_t)td2;
  143         pcb2->pcb_context[PCB_REG_S2] = (register_t)(intptr_t)td2->td_frame;
  144         pcb2->pcb_context[PCB_REG_SR] = mips_rd_status() &
  145             (MIPS_SR_KX | MIPS_SR_UX | MIPS_SR_INT_MASK);
  146         /*
  147          * FREEBSD_DEVELOPERS_FIXME:
  148          * Setup any other CPU-Specific registers (Not MIPS Standard)
  149          * and/or bits in other standard MIPS registers (if CPU-Specific)
  150          *  that are needed.
  151          */
  152 
  153         td2->td_md.md_tls = td1->td_md.md_tls;
  154         td2->td_md.md_saved_intr = MIPS_SR_INT_IE;
  155         td2->td_md.md_spinlock_count = 1;
  156 #ifdef CPU_CNMIPS
  157         if (td1->td_md.md_flags & MDTD_COP2USED) {
  158                 if (td1->td_md.md_cop2owner == COP2_OWNER_USERLAND) {
  159                         if (td1->td_md.md_ucop2)
  160                                 octeon_cop2_save(td1->td_md.md_ucop2);
  161                         else
  162                                 panic("cpu_fork: ucop2 is NULL but COP2 is enabled");
  163                 }
  164                 else {
  165                         if (td1->td_md.md_cop2)
  166                                 octeon_cop2_save(td1->td_md.md_cop2);
  167                         else
  168                                 panic("cpu_fork: cop2 is NULL but COP2 is enabled");
  169                 }
  170         }
  171 
  172         if (td1->td_md.md_cop2) {
  173                 td2->td_md.md_cop2 = octeon_cop2_alloc_ctx();
  174                 memcpy(td2->td_md.md_cop2, td1->td_md.md_cop2, 
  175                         sizeof(*td1->td_md.md_cop2));
  176         }
  177         if (td1->td_md.md_ucop2) {
  178                 td2->td_md.md_ucop2 = octeon_cop2_alloc_ctx();
  179                 memcpy(td2->td_md.md_ucop2, td1->td_md.md_ucop2, 
  180                         sizeof(*td1->td_md.md_ucop2));
  181         }
  182         td2->td_md.md_cop2owner = td1->td_md.md_cop2owner;
  183         pcb2->pcb_context[PCB_REG_SR] |= MIPS_SR_PX | MIPS_SR_UX | MIPS_SR_KX | MIPS_SR_SX;
  184         /* Clear COP2 bits for userland & kernel */
  185         td2->td_frame->sr &= ~MIPS_SR_COP_2_BIT;
  186         pcb2->pcb_context[PCB_REG_SR] &= ~MIPS_SR_COP_2_BIT;
  187 #endif
  188 }
  189 
  190 /*
  191  * Intercept the return address from a freshly forked process that has NOT
  192  * been scheduled yet.
  193  *
  194  * This is needed to make kernel threads stay in kernel mode.
  195  */
  196 void
  197 cpu_fork_kthread_handler(struct thread *td, void (*func)(void *), void *arg)
  198 {
  199         /*
  200          * Note that the trap frame follows the args, so the function
  201          * is really called like this:  func(arg, frame);
  202          */
  203         td->td_pcb->pcb_context[PCB_REG_S0] = (register_t)(intptr_t)func;
  204         td->td_pcb->pcb_context[PCB_REG_S1] = (register_t)(intptr_t)arg;
  205 }
  206 
  207 void
  208 cpu_exit(struct thread *td)
  209 {
  210 }
  211 
  212 void
  213 cpu_thread_exit(struct thread *td)
  214 {
  215 
  216         if (PCPU_GET(fpcurthread) == td)
  217                 PCPU_GET(fpcurthread) = (struct thread *)0;
  218 #ifdef  CPU_CNMIPS
  219         if (td->td_md.md_cop2)
  220                 memset(td->td_md.md_cop2, 0,
  221                         sizeof(*td->td_md.md_cop2));
  222         if (td->td_md.md_ucop2)
  223                 memset(td->td_md.md_ucop2, 0,
  224                         sizeof(*td->td_md.md_ucop2));
  225 #endif
  226 }
  227 
  228 void
  229 cpu_thread_free(struct thread *td)
  230 {
  231 #ifdef  CPU_CNMIPS
  232         if (td->td_md.md_cop2)
  233                 octeon_cop2_free_ctx(td->td_md.md_cop2);
  234         if (td->td_md.md_ucop2)
  235                 octeon_cop2_free_ctx(td->td_md.md_ucop2);
  236         td->td_md.md_cop2 = NULL;
  237         td->td_md.md_ucop2 = NULL;
  238 #endif
  239 }
  240 
  241 void
  242 cpu_thread_clean(struct thread *td)
  243 {
  244 }
  245 
  246 void
  247 cpu_thread_swapin(struct thread *td)
  248 {
  249         pt_entry_t *pte;
  250         int i;
  251 
  252         /*
  253          * The kstack may be at a different physical address now.
  254          * Cache the PTEs for the Kernel stack in the machine dependent
  255          * part of the thread struct so cpu_switch() can quickly map in
  256          * the pcb struct and kernel stack.
  257          */
  258         for (i = 0; i < KSTACK_PAGES; i++) {
  259                 pte = pmap_pte(kernel_pmap, td->td_kstack + i * PAGE_SIZE);
  260                 td->td_md.md_upte[i] = *pte & ~TLBLO_SWBITS_MASK;
  261         }
  262 }
  263 
  264 void
  265 cpu_thread_swapout(struct thread *td)
  266 {
  267 }
  268 
  269 void
  270 cpu_thread_alloc(struct thread *td)
  271 {
  272         pt_entry_t *pte;
  273         int i;
  274 
  275         KASSERT((td->td_kstack & (1 << PAGE_SHIFT)) == 0, ("kernel stack must be aligned."));
  276         td->td_pcb = (struct pcb *)(td->td_kstack +
  277             td->td_kstack_pages * PAGE_SIZE) - 1;
  278         td->td_frame = &td->td_pcb->pcb_regs;
  279 
  280         for (i = 0; i < KSTACK_PAGES; i++) {
  281                 pte = pmap_pte(kernel_pmap, td->td_kstack + i * PAGE_SIZE);
  282                 td->td_md.md_upte[i] = *pte & ~TLBLO_SWBITS_MASK;
  283         }
  284 }
  285 
  286 void
  287 cpu_set_syscall_retval(struct thread *td, int error)
  288 {
  289         struct trapframe *locr0 = td->td_frame;
  290         unsigned int code;
  291         int quad_syscall;
  292 
  293         code = locr0->v0;
  294         quad_syscall = 0;
  295 #if defined(__mips_n32) || defined(__mips_n64)
  296 #ifdef COMPAT_FREEBSD32
  297         if (code == SYS___syscall && SV_PROC_FLAG(td->td_proc, SV_ILP32))
  298                 quad_syscall = 1;
  299 #endif
  300 #else
  301         if (code == SYS___syscall)
  302                 quad_syscall = 1;
  303 #endif
  304 
  305         if (code == SYS_syscall)
  306                 code = locr0->a0;
  307         else if (code == SYS___syscall) {
  308                 if (quad_syscall)
  309                         code = _QUAD_LOWWORD ? locr0->a1 : locr0->a0;
  310                 else
  311                         code = locr0->a0;
  312         }
  313 
  314         switch (error) {
  315         case 0:
  316                 if (quad_syscall && code != SYS_lseek) {
  317                         /*
  318                          * System call invoked through the
  319                          * SYS___syscall interface but the
  320                          * return value is really just 32
  321                          * bits.
  322                          */
  323                         locr0->v0 = td->td_retval[0];
  324                         if (_QUAD_LOWWORD)
  325                                 locr0->v1 = td->td_retval[0];
  326                         locr0->a3 = 0;
  327                 } else {
  328                         locr0->v0 = td->td_retval[0];
  329                         locr0->v1 = td->td_retval[1];
  330                         locr0->a3 = 0;
  331                 }
  332                 break;
  333 
  334         case ERESTART:
  335                 locr0->pc = td->td_pcb->pcb_tpc;
  336                 break;
  337 
  338         case EJUSTRETURN:
  339                 break;  /* nothing to do */
  340 
  341         default:
  342                 if (quad_syscall && code != SYS_lseek) {
  343                         locr0->v0 = error;
  344                         if (_QUAD_LOWWORD)
  345                                 locr0->v1 = error;
  346                         locr0->a3 = 1;
  347                 } else {
  348                         locr0->v0 = error;
  349                         locr0->a3 = 1;
  350                 }
  351         }
  352 }
  353 
  354 /*
  355  * Initialize machine state, mostly pcb and trap frame for a new
  356  * thread, about to return to userspace.  Put enough state in the new
  357  * thread's PCB to get it to go back to the fork_return(), which
  358  * finalizes the thread state and handles peculiarities of the first
  359  * return to userspace for the new thread.
  360  */
  361 void
  362 cpu_copy_thread(struct thread *td, struct thread *td0)
  363 {
  364         struct pcb *pcb2;
  365 
  366         /* Point the pcb to the top of the stack. */
  367         pcb2 = td->td_pcb;
  368 
  369         /*
  370          * Copy the upcall pcb.  This loads kernel regs.
  371          * Those not loaded individually below get their default
  372          * values here.
  373          *
  374          * XXXKSE It might be a good idea to simply skip this as
  375          * the values of the other registers may be unimportant.
  376          * This would remove any requirement for knowing the KSE
  377          * at this time (see the matching comment below for
  378          * more analysis) (need a good safe default).
  379          * In MIPS, the trapframe is the first element of the PCB
  380          * and gets copied when we copy the PCB. No separate copy
  381          * is needed.
  382          */
  383         bcopy(td0->td_pcb, pcb2, sizeof(*pcb2));
  384 
  385         /*
  386          * Set registers for trampoline to user mode.
  387          */
  388 
  389         pcb2->pcb_context[PCB_REG_RA] = (register_t)(intptr_t)fork_trampoline;
  390         /* Make sp 64-bit aligned */
  391         pcb2->pcb_context[PCB_REG_SP] = (register_t)(((vm_offset_t)td->td_pcb &
  392             ~(sizeof(__int64_t) - 1)) - CALLFRAME_SIZ);
  393         pcb2->pcb_context[PCB_REG_S0] = (register_t)(intptr_t)fork_return;
  394         pcb2->pcb_context[PCB_REG_S1] = (register_t)(intptr_t)td;
  395         pcb2->pcb_context[PCB_REG_S2] = (register_t)(intptr_t)td->td_frame;
  396         /* Dont set IE bit in SR. sched lock release will take care of it */
  397         pcb2->pcb_context[PCB_REG_SR] = mips_rd_status() &
  398             (MIPS_SR_PX | MIPS_SR_KX | MIPS_SR_UX | MIPS_SR_INT_MASK);
  399 
  400         /*
  401          * FREEBSD_DEVELOPERS_FIXME:
  402          * Setup any other CPU-Specific registers (Not MIPS Standard)
  403          * that are needed.
  404          */
  405 
  406         /* Setup to release spin count in in fork_exit(). */
  407         td->td_md.md_spinlock_count = 1;
  408         td->td_md.md_saved_intr = MIPS_SR_INT_IE;
  409 #if 0
  410             /* Maybe we need to fix this? */
  411         td->td_md.md_saved_sr = ( (MIPS_SR_COP_2_BIT | MIPS_SR_COP_0_BIT) |
  412                                   (MIPS_SR_PX | MIPS_SR_UX | MIPS_SR_KX | MIPS_SR_SX) |
  413                                   (MIPS_SR_INT_IE | MIPS_HARD_INT_MASK));
  414 #endif
  415 }
  416 
  417 /*
  418  * Set that machine state for performing an upcall that starts
  419  * the entry function with the given argument.
  420  */
  421 void
  422 cpu_set_upcall(struct thread *td, void (*entry)(void *), void *arg,
  423     stack_t *stack)
  424 {
  425         struct trapframe *tf;
  426         register_t sp;
  427 
  428         /*
  429          * At the point where a function is called, sp must be 8
  430          * byte aligned[for compatibility with 64-bit CPUs]
  431          * in ``See MIPS Run'' by D. Sweetman, p. 269
  432          * align stack
  433          */
  434         sp = (((intptr_t)stack->ss_sp + stack->ss_size) & ~0x7) -
  435             CALLFRAME_SIZ;
  436 
  437         /*
  438          * Set the trap frame to point at the beginning of the uts
  439          * function.
  440          */
  441         tf = td->td_frame;
  442         bzero(tf, sizeof(struct trapframe));
  443         tf->sp = sp;
  444         tf->pc = (register_t)(intptr_t)entry;
  445         /* 
  446          * MIPS ABI requires T9 to be the same as PC 
  447          * in subroutine entry point
  448          */
  449         tf->t9 = (register_t)(intptr_t)entry; 
  450         tf->a0 = (register_t)(intptr_t)arg;
  451 
  452         /*
  453          * Keep interrupt mask
  454          */
  455         td->td_frame->sr = MIPS_SR_KSU_USER | MIPS_SR_EXL | MIPS_SR_INT_IE |
  456             (mips_rd_status() & MIPS_SR_INT_MASK);
  457 #if defined(__mips_n32) 
  458         td->td_frame->sr |= MIPS_SR_PX;
  459 #elif  defined(__mips_n64)
  460         td->td_frame->sr |= MIPS_SR_PX | MIPS_SR_UX | MIPS_SR_KX;
  461 #endif
  462 /*      tf->sr |= (ALL_INT_MASK & idle_mask) | SR_INT_ENAB; */
  463         /**XXX the above may now be wrong -- mips2 implements this as panic */
  464         /*
  465          * FREEBSD_DEVELOPERS_FIXME:
  466          * Setup any other CPU-Specific registers (Not MIPS Standard)
  467          * that are needed.
  468          */
  469 }
  470 
  471 /*
  472  * Implement the pre-zeroed page mechanism.
  473  * This routine is called from the idle loop.
  474  */
  475 
  476 #define ZIDLE_LO(v)     ((v) * 2 / 3)
  477 #define ZIDLE_HI(v)     ((v) * 4 / 5)
  478 
  479 /*
  480  * Software interrupt handler for queued VM system processing.
  481  */
  482 void
  483 swi_vm(void *dummy)
  484 {
  485 
  486         if (busdma_swi_pending)
  487                 busdma_swi();
  488 }
  489 
  490 int
  491 cpu_set_user_tls(struct thread *td, void *tls_base)
  492 {
  493 
  494         td->td_md.md_tls = (char*)tls_base;
  495 
  496         return (0);
  497 }
  498 
  499 #ifdef DDB
  500 #include <ddb/ddb.h>
  501 
  502 #define DB_PRINT_REG(ptr, regname)                      \
  503         db_printf("  %-12s %p\n", #regname, (void *)(intptr_t)((ptr)->regname))
  504 
  505 #define DB_PRINT_REG_ARRAY(ptr, arrname, regname)       \
  506         db_printf("  %-12s %p\n", #regname, (void *)(intptr_t)((ptr)->arrname[regname]))
  507 
  508 static void
  509 dump_trapframe(struct trapframe *trapframe)
  510 {
  511 
  512         db_printf("Trapframe at %p\n", trapframe);
  513 
  514         DB_PRINT_REG(trapframe, zero);
  515         DB_PRINT_REG(trapframe, ast);
  516         DB_PRINT_REG(trapframe, v0);
  517         DB_PRINT_REG(trapframe, v1);
  518         DB_PRINT_REG(trapframe, a0);
  519         DB_PRINT_REG(trapframe, a1);
  520         DB_PRINT_REG(trapframe, a2);
  521         DB_PRINT_REG(trapframe, a3);
  522 #if defined(__mips_n32) || defined(__mips_n64)
  523         DB_PRINT_REG(trapframe, a4);
  524         DB_PRINT_REG(trapframe, a5);
  525         DB_PRINT_REG(trapframe, a6);
  526         DB_PRINT_REG(trapframe, a7);
  527         DB_PRINT_REG(trapframe, t0);
  528         DB_PRINT_REG(trapframe, t1);
  529         DB_PRINT_REG(trapframe, t2);
  530         DB_PRINT_REG(trapframe, t3);
  531 #else
  532         DB_PRINT_REG(trapframe, t0);
  533         DB_PRINT_REG(trapframe, t1);
  534         DB_PRINT_REG(trapframe, t2);
  535         DB_PRINT_REG(trapframe, t3);
  536         DB_PRINT_REG(trapframe, t4);
  537         DB_PRINT_REG(trapframe, t5);
  538         DB_PRINT_REG(trapframe, t6);
  539         DB_PRINT_REG(trapframe, t7);
  540 #endif
  541         DB_PRINT_REG(trapframe, s0);
  542         DB_PRINT_REG(trapframe, s1);
  543         DB_PRINT_REG(trapframe, s2);
  544         DB_PRINT_REG(trapframe, s3);
  545         DB_PRINT_REG(trapframe, s4);
  546         DB_PRINT_REG(trapframe, s5);
  547         DB_PRINT_REG(trapframe, s6);
  548         DB_PRINT_REG(trapframe, s7);
  549         DB_PRINT_REG(trapframe, t8);
  550         DB_PRINT_REG(trapframe, t9);
  551         DB_PRINT_REG(trapframe, k0);
  552         DB_PRINT_REG(trapframe, k1);
  553         DB_PRINT_REG(trapframe, gp);
  554         DB_PRINT_REG(trapframe, sp);
  555         DB_PRINT_REG(trapframe, s8);
  556         DB_PRINT_REG(trapframe, ra);
  557         DB_PRINT_REG(trapframe, sr);
  558         DB_PRINT_REG(trapframe, mullo);
  559         DB_PRINT_REG(trapframe, mulhi);
  560         DB_PRINT_REG(trapframe, badvaddr);
  561         DB_PRINT_REG(trapframe, cause);
  562         DB_PRINT_REG(trapframe, pc);
  563 }
  564 
  565 DB_SHOW_COMMAND(pcb, ddb_dump_pcb)
  566 {
  567         struct thread *td;
  568         struct pcb *pcb;
  569         struct trapframe *trapframe;
  570 
  571         /* Determine which thread to examine. */
  572         if (have_addr)
  573                 td = db_lookup_thread(addr, true);
  574         else
  575                 td = curthread;
  576         
  577         pcb = td->td_pcb;
  578 
  579         db_printf("Thread %d at %p\n", td->td_tid, td);
  580 
  581         db_printf("PCB at %p\n", pcb);
  582 
  583         trapframe = &pcb->pcb_regs;
  584         dump_trapframe(trapframe);
  585 
  586         db_printf("PCB Context:\n");
  587         DB_PRINT_REG_ARRAY(pcb, pcb_context, PCB_REG_S0);
  588         DB_PRINT_REG_ARRAY(pcb, pcb_context, PCB_REG_S1);
  589         DB_PRINT_REG_ARRAY(pcb, pcb_context, PCB_REG_S2);
  590         DB_PRINT_REG_ARRAY(pcb, pcb_context, PCB_REG_S3);
  591         DB_PRINT_REG_ARRAY(pcb, pcb_context, PCB_REG_S4);
  592         DB_PRINT_REG_ARRAY(pcb, pcb_context, PCB_REG_S5);
  593         DB_PRINT_REG_ARRAY(pcb, pcb_context, PCB_REG_S6);
  594         DB_PRINT_REG_ARRAY(pcb, pcb_context, PCB_REG_S7);
  595         DB_PRINT_REG_ARRAY(pcb, pcb_context, PCB_REG_SP);
  596         DB_PRINT_REG_ARRAY(pcb, pcb_context, PCB_REG_S8);
  597         DB_PRINT_REG_ARRAY(pcb, pcb_context, PCB_REG_RA);
  598         DB_PRINT_REG_ARRAY(pcb, pcb_context, PCB_REG_SR);
  599         DB_PRINT_REG_ARRAY(pcb, pcb_context, PCB_REG_GP);
  600         DB_PRINT_REG_ARRAY(pcb, pcb_context, PCB_REG_PC);
  601 
  602         db_printf("PCB onfault = %p\n", pcb->pcb_onfault);
  603         db_printf("md_saved_intr = 0x%0lx\n", (long)td->td_md.md_saved_intr);
  604         db_printf("md_spinlock_count = %d\n", td->td_md.md_spinlock_count);
  605 
  606         if (td->td_frame != trapframe) {
  607                 db_printf("td->td_frame %p is not the same as pcb_regs %p\n",
  608                           td->td_frame, trapframe);
  609         }
  610 }
  611 
  612 /*
  613  * Dump the trapframe beginning at address specified by first argument.
  614  */
  615 DB_SHOW_COMMAND(trapframe, ddb_dump_trapframe)
  616 {
  617         
  618         if (!have_addr)
  619                 return;
  620 
  621         dump_trapframe((struct trapframe *)addr);
  622 }
  623 
  624 #endif  /* DDB */

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