Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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FreeBSD/Linux Kernel Cross Reference
sys/mips/nlm/hal/poe.h
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1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2003-2012 Broadcom Corporation 5 * All Rights Reserved 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in 15 * the documentation and/or other materials provided with the 16 * distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR 19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 20 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 25 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 26 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE 27 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN 28 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 29 * 30 * $FreeBSD$ 31 */ 32 33 #ifndef __NLM_POE_H__ 34 #define __NLM_POE_H__ 35 36 /** 37 * @file_name poe.h 38 * @author Netlogic Microsystems 39 * @brief Basic definitions of XLP Packet Order Engine 40 */ 41 42 /* POE specific registers */ 43 #define POE_CL0_ENQ_SPILL_BASE_LO 0x0 44 #define POE_CL1_ENQ_SPILL_BASE_LO 0x2 45 #define POE_CL2_ENQ_SPILL_BASE_LO 0x4 46 #define POE_CL3_ENQ_SPILL_BASE_LO 0x6 47 #define POE_CL4_ENQ_SPILL_BASE_LO 0x8 48 #define POE_CL5_ENQ_SPILL_BASE_LO 0xa 49 #define POE_CL6_ENQ_SPILL_BASE_LO 0xc 50 #define POE_CL7_ENQ_SPILL_BASE_LO 0xe 51 #define POE_CL0_ENQ_SPILL_BASE_HI 0x1 52 #define POE_CL1_ENQ_SPILL_BASE_HI 0x3 53 #define POE_CL2_ENQ_SPILL_BASE_HI 0x5 54 #define POE_CL3_ENQ_SPILL_BASE_HI 0x7 55 #define POE_CL4_ENQ_SPILL_BASE_HI 0x9 56 #define POE_CL5_ENQ_SPILL_BASE_HI 0xb 57 #define POE_CL6_ENQ_SPILL_BASE_HI 0xd 58 #define POE_CL7_ENQ_SPILL_BASE_HI 0xf 59 #define POE_CL0_DEQ_SPILL_BASE_LO 0x10 60 #define POE_CL1_DEQ_SPILL_BASE_LO 0x12 61 #define POE_CL2_DEQ_SPILL_BASE_LO 0x14 62 #define POE_CL3_DEQ_SPILL_BASE_LO 0x16 63 #define POE_CL4_DEQ_SPILL_BASE_LO 0x18 64 #define POE_CL5_DEQ_SPILL_BASE_LO 0x1a 65 #define POE_CL6_DEQ_SPILL_BASE_LO 0x1c 66 #define POE_CL7_DEQ_SPILL_BASE_LO 0x1e 67 #define POE_CL0_DEQ_SPILL_BASE_HI 0x11 68 #define POE_CL1_DEQ_SPILL_BASE_HI 0x13 69 #define POE_CL2_DEQ_SPILL_BASE_HI 0x15 70 #define POE_CL3_DEQ_SPILL_BASE_HI 0x17 71 #define POE_CL4_DEQ_SPILL_BASE_HI 0x19 72 #define POE_CL5_DEQ_SPILL_BASE_HI 0x1b 73 #define POE_CL6_DEQ_SPILL_BASE_HI 0x1d 74 #define POE_CL7_DEQ_SPILL_BASE_HI 0x1f 75 #define POE_MSG_STORAGE_BASE_ADDR_LO 0x20 76 #define POE_MSG_STORAGE_BASE_ADDR_HI 0x21 77 #define POE_FBP_BASE_ADDR_LO 0x22 78 #define POE_FBP_BASE_ADDR_HI 0x23 79 #define POE_CL0_ENQ_SPILL_MAXLINE_LO 0x24 80 #define POE_CL1_ENQ_SPILL_MAXLINE_LO 0x25 81 #define POE_CL2_ENQ_SPILL_MAXLINE_LO 0x26 82 #define POE_CL3_ENQ_SPILL_MAXLINE_LO 0x27 83 #define POE_CL4_ENQ_SPILL_MAXLINE_LO 0x28 84 #define POE_CL5_ENQ_SPILL_MAXLINE_LO 0x29 85 #define POE_CL6_ENQ_SPILL_MAXLINE_LO 0x2a 86 #define POE_CL7_ENQ_SPILL_MAXLINE_LO 0x2b 87 #define POE_CL0_ENQ_SPILL_MAXLINE_HI 0x2c 88 #define POE_CL1_ENQ_SPILL_MAXLINE_HI 0x2d 89 #define POE_CL2_ENQ_SPILL_MAXLINE_HI 0x2e 90 #define POE_CL3_ENQ_SPILL_MAXLINE_HI 0x2f 91 #define POE_CL4_ENQ_SPILL_MAXLINE_HI 0x30 92 #define POE_CL5_ENQ_SPILL_MAXLINE_HI 0x31 93 #define POE_CL6_ENQ_SPILL_MAXLINE_HI 0x32 94 #define POE_CL7_ENQ_SPILL_MAXLINE_HI 0x33 95 #define POE_MAX_FLOW_MSG0 0x40 96 #define POE_MAX_FLOW_MSG1 0x41 97 #define POE_MAX_FLOW_MSG2 0x42 98 #define POE_MAX_FLOW_MSG3 0x43 99 #define POE_MAX_FLOW_MSG4 0x44 100 #define POE_MAX_FLOW_MSG5 0x45 101 #define POE_MAX_FLOW_MSG6 0x46 102 #define POE_MAX_FLOW_MSG7 0x47 103 #define POE_MAX_MSG_CL0 0x48 104 #define POE_MAX_MSG_CL1 0x49 105 #define POE_MAX_MSG_CL2 0x4a 106 #define POE_MAX_MSG_CL3 0x4b 107 #define POE_MAX_MSG_CL4 0x4c 108 #define POE_MAX_MSG_CL5 0x4d 109 #define POE_MAX_MSG_CL6 0x4e 110 #define POE_MAX_MSG_CL7 0x4f 111 #define POE_MAX_LOC_BUF_STG_CL0 0x50 112 #define POE_MAX_LOC_BUF_STG_CL1 0x51 113 #define POE_MAX_LOC_BUF_STG_CL2 0x52 114 #define POE_MAX_LOC_BUF_STG_CL3 0x53 115 #define POE_MAX_LOC_BUF_STG_CL4 0x54 116 #define POE_MAX_LOC_BUF_STG_CL5 0x55 117 #define POE_MAX_LOC_BUF_STG_CL6 0x56 118 #define POE_MAX_LOC_BUF_STG_CL7 0x57 119 #define POE_ENQ_MSG_COUNT0_SIZE 0x58 120 #define POE_ENQ_MSG_COUNT1_SIZE 0x59 121 #define POE_ENQ_MSG_COUNT2_SIZE 0x5a 122 #define POE_ENQ_MSG_COUNT3_SIZE 0x5b 123 #define POE_ENQ_MSG_COUNT4_SIZE 0x5c 124 #define POE_ENQ_MSG_COUNT5_SIZE 0x5d 125 #define POE_ENQ_MSG_COUNT6_SIZE 0x5e 126 #define POE_ENQ_MSG_COUNT7_SIZE 0x5f 127 #define POE_ERR_MSG_DESCRIP_LO0 0x60 128 #define POE_ERR_MSG_DESCRIP_LO1 0x62 129 #define POE_ERR_MSG_DESCRIP_LO2 0x64 130 #define POE_ERR_MSG_DESCRIP_LO3 0x66 131 #define POE_ERR_MSG_DESCRIP_HI0 0x61 132 #define POE_ERR_MSG_DESCRIP_HI1 0x63 133 #define POE_ERR_MSG_DESCRIP_HI2 0x65 134 #define POE_ERR_MSG_DESCRIP_HI3 0x67 135 #define POE_OOO_MSG_CNT_LO 0x68 136 #define POE_IN_ORDER_MSG_CNT_LO 0x69 137 #define POE_LOC_BUF_STOR_CNT_LO 0x6a 138 #define POE_EXT_BUF_STOR_CNT_LO 0x6b 139 #define POE_LOC_BUF_ALLOC_CNT_LO 0x6c 140 #define POE_EXT_BUF_ALLOC_CNT_LO 0x6d 141 #define POE_OOO_MSG_CNT_HI 0x6e 142 #define POE_IN_ORDER_MSG_CNT_HI 0x6f 143 #define POE_LOC_BUF_STOR_CNT_HI 0x70 144 #define POE_EXT_BUF_STOR_CNT_HI 0x71 145 #define POE_LOC_BUF_ALLOC_CNT_HI 0x72 146 #define POE_EXT_BUF_ALLOC_CNT_HI 0x73 147 #define POE_MODE_ERR_FLOW_ID 0x74 148 #define POE_STATISTICS_ENABLE 0x75 149 #define POE_MAX_SIZE_FLOW 0x76 150 #define POE_MAX_SIZE 0x77 151 #define POE_FBP_SP 0x78 152 #define POE_FBP_SP_EN 0x79 153 #define POE_LOC_ALLOC_EN 0x7a 154 #define POE_EXT_ALLOC_EN 0x7b 155 #define POE_DISTR_0_DROP_CNT 0xc0 156 #define POE_DISTR_1_DROP_CNT 0xc1 157 #define POE_DISTR_2_DROP_CNT 0xc2 158 #define POE_DISTR_3_DROP_CNT 0xc3 159 #define POE_DISTR_4_DROP_CNT 0xc4 160 #define POE_DISTR_5_DROP_CNT 0xc5 161 #define POE_DISTR_6_DROP_CNT 0xc6 162 #define POE_DISTR_7_DROP_CNT 0xc7 163 #define POE_DISTR_8_DROP_CNT 0xc8 164 #define POE_DISTR_9_DROP_CNT 0xc9 165 #define POE_DISTR_10_DROP_CNT 0xca 166 #define POE_DISTR_11_DROP_CNT 0xcb 167 #define POE_DISTR_12_DROP_CNT 0xcc 168 #define POE_DISTR_13_DROP_CNT 0xcd 169 #define POE_DISTR_14_DROP_CNT 0xce 170 #define POE_DISTR_15_DROP_CNT 0xcf 171 #define POE_CLASS_0_DROP_CNT 0xd0 172 #define POE_CLASS_1_DROP_CNT 0xd1 173 #define POE_CLASS_2_DROP_CNT 0xd2 174 #define POE_CLASS_3_DROP_CNT 0xd3 175 #define POE_CLASS_4_DROP_CNT 0xd4 176 #define POE_CLASS_5_DROP_CNT 0xd5 177 #define POE_CLASS_6_DROP_CNT 0xd6 178 #define POE_CLASS_7_DROP_CNT 0xd7 179 #define POE_DISTR_C0_DROP_CNT 0xd8 180 #define POE_DISTR_C1_DROP_CNT 0xd9 181 #define POE_DISTR_C2_DROP_CNT 0xda 182 #define POE_DISTR_C3_DROP_CNT 0xdb 183 #define POE_DISTR_C4_DROP_CNT 0xdc 184 #define POE_DISTR_C5_DROP_CNT 0xdd 185 #define POE_DISTR_C6_DROP_CNT 0xde 186 #define POE_DISTR_C7_DROP_CNT 0xdf 187 #define POE_CPU_DROP_CNT 0xe0 188 #define POE_MAX_FLOW_DROP_CNT 0xe1 189 #define POE_INTERRUPT_VEC 0x140 190 #define POE_INTERRUPT_MASK 0x141 191 #define POE_FATALERR_MASK 0x142 192 #define POE_IDI_CFG 0x143 193 #define POE_TIMEOUT_VALUE 0x144 194 #define POE_CACHE_ALLOC_EN 0x145 195 #define POE_FBP_ECC_ERR_CNT 0x146 196 #define POE_MSG_STRG_ECC_ERR_CNT 0x147 197 #define POE_FID_INFO_ECC_ERR_CNT 0x148 198 #define POE_MSG_INFO_ECC_ERR_CNT 0x149 199 #define POE_LL_ECC_ERR_CNT 0x14a 200 #define POE_SIZE_ECC_ERR_CNT 0x14b 201 #define POE_FMN_TXCR_ECC_ERR_CNT 0x14c 202 #define POE_ENQ_INSPIL_ECC_ERR_CNT 0x14d 203 #define POE_ENQ_OUTSPIL_ECC_ERR_CNT 0x14e 204 #define POE_DEQ_OUTSPIL_ECC_ERR_CNT 0x14f 205 #define POE_ENQ_MSG_SENT 0x150 206 #define POE_ENQ_MSG_CNT 0x151 207 #define POE_FID_RDATA 0x152 208 #define POE_FID_WDATA 0x153 209 #define POE_FID_CMD 0x154 210 #define POE_FID_ADDR 0x155 211 #define POE_MSG_INFO_CMD 0x156 212 #define POE_MSG_INFO_ADDR 0x157 213 #define POE_MSG_INFO_RDATA 0x158 214 #define POE_LL_CMD 0x159 215 #define POE_LL_ADDR 0x15a 216 #define POE_LL_RDATA 0x15b 217 #define POE_MSG_STG_CMD 0x15c 218 #define POE_MSG_STG_ADDR 0x15d 219 #define POE_MSG_STG_RDATA 0x15e 220 #define POE_DISTR_THRESHOLD_0 0x1c0 221 #define POE_DISTR_THRESHOLD_1 0x1c1 222 #define POE_DISTR_THRESHOLD_2 0x1c2 223 #define POE_DISTR_THRESHOLD_3 0x1c3 224 #define POE_DISTR_THRESHOLD_4 0x1c4 225 #define POE_DISTR_THRESHOLD(i) (0x1c0 + (i)) 226 #define POE_DISTR_EN 0x1c5 227 #define POE_ENQ_SPILL_THOLD 0x1c8 228 #define POE_DEQ_SPILL_THOLD 0x1c9 229 #define POE_DEQ_SPILL_TIMER 0x1ca 230 #define POE_DISTR_CLASS_DROP_EN 0x1cb 231 #define POE_DISTR_VEC_DROP_EN 0x1cc 232 #define POE_DISTR_DROP_TIMER 0x1cd 233 #define POE_ERROR_LOG_W0 0x1ce 234 #define POE_ERROR_LOG_W1 0x1cf 235 #define POE_ERROR_LOG_W2 0x1d0 236 #define POE_ERR_INJ_CTRL0 0x1d1 237 #define POE_TX_TIMER 0x1d4 238 239 #define NUM_DIST_VEC 16 240 #define NUM_WORDS_PER_DV 16 241 #define MAX_DV_TBL_ENTRIES (NUM_DIST_VEC * NUM_WORDS_PER_DV) 242 #define POE_DIST_THRESHOLD_VAL 0xa 243 244 /* 245 * POE distribution vectors 246 * 247 * Each vector is 512 bit with msb indicating vc 512 and lsb indicating vc 0 248 * 512-bit-vector is specified as 16 32-bit words. 249 * Left most word has the vc range 511-479 right most word has vc range 31 - 0 250 * Each word has the MSB select higer vc number and LSB select lower vc num 251 */ 252 #define POE_DISTVECT_BASE 0x100 253 #define POE_DISTVECT(vec) (POE_DISTVECT_BASE + 16 * (vec)) 254 #define POE_DISTVECT_OFFSET(node,cpu) (4 * (3 - (node)) + (3 - (cpu)/8)) 255 #define POE_DISTVECT_SHIFT(node,cpu) (((cpu) % 8 ) * 4) 256 257 #if !defined(LOCORE) && !defined(__ASSEMBLY__) 258 259 #define nlm_read_poe_reg(b, r) nlm_read_reg(b, r) 260 #define nlm_write_poe_reg(b, r, v) nlm_write_reg(b, r, v) 261 #define nlm_read_poedv_reg(b, r) nlm_read_reg_xkphys(b, r) 262 #define nlm_write_poedv_reg(b, r, v) nlm_write_reg_xkphys(b, r, v) 263 #define nlm_get_poe_pcibase(node) \ 264 nlm_pcicfg_base(XLP_IO_POE_OFFSET(node)) 265 #define nlm_get_poe_regbase(node) \ 266 (nlm_get_poe_pcibase(node) + XLP_IO_PCI_HDRSZ) 267 #define nlm_get_poedv_regbase(node) \ 268 nlm_xkphys_map_pcibar0(nlm_get_poe_pcibase(node)) 269 270 static __inline int 271 nlm_poe_max_flows(uint64_t poe_pcibase) 272 { 273 return (nlm_read_reg(poe_pcibase, XLP_PCI_DEVINFO_REG0)); 274 } 275 276 /* 277 * Helper function, calculate the distribution vector 278 * cm0, cm1, cm2, cm3 : CPU masks for nodes 0..3 279 * thr_vcmask: destination VCs for a thread 280 */ 281 static __inline void 282 nlm_calc_poe_distvec(uint32_t cm0, uint32_t cm1, uint32_t cm2, uint32_t cm3, 283 uint32_t thr_vcmask, uint32_t *distvec) 284 { 285 uint32_t cpumask = 0, val; 286 int i, cpu, node, startcpu, index; 287 288 thr_vcmask &= 0xf; 289 for (node = 0; node < XLP_MAX_NODES; node++) { 290 switch (node) { 291 case 0: cpumask = cm0; break; 292 case 1: cpumask = cm1; break; 293 case 2: cpumask = cm2; break; 294 case 3: cpumask = cm3; break; 295 } 296 297 for (i = 0; i < 4; i++) { 298 val = 0; 299 startcpu = 31 - i * 8; 300 for (cpu = startcpu; cpu >= startcpu - 7; cpu--) { 301 val <<= 4; 302 if (cpumask & (1U << cpu)) 303 val |= thr_vcmask; 304 } 305 index = POE_DISTVECT_OFFSET(node, startcpu); 306 distvec[index] = val; 307 } 308 } 309 } 310 311 static __inline int 312 nlm_write_poe_distvec(uint64_t poedv_base, int vec, uint32_t *distvec) 313 { 314 uint32_t reg; 315 int i; 316 317 if (vec < 0 || vec >= NUM_DIST_VEC) 318 return (-1); 319 320 for (i = 0; i < NUM_WORDS_PER_DV; i++) { 321 reg = POE_DISTVECT(vec) + i; 322 nlm_write_poedv_reg(poedv_base, reg, distvec[i]); 323 } 324 325 return (0); 326 } 327 328 static __inline void 329 nlm_config_poe(uint64_t poe_base, uint64_t poedv_base) 330 { 331 uint32_t zerodv[NUM_WORDS_PER_DV]; 332 int i; 333 334 /* First disable distribution vector logic */ 335 nlm_write_poe_reg(poe_base, POE_DISTR_EN, 0); 336 337 memset(zerodv, 0, sizeof(zerodv)); 338 for (i = 0; i < NUM_DIST_VEC; i++) 339 nlm_write_poe_distvec(poedv_base, i, zerodv); 340 341 /* set the threshold */ 342 for (i = 0; i < 5; i++) 343 nlm_write_poe_reg(poe_base, POE_DISTR_THRESHOLD(i), 344 POE_DIST_THRESHOLD_VAL); 345 346 nlm_write_poe_reg(poe_base, POE_DISTR_EN, 1); 347 348 /* always enable local message store */ 349 nlm_write_poe_reg(poe_base, POE_LOC_ALLOC_EN, 1); 350 351 nlm_write_poe_reg(poe_base, POE_TX_TIMER, 0x3); 352 } 353 #endif /* !(LOCORE) && !(__ASSEMBLY__) */ 354 #endif
Cache object: d871734570e84a0f023bb341ee3d77db
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