sys.h

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    1 /*-
    2  * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
    3  *
    4  * Copyright 2003-2011 Netlogic Microsystems (Netlogic). All rights
    5  * reserved.
    6  *
    7  * Redistribution and use in source and binary forms, with or without
    8  * modification, are permitted provided that the following conditions are
    9  * met:
   10  *
   11  * 1. Redistributions of source code must retain the above copyright
   12  *    notice, this list of conditions and the following disclaimer.
   13  * 2. Redistributions in binary form must reproduce the above copyright
   14  *    notice, this list of conditions and the following disclaimer in
   15  *    the documentation and/or other materials provided with the
   16  *    distribution.
   17  *
   18  * THIS SOFTWARE IS PROVIDED BY Netlogic Microsystems ``AS IS'' AND
   19  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   20  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
   21  * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE
   22  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
   23  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
   24  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
   25  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
   26  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
   27  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
   28  * THE POSSIBILITY OF SUCH DAMAGE.
   29  *
   30  * NETLOGIC_BSD
   31  * $FreeBSD$
   32  */
   33 
   34 #ifndef __NLM_HAL_SYS_H__
   35 #define __NLM_HAL_SYS_H__
   36 
   37 /**
   38 * @file_name sys.h
   39 * @author Netlogic Microsystems
   40 * @brief HAL for System configuration registers
   41 */
   42 #define SYS_CHIP_RESET                          0x00
   43 #define SYS_POWER_ON_RESET_CFG                  0x01
   44 #define SYS_EFUSE_DEVICE_CFG_STATUS0            0x02
   45 #define SYS_EFUSE_DEVICE_CFG_STATUS1            0x03
   46 #define SYS_EFUSE_DEVICE_CFG_STATUS2            0x04
   47 #define SYS_EFUSE_DEVICE_CFG3                   0x05
   48 #define SYS_EFUSE_DEVICE_CFG4                   0x06
   49 #define SYS_EFUSE_DEVICE_CFG5                   0x07
   50 #define SYS_EFUSE_DEVICE_CFG6                   0x08
   51 #define SYS_EFUSE_DEVICE_CFG7                   0x09
   52 #define SYS_PLL_CTRL                            0x0a
   53 #define SYS_CPU_RESET                           0x0b
   54 #define SYS_CPU_NONCOHERENT_MODE                0x0d
   55 #define SYS_CORE_DFS_DIS_CTRL                   0x0e
   56 #define SYS_CORE_DFS_RST_CTRL                   0x0f
   57 #define SYS_CORE_DFS_BYP_CTRL                   0x10
   58 #define SYS_CORE_DFS_PHA_CTRL                   0x11
   59 #define SYS_CORE_DFS_DIV_INC_CTRL               0x12
   60 #define SYS_CORE_DFS_DIV_DEC_CTRL               0x13
   61 #define SYS_CORE_DFS_DIV_VALUE                  0x14
   62 #define SYS_RESET                               0x15
   63 #define SYS_DFS_DIS_CTRL                        0x16
   64 #define SYS_DFS_RST_CTRL                        0x17
   65 #define SYS_DFS_BYP_CTRL                        0x18
   66 #define SYS_DFS_DIV_INC_CTRL                    0x19
   67 #define SYS_DFS_DIV_DEC_CTRL                    0x1a
   68 #define SYS_DFS_DIV_VALUE0                      0x1b
   69 #define SYS_DFS_DIV_VALUE1                      0x1c
   70 #define SYS_SENSE_AMP_DLY                       0x1d
   71 #define SYS_SOC_SENSE_AMP_DLY                   0x1e
   72 #define SYS_CTRL0                               0x1f
   73 #define SYS_CTRL1                               0x20
   74 #define SYS_TIMEOUT_BS1                         0x21
   75 #define SYS_BYTE_SWAP                           0x22
   76 #define SYS_VRM_VID                             0x23
   77 #define SYS_PWR_RAM_CMD                         0x24
   78 #define SYS_PWR_RAM_ADDR                        0x25
   79 #define SYS_PWR_RAM_DATA0                       0x26
   80 #define SYS_PWR_RAM_DATA1                       0x27
   81 #define SYS_PWR_RAM_DATA2                       0x28
   82 #define SYS_PWR_UCODE                           0x29
   83 #define SYS_CPU0_PWR_STATUS                     0x2a
   84 #define SYS_CPU1_PWR_STATUS                     0x2b
   85 #define SYS_CPU2_PWR_STATUS                     0x2c
   86 #define SYS_CPU3_PWR_STATUS                     0x2d
   87 #define SYS_CPU4_PWR_STATUS                     0x2e
   88 #define SYS_CPU5_PWR_STATUS                     0x2f
   89 #define SYS_CPU6_PWR_STATUS                     0x30
   90 #define SYS_CPU7_PWR_STATUS                     0x31
   91 #define SYS_STATUS                              0x32
   92 #define SYS_INT_POL                             0x33
   93 #define SYS_INT_TYPE                            0x34
   94 #define SYS_INT_STATUS                          0x35
   95 #define SYS_INT_MASK0                           0x36
   96 #define SYS_INT_MASK1                           0x37
   97 #define SYS_UCO_S_ECC                           0x38
   98 #define SYS_UCO_M_ECC                           0x39
   99 #define SYS_UCO_ADDR                            0x3a
  100 #define SYS_PLL_DFS_BYP_CTRL                    0x3a /* Bx stepping */
  101 #define SYS_UCO_INSTR                           0x3b
  102 #define SYS_MEM_BIST0                           0x3c
  103 #define SYS_MEM_BIST1                           0x3d
  104 #define SYS_PLL_DFS_DIV_VALUE                   0x3d /* Bx stepping */
  105 #define SYS_MEM_BIST2                           0x3e
  106 #define SYS_MEM_BIST3                           0x3f
  107 #define SYS_MEM_BIST4                           0x40
  108 #define SYS_MEM_BIST5                           0x41
  109 #define SYS_MEM_BIST6                           0x42
  110 #define SYS_MEM_BIST7                           0x43
  111 #define SYS_MEM_BIST8                           0x44
  112 #define SYS_MEM_BIST9                           0x45
  113 #define SYS_MEM_BIST10                          0x46
  114 #define SYS_MEM_BIST11                          0x47
  115 #define SYS_MEM_BIST12                          0x48
  116 #define SYS_SCRTCH0                             0x49
  117 #define SYS_SCRTCH1                             0x4a
  118 #define SYS_SCRTCH2                             0x4b
  119 #define SYS_SCRTCH3                             0x4c
  120 
  121 #if !defined(LOCORE) && !defined(__ASSEMBLY__)
  122 
  123 #define nlm_read_sys_reg(b, r)          nlm_read_reg(b, r)
  124 #define nlm_write_sys_reg(b, r, v)      nlm_write_reg(b, r, v)
  125 #define nlm_get_sys_pcibase(node) nlm_pcicfg_base(XLP_IO_SYS_OFFSET(node))
  126 #define nlm_get_sys_regbase(node) (nlm_get_sys_pcibase(node) + XLP_IO_PCI_HDRSZ)
  127 
  128 enum {
  129         /* Don't change order and it must start from zero */
  130         DFS_DEVICE_NAE = 0,
  131         DFS_DEVICE_SAE,
  132         DFS_DEVICE_RSA,
  133         DFS_DEVICE_DTRE,
  134         DFS_DEVICE_CMP,
  135         DFS_DEVICE_KBP,
  136         DFS_DEVICE_DMC,
  137         DFS_DEVICE_NAND,
  138         DFS_DEVICE_MMC,
  139         DFS_DEVICE_NOR,
  140         DFS_DEVICE_CORE,
  141         DFS_DEVICE_REGEX_SLOW,
  142         DFS_DEVICE_REGEX_FAST,
  143         DFS_DEVICE_SATA,
  144         INVALID_DFS_DEVICE = 0xFF
  145 };
  146 
  147 static __inline
  148 void nlm_sys_enable_block(uint64_t sys_base, int block)
  149 {
  150         uint32_t dfsdis, mask;
  151 
  152         mask = 1 << block;
  153         dfsdis = nlm_read_sys_reg(sys_base, SYS_DFS_DIS_CTRL);
  154         if ((dfsdis & mask) == 0)
  155                 return;                 /* already enabled, nothing to do */
  156         dfsdis &= ~mask;
  157         nlm_write_sys_reg(sys_base, SYS_DFS_DIS_CTRL, dfsdis);
  158 }
  159 
  160 #endif
  161 #endif

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FreeBSD/Linux Kernel Cross Reference sys/mips/nlm/hal/sys.h

FreeBSD/Linux Kernel Cross Reference
sys/mips/nlm/hal/sys.h