The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


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FreeBSD/Linux Kernel Cross Reference
sys/mips/nlm/mpreset.S

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    1 /*-
    2  * Copyright 2003-2011 Netlogic Microsystems (Netlogic). All rights
    3  * reserved.
    4  *
    5  * Redistribution and use in source and binary forms, with or without
    6  * modification, are permitted provided that the following conditions are
    7  * met:
    8  *
    9  * 1. Redistributions of source code must retain the above copyright
   10  *    notice, this list of conditions and the following disclaimer.
   11  * 2. Redistributions in binary form must reproduce the above copyright
   12  *    notice, this list of conditions and the following disclaimer in
   13  *    the documentation and/or other materials provided with the
   14  *    distribution.
   15  * 
   16  * THIS SOFTWARE IS PROVIDED BY Netlogic Microsystems ``AS IS'' AND
   17  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   18  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
   19  * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE 
   20  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
   21  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
   22  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
   23  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
   24  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
   25  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
   26  * THE POSSIBILITY OF SUCH DAMAGE.
   27  *
   28  * NETLOGIC_BSD
   29  * $FreeBSD: stable/9/sys/mips/nlm/mpreset.S 225394 2011-09-05 10:45:29Z jchandra $
   30  */
   31 
   32 #include <machine/asm.h>
   33 #include <machine/cpu.h>
   34 #include <machine/cpuregs.h>
   35 #include <mips/nlm/hal/iomap.h>
   36 #include <mips/nlm/hal/sys.h>
   37 #include <mips/nlm/hal/cpucontrol.h>
   38 
   39 #define SYS_REG_KSEG1(node, reg)        (0xa0000000 + XLP_DEFAULT_IO_BASE + \
   40                 XLP_IO_SYS_OFFSET(node)  + XLP_IO_PCI_HDRSZ + (reg) * 4)
   41 #include "assym.s"
   42 
   43         .text
   44         .set    noat
   45         .set    noreorder
   46         .set    mips64
   47 
   48 VECTOR(XLPResetEntry, unknown)
   49         mfc0    t0, MIPS_COP_0_STATUS
   50         li      t1, 0x80000
   51         and     t1, t0, t1
   52         bnez    t1, nmi_handler
   53         nop
   54 
   55 #ifdef SMP
   56         /* Reset entry for secordary cores */
   57         mfc0    t0, MIPS_COP_0_PRID, 1
   58         srl     t0, t0, 2               /* discard thread id */
   59         andi    t0, t0, 0x7             /* core id */
   60         li      t1, 1
   61         sll     t0, t1, t0
   62         nor     t0, t0, zero            /* mask with core id bit clear */
   63 
   64         /* clear CPU non-coherent bit */
   65         li      t2, SYS_REG_KSEG1(0, SYS_CPU_NONCOHERENT_MODE)
   66         lw      t1, 0(t2)
   67         and     t1, t1, t0
   68         sw      t1, 0(t2)
   69         lw      t1, 0(t2)       /* read-back ensures operation complete */
   70         sync
   71 
   72         dla     t2, mpentry
   73         jr      t2
   74         nop
   75 #endif
   76         nop
   77         /* NOT REACHED */
   78 VECTOR_END(XLPResetEntry)
   79 
   80 
   81         /* Not yet */
   82 nmi_handler:
   83         nop
   84         nop
   85         j       nmi_handler
   86 
   87 #ifdef SMP
   88         /*
   89          * Enable other threads in the core, called from thread 0
   90          * of the core
   91          */
   92 LEAF(xlp_enable_threads)
   93         /*
   94          * Save and restore callee saved registers of all ABIs
   95          * Enabling threads trashes the registers
   96          */
   97         dmtc0   sp, $4, 2       /* SP saved in UserLocal */
   98         ori     sp, sp, 0x7
   99         xori    sp, sp, 0x7     /* align 64 bit */
  100         addiu   sp, sp, -128
  101         mfc0    t1, MIPS_COP_0_STATUS
  102         sd      s0, 0(sp)
  103         sd      s1, 8(sp)
  104         sd      s2, 16(sp)
  105         sd      s3, 24(sp)
  106         sd      s4, 32(sp)
  107         sd      s5, 40(sp)
  108         sd      s6, 48(sp)
  109         sd      s7, 56(sp)
  110         sd      s8, 64(sp)
  111         sd      t1, 72(sp)
  112         sd      gp, 80(sp)
  113         sd      ra, 88(sp)
  114         /* Use register number to work in o32 and n32 */
  115         li      $9, ((CPU_BLOCKID_MAP << 8) | MAP_THREADMODE)
  116         move    $8, a0  
  117         sync
  118         .word   0x71280019      /* mtcr    t0, t1*/
  119         mfc0    t0, MIPS_COP_0_PRID, 1
  120         andi    t0, 0x3
  121         beqz    t0, 2f
  122         nop
  123         dla     t1, mpentry     /* child thread, go to hardware init */
  124         jr      t1
  125         nop
  126 
  127 
  128 2:      /*
  129          * Parent hardware thread, restore registers, return
  130          */
  131 #if 1
  132         /*
  133          * A0 Errata - Write MMU_SETUP after changing thread mode register.
  134          */
  135         li      $9, 0x400
  136         li      $8, 0
  137         .word   0x71280019      /* mtcr    $8, $9*/
  138         .word   0x000000c0      /* ehb */
  139 #endif
  140         dmfc0   t0, $4, 2       /* SP saved in UserLocal */
  141         ori     sp, t0, 0x7
  142         xori    sp, sp, 0x7     /* align 64 bit */
  143         addiu   sp, sp, -128
  144         ld      s0, 0(sp)
  145         ld      s1, 8(sp)
  146         ld      s2, 16(sp)
  147         ld      s3, 24(sp)
  148         ld      s4, 32(sp)
  149         ld      s5, 40(sp)
  150         ld      s6, 48(sp)
  151         ld      s7, 56(sp)
  152         ld      s8, 64(sp)
  153         ld      t1, 72(sp)
  154         ld      gp, 80(sp)
  155         ld      ra, 88(sp)
  156         mfc0    t1, MIPS_COP_0_STATUS
  157 
  158         move    sp, t0          /* Restore the real SP */
  159         jr      ra
  160         nop
  161 END(xlp_enable_threads)
  162 #endif

Cache object: fa275b5830fdba94a3e26475fde057a5


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