FreeBSD/Linux Kernel Cross Reference
sys/mips/nlm/tick.c
1 /*-
2 * Copyright 2003-2011 Netlogic Microsystems (Netlogic). All rights
3 * reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met:
8 *
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in
13 * the documentation and/or other materials provided with the
14 * distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY Netlogic Microsystems ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE
20 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
26 * THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * NETLOGIC_BSD */
29
30 /*
31 * Simple driver for the 32-bit interval counter built in to all
32 * MIPS32 CPUs.
33 */
34
35 #include <sys/cdefs.h>
36 __FBSDID("$FreeBSD: releng/9.1/sys/mips/nlm/tick.c 224110 2011-07-16 19:35:44Z jchandra $");
37
38 #include "opt_cputype.h"
39
40 #include <sys/param.h>
41 #include <sys/systm.h>
42 #include <sys/sysctl.h>
43 #include <sys/bus.h>
44 #include <sys/kernel.h>
45 #include <sys/module.h>
46 #include <sys/rman.h>
47 #include <sys/power.h>
48 #include <sys/smp.h>
49 #include <sys/time.h>
50 #include <sys/timeet.h>
51 #include <sys/timetc.h>
52
53 #include <machine/hwfunc.h>
54 #include <machine/clock.h>
55 #include <machine/locore.h>
56 #include <machine/md_var.h>
57 #include <machine/intr_machdep.h>
58
59 #include <mips/nlm/interrupt.h>
60
61 uint64_t counter_freq;
62
63 struct timecounter *platform_timecounter;
64
65 static DPCPU_DEFINE(uint32_t, cycles_per_tick);
66 static uint32_t cycles_per_usec;
67
68 static DPCPU_DEFINE(volatile uint32_t, counter_upper);
69 static DPCPU_DEFINE(volatile uint32_t, counter_lower_last);
70 static DPCPU_DEFINE(uint32_t, compare_ticks);
71 static DPCPU_DEFINE(uint32_t, lost_ticks);
72
73 struct clock_softc {
74 int intr_rid;
75 struct resource *intr_res;
76 void *intr_handler;
77 struct timecounter tc;
78 struct eventtimer et;
79 };
80 static struct clock_softc *softc;
81
82 /*
83 * Device methods
84 */
85 static int clock_probe(device_t);
86 static void clock_identify(driver_t *, device_t);
87 static int clock_attach(device_t);
88 static unsigned counter_get_timecount(struct timecounter *tc);
89
90 void
91 mips_timer_early_init(uint64_t clock_hz)
92 {
93 /* Initialize clock early so that we can use DELAY sooner */
94 counter_freq = clock_hz;
95 cycles_per_usec = (clock_hz / (1000 * 1000));
96 }
97
98 void
99 platform_initclocks(void)
100 {
101
102 if (platform_timecounter != NULL)
103 tc_init(platform_timecounter);
104 }
105
106 static uint64_t
107 tick_ticker(void)
108 {
109 uint64_t ret;
110 uint32_t ticktock;
111 uint32_t t_lower_last, t_upper;
112
113 /*
114 * Disable preemption because we are working with cpu specific data.
115 */
116 critical_enter();
117
118 /*
119 * Note that even though preemption is disabled, interrupts are
120 * still enabled. In particular there is a race with clock_intr()
121 * reading the values of 'counter_upper' and 'counter_lower_last'.
122 *
123 * XXX this depends on clock_intr() being executed periodically
124 * so that 'counter_upper' and 'counter_lower_last' are not stale.
125 */
126 do {
127 t_upper = DPCPU_GET(counter_upper);
128 t_lower_last = DPCPU_GET(counter_lower_last);
129 } while (t_upper != DPCPU_GET(counter_upper));
130
131 ticktock = mips_rd_count();
132
133 critical_exit();
134
135 /* COUNT register wrapped around */
136 if (ticktock < t_lower_last)
137 t_upper++;
138
139 ret = ((uint64_t)t_upper << 32) | ticktock;
140 return (ret);
141 }
142
143 void
144 mips_timer_init_params(uint64_t platform_counter_freq, int double_count)
145 {
146
147 /*
148 * XXX: Do not use printf here: uart code 8250 may use DELAY so this
149 * function should be called before cninit.
150 */
151 counter_freq = platform_counter_freq;
152 /*
153 * XXX: Some MIPS32 cores update the Count register only every two
154 * pipeline cycles.
155 * We know this because of status registers in CP0, make it automatic.
156 */
157 if (double_count != 0)
158 counter_freq /= 2;
159
160 cycles_per_usec = counter_freq / (1 * 1000 * 1000);
161 set_cputicker(tick_ticker, counter_freq, 1);
162 }
163
164 static int
165 sysctl_machdep_counter_freq(SYSCTL_HANDLER_ARGS)
166 {
167 int error;
168 uint64_t freq;
169
170 if (softc == NULL)
171 return (EOPNOTSUPP);
172 freq = counter_freq;
173 error = sysctl_handle_64(oidp, &freq, sizeof(freq), req);
174 if (error == 0 && req->newptr != NULL) {
175 counter_freq = freq;
176 softc->et.et_frequency = counter_freq;
177 softc->tc.tc_frequency = counter_freq;
178 }
179 return (error);
180 }
181
182 SYSCTL_PROC(_machdep, OID_AUTO, counter_freq, CTLTYPE_U64 | CTLFLAG_RW,
183 NULL, 0, sysctl_machdep_counter_freq, "QU",
184 "Timecounter frequency in Hz");
185
186 static unsigned
187 counter_get_timecount(struct timecounter *tc)
188 {
189
190 return (mips_rd_count());
191 }
192
193 /*
194 * Wait for about n microseconds (at least!).
195 */
196 void
197 DELAY(int n)
198 {
199 uint32_t cur, last, delta, usecs;
200
201 /*
202 * This works by polling the timer and counting the number of
203 * microseconds that go by.
204 */
205 last = mips_rd_count();
206 delta = usecs = 0;
207
208 while (n > usecs) {
209 cur = mips_rd_count();
210
211 /* Check to see if the timer has wrapped around. */
212 if (cur < last)
213 delta += cur + (0xffffffff - last) + 1;
214 else
215 delta += cur - last;
216
217 last = cur;
218
219 if (delta >= cycles_per_usec) {
220 usecs += delta / cycles_per_usec;
221 delta %= cycles_per_usec;
222 }
223 }
224 }
225
226 static int
227 clock_start(struct eventtimer *et,
228 struct bintime *first, struct bintime *period)
229 {
230 uint32_t fdiv, div, next;
231
232 if (period != NULL) {
233 div = (et->et_frequency * (period->frac >> 32)) >> 32;
234 if (period->sec != 0)
235 div += et->et_frequency * period->sec;
236 } else
237 div = 0;
238 if (first != NULL) {
239 fdiv = (et->et_frequency * (first->frac >> 32)) >> 32;
240 if (first->sec != 0)
241 fdiv += et->et_frequency * first->sec;
242 } else
243 fdiv = div;
244 DPCPU_SET(cycles_per_tick, div);
245 next = mips_rd_count() + fdiv;
246 DPCPU_SET(compare_ticks, next);
247 mips_wr_compare(next);
248 return (0);
249 }
250
251 static int
252 clock_stop(struct eventtimer *et)
253 {
254
255 DPCPU_SET(cycles_per_tick, 0);
256 mips_wr_compare(0xffffffff);
257 return (0);
258 }
259
260 /*
261 * Device section of file below
262 */
263 static int
264 clock_intr(void *arg)
265 {
266 struct clock_softc *sc = (struct clock_softc *)arg;
267 uint32_t cycles_per_tick;
268 uint32_t count, compare_last, compare_next, lost_ticks;
269
270 cycles_per_tick = DPCPU_GET(cycles_per_tick);
271 /*
272 * Set next clock edge.
273 */
274 count = mips_rd_count();
275 compare_last = DPCPU_GET(compare_ticks);
276 if (cycles_per_tick > 0) {
277 compare_next = count + cycles_per_tick;
278 DPCPU_SET(compare_ticks, compare_next);
279 mips_wr_compare(compare_next);
280 } else /* In one-shot mode timer should be stopped after the event. */
281 mips_wr_compare(0xffffffff);
282
283 /* COUNT register wrapped around */
284 if (count < DPCPU_GET(counter_lower_last)) {
285 DPCPU_SET(counter_upper, DPCPU_GET(counter_upper) + 1);
286 }
287 DPCPU_SET(counter_lower_last, count);
288
289 if (cycles_per_tick > 0) {
290
291 /*
292 * Account for the "lost time" between when the timer interrupt
293 * fired and when 'clock_intr' actually started executing.
294 */
295 lost_ticks = DPCPU_GET(lost_ticks);
296 lost_ticks += count - compare_last;
297
298 /*
299 * If the COUNT and COMPARE registers are no longer in sync
300 * then make up some reasonable value for the 'lost_ticks'.
301 *
302 * This could happen, for e.g., after we resume normal
303 * operations after exiting the debugger.
304 */
305 if (lost_ticks > 2 * cycles_per_tick)
306 lost_ticks = cycles_per_tick;
307
308 while (lost_ticks >= cycles_per_tick) {
309 if (sc->et.et_active)
310 sc->et.et_event_cb(&sc->et, sc->et.et_arg);
311 lost_ticks -= cycles_per_tick;
312 }
313 DPCPU_SET(lost_ticks, lost_ticks);
314 }
315 if (sc->et.et_active)
316 sc->et.et_event_cb(&sc->et, sc->et.et_arg);
317 return (FILTER_HANDLED);
318 }
319
320 static int
321 clock_probe(device_t dev)
322 {
323
324 if (device_get_unit(dev) != 0)
325 panic("can't attach more clocks");
326
327 device_set_desc(dev, "Generic MIPS32 ticker");
328 return (0);
329 }
330
331 static void
332 clock_identify(driver_t * drv, device_t parent)
333 {
334
335 BUS_ADD_CHILD(parent, 0, "clock", 0);
336 }
337
338 static int
339 clock_attach(device_t dev)
340 {
341 struct clock_softc *sc;
342
343 softc = sc = device_get_softc(dev);
344 cpu_establish_hardintr("compare", clock_intr, NULL,
345 sc, IRQ_TIMER, INTR_TYPE_CLK, &sc->intr_handler);
346
347 sc->tc.tc_get_timecount = counter_get_timecount;
348 sc->tc.tc_counter_mask = 0xffffffff;
349 sc->tc.tc_frequency = counter_freq;
350 sc->tc.tc_name = "MIPS32";
351 sc->tc.tc_quality = 800;
352 sc->tc.tc_priv = sc;
353 tc_init(&sc->tc);
354 sc->et.et_name = "MIPS32";
355 #if 0
356 sc->et.et_flags = ET_FLAGS_PERIODIC | ET_FLAGS_ONESHOT |
357 ET_FLAGS_PERCPU;
358 #endif
359 sc->et.et_flags = ET_FLAGS_PERIODIC | ET_FLAGS_PERCPU;
360 sc->et.et_quality = 800;
361 sc->et.et_frequency = counter_freq;
362 sc->et.et_min_period.sec = 0;
363 sc->et.et_min_period.frac = 0x00004000LLU << 32; /* To be safe. */
364 sc->et.et_max_period.sec = 0xfffffffeU / sc->et.et_frequency;
365 sc->et.et_max_period.frac =
366 ((0xfffffffeLLU << 32) / sc->et.et_frequency) << 32;
367 sc->et.et_start = clock_start;
368 sc->et.et_stop = clock_stop;
369 sc->et.et_priv = sc;
370 et_register(&sc->et);
371 return (0);
372 }
373
374 static device_method_t clock_methods[] = {
375 /* Device interface */
376 DEVMETHOD(device_probe, clock_probe),
377 DEVMETHOD(device_identify, clock_identify),
378 DEVMETHOD(device_attach, clock_attach),
379 DEVMETHOD(device_detach, bus_generic_detach),
380 DEVMETHOD(device_shutdown, bus_generic_shutdown),
381
382 {0, 0}
383 };
384
385 static driver_t clock_driver = {
386 "clock",
387 clock_methods,
388 sizeof(struct clock_softc),
389 };
390
391 static devclass_t clock_devclass;
392
393 DRIVER_MODULE(clock, nexus, clock_driver, clock_devclass, 0, 0);
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