The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


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FreeBSD/Linux Kernel Cross Reference
sys/mips/rmi/ehcireg.h

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    1 /*      $NetBSD: ehcireg.h,v 1.18 2004/10/22 10:38:17 augustss Exp $    */
    2 /*      $FreeBSD: stable/8/sys/mips/rmi/ehcireg.h 215938 2010-11-27 12:26:40Z jchandra $        */
    3 
    4 /*-
    5  * Copyright (c) 2001 The NetBSD Foundation, Inc.
    6  * All rights reserved.
    7  *
    8  * This code is derived from software contributed to The NetBSD Foundation
    9  * by Lennart Augustsson (lennart@augustsson.net).
   10  *
   11  * Redistribution and use in source and binary forms, with or without
   12  * modification, are permitted provided that the following conditions
   13  * are met:
   14  * 1. Redistributions of source code must retain the above copyright
   15  *    notice, this list of conditions and the following disclaimer.
   16  * 2. Redistributions in binary form must reproduce the above copyright
   17  *    notice, this list of conditions and the following disclaimer in the
   18  *    documentation and/or other materials provided with the distribution.
   19  * 3. All advertising materials mentioning features or use of this software
   20  *    must display the following acknowledgement:
   21  *        This product includes software developed by the NetBSD
   22  *        Foundation, Inc. and its contributors.
   23  * 4. Neither the name of The NetBSD Foundation nor the names of its
   24  *    contributors may be used to endorse or promote products derived
   25  *    from this software without specific prior written permission.
   26  *
   27  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
   28  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
   29  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
   30  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
   31  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
   32  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
   33  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
   34  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
   35  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
   36  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
   37  * POSSIBILITY OF SUCH DAMAGE.
   38  */
   39 
   40 /*
   41  * The EHCI 0.96 spec can be found at
   42  * http://developer.intel.com/technology/usb/download/ehci-r096.pdf
   43  * and the USB 2.0 spec at
   44  * http://www.usb.org/developers/data/usb_20.zip
   45  */
   46 
   47 #ifndef _DEV_PCI_EHCIREG_H_
   48 #define _DEV_PCI_EHCIREG_H_
   49 
   50 /*** PCI config registers ***/
   51 
   52 #define PCI_CBMEM               0x10    /* configuration base MEM */
   53 
   54 #define PCI_INTERFACE_EHCI      0x20
   55 
   56 #define PCI_USBREV              0x60    /* RO USB protocol revision */
   57 #define  PCI_USBREV_MASK        0xff
   58 #define  PCI_USBREV_PRE_1_0     0x00
   59 #define  PCI_USBREV_1_0         0x10
   60 #define  PCI_USBREV_1_1         0x11
   61 #define  PCI_USBREV_2_0         0x20
   62 
   63 #define PCI_EHCI_FLADJ          0x61    /* RW Frame len adj, SOF=59488+6*fladj */
   64 
   65 #define PCI_EHCI_PORTWAKECAP    0x62    /* RW Port wake caps (opt)  */
   66 
   67 /* EHCI Extended Capabilities */
   68 #define EHCI_EC_LEGSUP          0x01
   69 
   70 #define EHCI_EECP_NEXT(x)       (((x) >> 8) & 0xff)
   71 #define EHCI_EECP_ID(x)         ((x) & 0xff)
   72 
   73 /* Legacy support extended capability */
   74 #define EHCI_LEGSUP_OS_SEM      0x03    /* OS owned semaphore */
   75 #define EHCI_LEGSUP_BIOS_SEM    0x02    /* BIOS owned semaphore */
   76 #define EHCI_LEGSUP_USBLEGCTLSTS 0x04
   77 
   78 /*** EHCI capability registers ***/
   79 
   80 #define EHCI_CAPLENGTH          0x00    /* RO Capability register length field */
   81 /* reserved                     0x01 */
   82 #define EHCI_HCIVERSION         0x02    /* RO Interface version number */
   83 
   84 #define EHCI_HCSPARAMS          0x04    /* RO Structural parameters */
   85 #define  EHCI_HCS_DEBUGPORT(x)  (((x) >> 20) & 0xf)
   86 #define  EHCI_HCS_P_INDICATOR(x) ((x) & 0x10000)
   87 #define  EHCI_HCS_N_CC(x)       (((x) >> 12) & 0xf)     /* # of companion ctlrs */
   88 #define  EHCI_HCS_N_PCC(x)      (((x) >> 8) & 0xf)      /* # of ports per comp. */
   89 #define  EHCI_HCS_PPC(x)        ((x) & 0x10)    /* port power control */
   90 #define  EHCI_HCS_N_PORTS(x)    ((x) & 0xf)     /* # of ports */
   91 
   92 #define EHCI_HCCPARAMS          0x08    /* RO Capability parameters */
   93 #define  EHCI_HCC_EECP(x)       (((x) >> 8) & 0xff)     /* extended ports caps */
   94 #define  EHCI_HCC_IST(x)        (((x) >> 4) & 0xf)      /* isoc sched threshold */
   95 #define  EHCI_HCC_ASPC(x)       ((x) & 0x4)     /* async sched park cap */
   96 #define  EHCI_HCC_PFLF(x)       ((x) & 0x2)     /* prog frame list flag */
   97 #define  EHCI_HCC_64BIT(x)      ((x) & 0x1)     /* 64 bit address cap */
   98 
   99 #define EHCI_HCSP_PORTROUTE     0x0c    /* RO Companion port route description */
  100 
  101 /* EHCI operational registers.  Offset given by EHCI_CAPLENGTH register */
  102 #define EHCI_USBCMD             0x00    /* RO, RW, WO Command register */
  103 #define  EHCI_CMD_ITC_M         0x00ff0000      /* RW interrupt threshold ctrl */
  104 #define   EHCI_CMD_ITC_1        0x00010000
  105 #define   EHCI_CMD_ITC_2        0x00020000
  106 #define   EHCI_CMD_ITC_4        0x00040000
  107 #define   EHCI_CMD_ITC_8        0x00080000
  108 #define   EHCI_CMD_ITC_16       0x00100000
  109 #define   EHCI_CMD_ITC_32       0x00200000
  110 #define   EHCI_CMD_ITC_64       0x00400000
  111 #define  EHCI_CMD_ASPME         0x00000800      /* RW/RO async park enable */
  112 #define  EHCI_CMD_ASPMC         0x00000300      /* RW/RO async park count */
  113 #define  EHCI_CMD_LHCR          0x00000080      /* RW light host ctrl reset */
  114 #define  EHCI_CMD_IAAD          0x00000040      /* RW intr on async adv door
  115                                                  * bell */
  116 #define  EHCI_CMD_ASE           0x00000020      /* RW async sched enable */
  117 #define  EHCI_CMD_PSE           0x00000010      /* RW periodic sched enable */
  118 #define  EHCI_CMD_FLS_M         0x0000000c      /* RW/RO frame list size */
  119 #define  EHCI_CMD_FLS(x)        (((x) >> 2) & 3)        /* RW/RO frame list size */
  120 #define  EHCI_CMD_HCRESET       0x00000002      /* RW reset */
  121 #define  EHCI_CMD_RS            0x00000001      /* RW run/stop */
  122 
  123 #define EHCI_USBSTS             0x04    /* RO, RW, RWC Status register */
  124 #define  EHCI_STS_ASS           0x00008000      /* RO async sched status */
  125 #define  EHCI_STS_PSS           0x00004000      /* RO periodic sched status */
  126 #define  EHCI_STS_REC           0x00002000      /* RO reclamation */
  127 #define  EHCI_STS_HCH           0x00001000      /* RO host controller halted */
  128 #define  EHCI_STS_IAA           0x00000020      /* RWC interrupt on async adv */
  129 #define  EHCI_STS_HSE           0x00000010      /* RWC host system error */
  130 #define  EHCI_STS_FLR           0x00000008      /* RWC frame list rollover */
  131 #define  EHCI_STS_PCD           0x00000004      /* RWC port change detect */
  132 #define  EHCI_STS_ERRINT        0x00000002      /* RWC error interrupt */
  133 #define  EHCI_STS_INT           0x00000001      /* RWC interrupt */
  134 #define  EHCI_STS_INTRS(x)      ((x) & 0x3f)
  135 
  136 #define EHCI_NORMAL_INTRS (EHCI_STS_IAA | EHCI_STS_HSE | EHCI_STS_PCD | EHCI_STS_ERRINT | EHCI_STS_INT)
  137 
  138 #define EHCI_USBINTR            0x08    /* RW Interrupt register */
  139 #define EHCI_INTR_IAAE          0x00000020      /* interrupt on async advance
  140                                                  * ena */
  141 #define EHCI_INTR_HSEE          0x00000010      /* host system error ena */
  142 #define EHCI_INTR_FLRE          0x00000008      /* frame list rollover ena */
  143 #define EHCI_INTR_PCIE          0x00000004      /* port change ena */
  144 #define EHCI_INTR_UEIE          0x00000002      /* USB error intr ena */
  145 #define EHCI_INTR_UIE           0x00000001      /* USB intr ena */
  146 
  147 #define EHCI_FRINDEX            0x0c    /* RW Frame Index register */
  148 
  149 #define EHCI_CTRLDSSEGMENT      0x10    /* RW Control Data Structure Segment */
  150 
  151 #define EHCI_PERIODICLISTBASE   0x14    /* RW Periodic List Base */
  152 #define EHCI_ASYNCLISTADDR      0x18    /* RW Async List Base */
  153 
  154 #define EHCI_CONFIGFLAG         0x40    /* RW Configure Flag register */
  155 #define  EHCI_CONF_CF           0x00000001      /* RW configure flag */
  156 
  157 #define EHCI_PORTSC(n)          (0x40+4*(n))    /* RO, RW, RWC Port Status reg */
  158 #define  EHCI_PS_WKOC_E         0x00400000      /* RW wake on over current ena */
  159 #define  EHCI_PS_WKDSCNNT_E     0x00200000      /* RW wake on disconnect ena */
  160 #define  EHCI_PS_WKCNNT_E       0x00100000      /* RW wake on connect ena */
  161 #define  EHCI_PS_PTC            0x000f0000      /* RW port test control */
  162 #define  EHCI_PS_PIC            0x0000c000      /* RW port indicator control */
  163 #define  EHCI_PS_PO             0x00002000      /* RW port owner */
  164 #define  EHCI_PS_PP             0x00001000      /* RW,RO port power */
  165 #define  EHCI_PS_LS             0x00000c00      /* RO line status */
  166 #define  EHCI_PS_IS_LOWSPEED(x) (((x) & EHCI_PS_LS) == 0x00000400)
  167 #define  EHCI_PS_PR             0x00000100      /* RW port reset */
  168 #define  EHCI_PS_SUSP           0x00000080      /* RW suspend */
  169 #define  EHCI_PS_FPR            0x00000040      /* RW force port resume */
  170 #define  EHCI_PS_OCC            0x00000020      /* RWC over current change */
  171 #define  EHCI_PS_OCA            0x00000010      /* RO over current active */
  172 #define  EHCI_PS_PEC            0x00000008      /* RWC port enable change */
  173 #define  EHCI_PS_PE             0x00000004      /* RW port enable */
  174 #define  EHCI_PS_CSC            0x00000002      /* RWC connect status change */
  175 #define  EHCI_PS_CS             0x00000001      /* RO connect status */
  176 #define  EHCI_PS_CLEAR          (EHCI_PS_OCC|EHCI_PS_PEC|EHCI_PS_CSC)
  177 
  178 #define EHCI_PORT_RESET_COMPLETE 2      /* ms */
  179 
  180 #define EHCI_FLALIGN_ALIGN      0x1000
  181 
  182 /* No data structure may cross a page boundary. */
  183 #define EHCI_PAGE_SIZE 0x1000
  184 #define EHCI_PAGE(x) ((x) &~ 0xfff)
  185 #define EHCI_PAGE_OFFSET(x) ((x) & 0xfff)
  186 #if defined(__FreeBSD__)
  187 #define EHCI_PAGE_MASK(x) ((x) & 0xfff)
  188 #endif
  189 
  190 typedef u_int32_t ehci_link_t;
  191 
  192 #define EHCI_LINK_TERMINATE     0x00000001
  193 #define EHCI_LINK_TYPE(x)       ((x) & 0x00000006)
  194 #define  EHCI_LINK_ITD          0x0
  195 #define  EHCI_LINK_QH           0x2
  196 #define  EHCI_LINK_SITD         0x4
  197 #define  EHCI_LINK_FSTN         0x6
  198 #define EHCI_LINK_ADDR(x)       ((x) &~ 0x1f)
  199 
  200 typedef u_int32_t ehci_physaddr_t;
  201 
  202 /* Isochronous Transfer Descriptor */
  203 typedef struct {
  204         ehci_link_t itd_next;
  205         /* XXX many more */
  206 }      ehci_itd_t;
  207 
  208 #define EHCI_ITD_ALIGN 32
  209 
  210 /* Split Transaction Isochronous Transfer Descriptor */
  211 typedef struct {
  212         ehci_link_t sitd_next;
  213         /* XXX many more */
  214 }      ehci_sitd_t;
  215 
  216 #define EHCI_SITD_ALIGN 32
  217 
  218 /* Queue Element Transfer Descriptor */
  219 #define EHCI_QTD_NBUFFERS 5
  220 typedef struct {
  221         ehci_link_t qtd_next;
  222         ehci_link_t qtd_altnext;
  223         u_int32_t qtd_status;
  224 #define EHCI_QTD_GET_STATUS(x)  (((x) >>  0) & 0xff)
  225 #define EHCI_QTD_SET_STATUS(x) ((x) <<  0)
  226 #define  EHCI_QTD_ACTIVE        0x80
  227 #define  EHCI_QTD_HALTED        0x40
  228 #define  EHCI_QTD_BUFERR        0x20
  229 #define  EHCI_QTD_BABBLE        0x10
  230 #define  EHCI_QTD_XACTERR       0x08
  231 #define  EHCI_QTD_MISSEDMICRO   0x04
  232 #define  EHCI_QTD_SPLITXSTATE   0x02
  233 #define  EHCI_QTD_PINGSTATE     0x01
  234 #define  EHCI_QTD_STATERRS      0x7c
  235 #define EHCI_QTD_GET_PID(x)     (((x) >>  8) & 0x3)
  236 #define EHCI_QTD_SET_PID(x)     ((x) <<  8)
  237 #define  EHCI_QTD_PID_OUT       0x0
  238 #define  EHCI_QTD_PID_IN        0x1
  239 #define  EHCI_QTD_PID_SETUP     0x2
  240 #define EHCI_QTD_GET_CERR(x)    (((x) >> 10) &  0x3)
  241 #define EHCI_QTD_SET_CERR(x)    ((x) << 10)
  242 #define EHCI_QTD_GET_C_PAGE(x)  (((x) >> 12) &  0x7)
  243 #define EHCI_QTD_SET_C_PAGE(x)  ((x) << 12)
  244 #define EHCI_QTD_GET_IOC(x)     (((x) >> 15) &  0x1)
  245 #define EHCI_QTD_IOC            0x00008000
  246 #define EHCI_QTD_GET_BYTES(x)   (((x) >> 16) &  0x7fff)
  247 #define EHCI_QTD_SET_BYTES(x)   ((x) << 16)
  248 #define EHCI_QTD_GET_TOGGLE(x)  (((x) >> 31) &  0x1)
  249 #define EHCI_QTD_SET_TOGGLE(x)  ((x) << 31)
  250 #define EHCI_QTD_TOGGLE_MASK    0x80000000
  251         ehci_physaddr_t qtd_buffer[EHCI_QTD_NBUFFERS];
  252         ehci_physaddr_t qtd_buffer_hi[EHCI_QTD_NBUFFERS];
  253 }      ehci_qtd_t;
  254 
  255 #define EHCI_QTD_ALIGN 32
  256 
  257 /* Queue Head */
  258 typedef struct {
  259         ehci_link_t qh_link;
  260         u_int32_t qh_endp;
  261 #define EHCI_QH_GET_ADDR(x)     (((x) >>  0) & 0x7f)    /* endpoint addr */
  262 #define EHCI_QH_SET_ADDR(x)     (x)
  263 #define EHCI_QH_ADDRMASK        0x0000007f
  264 #define EHCI_QH_GET_INACT(x)    (((x) >>  7) & 0x01)    /* inactivate on next */
  265 #define EHCI_QH_INACT           0x00000080
  266 #define EHCI_QH_GET_ENDPT(x)    (((x) >>  8) & 0x0f)    /* endpoint no */
  267 #define EHCI_QH_SET_ENDPT(x)    ((x) <<  8)
  268 #define EHCI_QH_GET_EPS(x)      (((x) >> 12) & 0x03)    /* endpoint speed */
  269 #define EHCI_QH_SET_EPS(x)      ((x) << 12)
  270 #define  EHCI_QH_SPEED_FULL     0x0
  271 #define  EHCI_QH_SPEED_LOW      0x1
  272 #define  EHCI_QH_SPEED_HIGH     0x2
  273 #define EHCI_QH_GET_DTC(x)      (((x) >> 14) & 0x01)    /* data toggle control */
  274 #define EHCI_QH_DTC             0x00004000
  275 #define EHCI_QH_GET_HRECL(x)    (((x) >> 15) & 0x01)    /* head of reclamation */
  276 #define EHCI_QH_HRECL           0x00008000
  277 #define EHCI_QH_GET_MPL(x)      (((x) >> 16) & 0x7ff)   /* max packet len */
  278 #define EHCI_QH_SET_MPL(x)      ((x) << 16)
  279 #define EHCI_QH_MPLMASK         0x07ff0000
  280 #define EHCI_QH_GET_CTL(x)      (((x) >> 27) & 0x01)    /* control endpoint */
  281 #define EHCI_QH_CTL             0x08000000
  282 #define EHCI_QH_GET_NRL(x)      (((x) >> 28) & 0x0f)    /* NAK reload */
  283 #define EHCI_QH_SET_NRL(x)      ((x) << 28)
  284         u_int32_t qh_endphub;
  285 #define EHCI_QH_GET_SMASK(x)    (((x) >>  0) & 0xff)    /* intr sched mask */
  286 #define EHCI_QH_SET_SMASK(x)    ((x) <<  0)
  287 #define EHCI_QH_GET_CMASK(x)    (((x) >>  8) & 0xff)    /* split completion mask */
  288 #define EHCI_QH_SET_CMASK(x)    ((x) <<  8)
  289 #define EHCI_QH_GET_HUBA(x)     (((x) >> 16) & 0x7f)    /* hub address */
  290 #define EHCI_QH_SET_HUBA(x)     ((x) << 16)
  291 #define EHCI_QH_GET_PORT(x)     (((x) >> 23) & 0x7f)    /* hub port */
  292 #define EHCI_QH_SET_PORT(x)     ((x) << 23)
  293 #define EHCI_QH_GET_MULT(x)     (((x) >> 30) & 0x03)    /* pipe multiplier */
  294 #define EHCI_QH_SET_MULT(x)     ((x) << 30)
  295         ehci_link_t qh_curqtd;
  296         ehci_qtd_t qh_qtd;
  297 }      ehci_qh_t;
  298 
  299 #define EHCI_QH_ALIGN 32
  300 
  301 /* Periodic Frame Span Traversal Node */
  302 typedef struct {
  303         ehci_link_t fstn_link;
  304         ehci_link_t fstn_back;
  305 }      ehci_fstn_t;
  306 
  307 #define EHCI_FSTN_ALIGN 32
  308 
  309 #endif                          /* _DEV_PCI_EHCIREG_H_ */

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