Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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FreeBSD/Linux Kernel Cross Reference
sys/mips/rmi/msgring.cfg
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1 /*- 2 * SPDX-License-Identifier: BSD-3-Clause 3 * 4 * Copyright (c) 2003-2009 RMI Corporation 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. Neither the name of RMI Corporation, nor the names of its contributors, 16 * may be used to endorse or promote products derived from this software 17 * without specific prior written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 * 31 * $FreeBSD: releng/11.2/sys/mips/rmi/msgring.cfg 330897 2018-03-14 03:19:51Z eadler $ 32 * RMI_BSD */ 33 /* 34 * This file defines the message ring configuration for phoenix-8. It tries to allow 35 * many different point-point communications between the message stations on the message ring 36 * and as result is _not_ the best configuration for performance 37 * 38 * The message ring on phoenix family of processors connects the cpus, gmacs, xgmac/spi4, 39 * security engine and the general purpose DMA engines. It provides a high bandwidth, 40 * low latency communication links. On traditional processors, this communication goes through 41 * which inherently does not scale very well with increasing number of cpus. 42 * 43 * Message ring has an in-built flow control mechanism. Every agent/station on the ring has to 44 * have software configured credits to send messages to any agent. Every receiving agent on the 45 * ring has a 256 entry FIFO that can divided into "buckets". All addressing on the ring is 46 * in terms of buckets. There are a total 128 buckets on the ring. The total number of credits 47 * across all sending agents should not exceed the bucket size. 48 * 49 * Below are the receiving agents and the max number of buckets they can have 50 * CPU 0 : 8 buckets 51 * CPU 1 : 8 buckets 52 * CPU 2 : 8 buckets 53 * CPU 3 : 8 buckets 54 * CPU 4 : 8 buckets 55 * CPU 5 : 8 buckets 56 * CPU 6 : 8 buckets 57 * CPU 7 : 8 buckets 58 * 59 * XGMAC 0 / SPI4 0 60 * TX : 16 buckets 61 * FREE : 2 buckets 62 * XGMAC 1 / SPI4 1 63 * TX : 16 buckets 64 * FREE : 2 buckets 65 * 66 * GMAC : 8 buckets 67 * 68 * SEC : 8 buckets 69 * 70 * DMA : 8 buckets 71 * 72 * The bucket size of a bucket should be aligned to the bucket's starting index in that 73 * receiving station's FIFO. For example, if sizes of bucket0 and bucket1 of a station 74 * are 32 and 32, bucket2's size has to be 64. bucket size 0 is valid. 75 * 76 * The format of the file is pretty straight forward. Each bucket definition has the size 77 * and the list of sending agents to that bucket with the number of credits to send. 78 * 79 * Undefined buckets have a size of 0 and Tx stations have 0 credits to send to that bucket. 80 * 81 * Following are the currently supported bucket names 82 * cpu_0_0 83 * cpu_0_1 84 * cpu_0_2 85 * cpu_0_3 86 * cpu_0_4 87 * cpu_0_5 88 * cpu_0_6 89 * cpu_0_7 90 * 91 * cpu_1_0 92 * cpu_1_1 93 * cpu_1_2 94 * cpu_1_3 95 * cpu_1_4 96 * cpu_1_5 97 * cpu_1_6 98 * cpu_1_7 99 * 100 * cpu_2_0 101 * cpu_2_1 102 * cpu_2_2 103 * cpu_2_3 104 * cpu_2_4 105 * cpu_2_5 106 * cpu_2_6 107 * cpu_2_7 108 * 109 * cpu_3_0 110 * cpu_3_1 111 * cpu_3_2 112 * cpu_3_3 113 * cpu_3_4 114 * cpu_3_5 115 * cpu_3_6 116 * cpu_3_7 117 * 118 * cpu_4_0 119 * cpu_4_1 120 * cpu_4_2 121 * cpu_4_3 122 * cpu_4_4 123 * cpu_4_5 124 * cpu_4_6 125 * cpu_4_7 126 * 127 * cpu_5_0 128 * cpu_5_1 129 * cpu_5_2 130 * cpu_5_3 131 * cpu_5_4 132 * cpu_5_5 133 * cpu_5_6 134 * cpu_5_7 135 * 136 * cpu_6_0 137 * cpu_6_1 138 * cpu_6_2 139 * cpu_6_3 140 * cpu_6_4 141 * cpu_6_5 142 * cpu_6_6 143 * cpu_6_7 144 * 145 * cpu_7_0 146 * cpu_7_1 147 * cpu_7_2 148 * cpu_7_3 149 * cpu_7_4 150 * cpu_7_5 151 * cpu_7_6 152 * cpu_7_7 153 * 154 * xgs_0_tx_0 155 * xgs_0_tx_1 156 * xgs_0_tx_2 157 * xgs_0_tx_3 158 * xgs_0_tx_4 159 * xgs_0_tx_5 160 * xgs_0_tx_6 161 * xgs_0_tx_7 162 * xgs_0_tx_8 163 * xgs_0_tx_9 164 * xgs_0_tx_10 165 * xgs_0_tx_11 166 * xgs_0_tx_12 167 * xgs_0_tx_13 168 * xgs_0_tx_14 169 * xgs_0_tx_15 170 * 171 * xgs_1_tx_0 172 * xgs_1_tx_1 173 * xgs_1_tx_2 174 * xgs_1_tx_3 175 * xgs_1_tx_4 176 * xgs_1_tx_5 177 * xgs_1_tx_6 178 * xgs_1_tx_7 179 * xgs_1_tx_8 180 * xgs_1_tx_9 181 * xgs_1_tx_10 182 * xgs_1_tx_11 183 * xgs_1_tx_12 184 * xgs_1_tx_13 185 * xgs_1_tx_14 186 * xgs_1_tx_15 187 * 188 * gmac_rsvd_0 189 * gmac_rfr_0 190 * gmac_tx_0 191 * gmac_tx_1 192 * gmac_tx_2 193 * gmac_tx_3 194 * gmac_rsvd_1 195 * gmac_rfr_1 196 * 197 * xgs_0_rsvd 198 * xgs_0_rfr 199 * 200 * xgs_1_rsvd 201 * xgs_1_rfr 202 * 203 * sec_pipe_0 204 * sec_pipe_1 205 * sec_pipe_2 206 * sec_pipe_3 207 * sec_rsa 208 * 209 * Following are the currently supported Tx Agent/Station names 210 * 211 * tx_stn_cpu_0 212 * tx_stn_cpu_1 213 * tx_stn_cpu_2 214 * tx_stn_cpu_3 215 * tx_stn_cpu_4 216 * tx_stn_cpu_5 217 * tx_stn_cpu_6 218 * tx_stn_cpu_7 219 * 220 * tx_stn_xgs_0 221 * tx_stn_xgs_1 222 * 223 * tx_stn_gmac 224 * 225 * tx_stn_dma 226 * 227 * tx_stn_sec 228 * 229 * 230 * 231 */ 232 233 /*************************************************************/ 234 // CPU_0 Message Station 235 236 bucket "cpu_0_0" { 237 size 32; 238 "tx_stn_xgs_0" 8; 239 "tx_stn_xgs_1" 8; 240 "tx_stn_gmac" 8; 241 "tx_stn_sec" 8; 242 } 243 bucket "cpu_0_1" { 244 size 32; 245 "tx_stn_xgs_0" 8; 246 "tx_stn_xgs_1" 8; 247 "tx_stn_gmac" 8; 248 "tx_stn_sec" 8; 249 } 250 bucket "cpu_0_2" { 251 size 32; 252 "tx_stn_xgs_0" 8; 253 "tx_stn_xgs_1" 8; 254 "tx_stn_gmac" 8; 255 "tx_stn_sec" 8; 256 } 257 bucket "cpu_0_3" { 258 size 32; 259 "tx_stn_xgs_0" 8; 260 "tx_stn_xgs_1" 8; 261 "tx_stn_gmac" 8; 262 "tx_stn_sec" 8; 263 } 264 bucket "cpu_0_4" { 265 size 32; 266 "tx_stn_gmac" 16; 267 "tx_stn_xgs_0" 8; 268 "tx_stn_xgs_1" 8; 269 } 270 bucket "cpu_0_5" { 271 size 32; 272 "tx_stn_gmac" 16; 273 "tx_stn_xgs_0" 8; 274 "tx_stn_xgs_1" 8; 275 } 276 bucket "cpu_0_6" { 277 size 32; 278 "tx_stn_gmac" 16; 279 "tx_stn_xgs_0" 8; 280 "tx_stn_xgs_1" 8; 281 } 282 bucket "cpu_0_7" { 283 size 32; 284 "tx_stn_gmac" 16; 285 "tx_stn_xgs_0" 8; 286 "tx_stn_xgs_1" 8; 287 } 288 289 /*************************************************************/ 290 // CPU_1 Message Station 291 292 bucket "cpu_1_0" { 293 size 32; 294 "tx_stn_xgs_0" 8; 295 "tx_stn_xgs_1" 8; 296 "tx_stn_gmac" 8; 297 "tx_stn_sec" 8; 298 } 299 bucket "cpu_1_1" { 300 size 32; 301 "tx_stn_xgs_0" 8; 302 "tx_stn_xgs_1" 8; 303 "tx_stn_gmac" 8; 304 "tx_stn_sec" 8; 305 } 306 bucket "cpu_1_2" { 307 size 32; 308 "tx_stn_xgs_0" 8; 309 "tx_stn_xgs_1" 8; 310 "tx_stn_gmac" 8; 311 "tx_stn_sec" 8; 312 } 313 bucket "cpu_1_3" { 314 size 32; 315 "tx_stn_xgs_0" 8; 316 "tx_stn_xgs_1" 8; 317 "tx_stn_gmac" 8; 318 "tx_stn_sec" 4; 319 "tx_stn_cpu_0" 4; /* NEEDED BY RMIOS IPSEC */ 320 } 321 bucket "cpu_1_4" { 322 size 32; 323 "tx_stn_gmac" 16; 324 "tx_stn_xgs_0" 8; 325 "tx_stn_xgs_1" 8; 326 } 327 bucket "cpu_1_5" { 328 size 32; 329 "tx_stn_gmac" 16; 330 "tx_stn_xgs_0" 8; 331 "tx_stn_xgs_1" 8; 332 } 333 bucket "cpu_1_6" { 334 size 32; 335 "tx_stn_gmac" 16; 336 "tx_stn_xgs_0" 8; 337 "tx_stn_xgs_1" 8; 338 } 339 bucket "cpu_1_7" { 340 size 32; 341 "tx_stn_gmac" 16; 342 "tx_stn_xgs_0" 8; 343 "tx_stn_xgs_1" 8; 344 } 345 346 /*************************************************************/ 347 // CPU_2 Message Station 348 349 bucket "cpu_2_0" { 350 size 32; 351 "tx_stn_xgs_0" 8; 352 "tx_stn_xgs_1" 8; 353 "tx_stn_gmac" 8; 354 "tx_stn_sec" 8; 355 } 356 bucket "cpu_2_1" { 357 size 32; 358 "tx_stn_xgs_0" 8; 359 "tx_stn_xgs_1" 8; 360 "tx_stn_gmac" 8; 361 "tx_stn_sec" 8; 362 } 363 bucket "cpu_2_2" { 364 size 32; 365 "tx_stn_xgs_0" 8; 366 "tx_stn_xgs_1" 8; 367 "tx_stn_gmac" 8; 368 "tx_stn_sec" 8; 369 } 370 bucket "cpu_2_3" { 371 size 32; 372 "tx_stn_xgs_0" 8; 373 "tx_stn_xgs_1" 8; 374 "tx_stn_gmac" 8; 375 "tx_stn_sec" 8; 376 } 377 bucket "cpu_2_4" { 378 size 32; 379 "tx_stn_gmac" 16; 380 "tx_stn_xgs_0" 8; 381 "tx_stn_xgs_1" 8; 382 } 383 bucket "cpu_2_5" { 384 size 32; 385 "tx_stn_gmac" 16; 386 "tx_stn_xgs_0" 8; 387 "tx_stn_xgs_1" 8; 388 } 389 bucket "cpu_2_6" { 390 size 32; 391 "tx_stn_gmac" 16; 392 "tx_stn_xgs_0" 8; 393 "tx_stn_xgs_1" 8; 394 } 395 bucket "cpu_2_7" { 396 size 32; 397 "tx_stn_gmac" 16; 398 "tx_stn_xgs_0" 8; 399 "tx_stn_xgs_1" 8; 400 } 401 402 /*************************************************************/ 403 // CPU_3 Message Station 404 405 bucket "cpu_3_0" { 406 size 32; 407 "tx_stn_xgs_0" 8; 408 "tx_stn_xgs_1" 8; 409 "tx_stn_gmac" 8; 410 "tx_stn_sec" 8; 411 } 412 bucket "cpu_3_1" { 413 size 32; 414 "tx_stn_xgs_0" 8; 415 "tx_stn_xgs_1" 8; 416 "tx_stn_gmac" 8; 417 "tx_stn_sec" 8; 418 } 419 bucket "cpu_3_2" { 420 size 32; 421 "tx_stn_xgs_0" 8; 422 "tx_stn_xgs_1" 8; 423 "tx_stn_gmac" 8; 424 "tx_stn_sec" 8; 425 } 426 bucket "cpu_3_3" { 427 size 32; 428 "tx_stn_xgs_0" 8; 429 "tx_stn_xgs_1" 8; 430 "tx_stn_gmac" 8; 431 "tx_stn_sec" 8; 432 } 433 bucket "cpu_3_4" { 434 size 32; 435 "tx_stn_gmac" 16; 436 "tx_stn_xgs_0" 8; 437 "tx_stn_xgs_1" 8; 438 } 439 bucket "cpu_3_5" { 440 size 32; 441 "tx_stn_gmac" 16; 442 "tx_stn_xgs_0" 8; 443 "tx_stn_xgs_1" 8; 444 } 445 bucket "cpu_3_6" { 446 size 32; 447 "tx_stn_gmac" 16; 448 "tx_stn_xgs_0" 8; 449 "tx_stn_xgs_1" 8; 450 } 451 bucket "cpu_3_7" { 452 size 32; 453 "tx_stn_gmac" 16; 454 "tx_stn_xgs_0" 8; 455 "tx_stn_xgs_1" 8; 456 } 457 458 /*************************************************************/ 459 // CPU_4 Message Station 460 461 bucket "cpu_4_0" { 462 size 32; 463 "tx_stn_xgs_0" 8; 464 "tx_stn_xgs_1" 8; 465 "tx_stn_gmac" 8; 466 "tx_stn_sec" 8; 467 } 468 bucket "cpu_4_1" { 469 size 32; 470 "tx_stn_xgs_0" 8; 471 "tx_stn_xgs_1" 8; 472 "tx_stn_gmac" 8; 473 "tx_stn_sec" 8; 474 } 475 bucket "cpu_4_2" { 476 size 32; 477 "tx_stn_xgs_0" 8; 478 "tx_stn_xgs_1" 8; 479 "tx_stn_gmac" 8; 480 "tx_stn_sec" 8; 481 } 482 bucket "cpu_4_3" { 483 size 32; 484 "tx_stn_xgs_0" 8; 485 "tx_stn_xgs_1" 8; 486 "tx_stn_gmac" 8; 487 "tx_stn_sec" 8; 488 } 489 bucket "cpu_4_4" { 490 size 32; 491 "tx_stn_gmac" 16; 492 "tx_stn_xgs_0" 8; 493 "tx_stn_xgs_1" 8; 494 } 495 bucket "cpu_4_5" { 496 size 32; 497 "tx_stn_gmac" 16; 498 "tx_stn_xgs_0" 8; 499 "tx_stn_xgs_1" 8; 500 } 501 bucket "cpu_4_6" { 502 size 32; 503 "tx_stn_gmac" 16; 504 "tx_stn_xgs_0" 8; 505 "tx_stn_xgs_1" 8; 506 } 507 bucket "cpu_4_7" { 508 size 32; 509 "tx_stn_gmac" 16; 510 "tx_stn_xgs_0" 8; 511 "tx_stn_xgs_1" 8; 512 } 513 514 /*************************************************************/ 515 // CPU_5 Message Station 516 517 bucket "cpu_5_0" { 518 size 32; 519 "tx_stn_xgs_0" 8; 520 "tx_stn_xgs_1" 8; 521 "tx_stn_gmac" 8; 522 "tx_stn_sec" 8; 523 } 524 bucket "cpu_5_1" { 525 size 32; 526 "tx_stn_xgs_0" 8; 527 "tx_stn_xgs_1" 8; 528 "tx_stn_gmac" 8; 529 "tx_stn_sec" 8; 530 } 531 bucket "cpu_5_2" { 532 size 32; 533 "tx_stn_xgs_0" 8; 534 "tx_stn_xgs_1" 8; 535 "tx_stn_gmac" 8; 536 "tx_stn_sec" 8; 537 } 538 bucket "cpu_5_3" { 539 size 32; 540 "tx_stn_xgs_0" 8; 541 "tx_stn_xgs_1" 8; 542 "tx_stn_gmac" 8; 543 "tx_stn_sec" 8; 544 } 545 bucket "cpu_5_4" { 546 size 32; 547 "tx_stn_gmac" 16; 548 "tx_stn_xgs_0" 8; 549 "tx_stn_xgs_1" 8; 550 } 551 bucket "cpu_5_5" { 552 size 32; 553 "tx_stn_gmac" 16; 554 "tx_stn_xgs_0" 8; 555 "tx_stn_xgs_1" 8; 556 } 557 bucket "cpu_5_6" { 558 size 32; 559 "tx_stn_gmac" 16; 560 "tx_stn_xgs_0" 8; 561 "tx_stn_xgs_1" 8; 562 } 563 bucket "cpu_5_7" { 564 size 32; 565 "tx_stn_gmac" 16; 566 "tx_stn_xgs_0" 8; 567 "tx_stn_xgs_1" 8; 568 } 569 570 571 /*************************************************************/ 572 // CPU_6 Message Station 573 574 bucket "cpu_6_0" { 575 size 32; 576 "tx_stn_xgs_0" 8; 577 "tx_stn_xgs_1" 8; 578 "tx_stn_gmac" 8; 579 "tx_stn_sec" 8; 580 } 581 bucket "cpu_6_1" { 582 size 32; 583 "tx_stn_xgs_0" 8; 584 "tx_stn_xgs_1" 8; 585 "tx_stn_gmac" 8; 586 "tx_stn_sec" 8; 587 } 588 bucket "cpu_6_2" { 589 size 32; 590 "tx_stn_xgs_0" 8; 591 "tx_stn_xgs_1" 8; 592 "tx_stn_gmac" 8; 593 "tx_stn_sec" 8; 594 } 595 bucket "cpu_6_3" { 596 size 32; 597 "tx_stn_xgs_0" 8; 598 "tx_stn_xgs_1" 8; 599 "tx_stn_gmac" 8; 600 "tx_stn_sec" 8; 601 } 602 bucket "cpu_6_4" { 603 size 32; 604 "tx_stn_gmac" 16; 605 "tx_stn_xgs_0" 8; 606 "tx_stn_xgs_1" 8; 607 } 608 bucket "cpu_6_5" { 609 size 32; 610 "tx_stn_gmac" 16; 611 "tx_stn_xgs_0" 8; 612 "tx_stn_xgs_1" 8; 613 } 614 bucket "cpu_6_6" { 615 size 32; 616 "tx_stn_gmac" 16; 617 "tx_stn_xgs_0" 8; 618 "tx_stn_xgs_1" 8; 619 } 620 bucket "cpu_6_7" { 621 size 32; 622 "tx_stn_gmac" 16; 623 "tx_stn_xgs_0" 8; 624 "tx_stn_xgs_1" 8; 625 } 626 627 628 /*************************************************************/ 629 // CPU_7 Message Station 630 631 bucket "cpu_7_0" { 632 size 32; 633 "tx_stn_xgs_0" 8; 634 "tx_stn_xgs_1" 8; 635 "tx_stn_gmac" 8; 636 "tx_stn_sec" 8; 637 } 638 bucket "cpu_7_1" { 639 size 32; 640 "tx_stn_xgs_0" 8; 641 "tx_stn_xgs_1" 8; 642 "tx_stn_gmac" 8; 643 "tx_stn_sec" 8; 644 } 645 bucket "cpu_7_2" { 646 size 32; 647 "tx_stn_xgs_0" 8; 648 "tx_stn_xgs_1" 8; 649 "tx_stn_gmac" 8; 650 "tx_stn_sec" 8; 651 } 652 bucket "cpu_7_3" { 653 size 32; 654 "tx_stn_xgs_0" 8; 655 "tx_stn_xgs_1" 8; 656 "tx_stn_gmac" 8; 657 "tx_stn_sec" 8; 658 } 659 bucket "cpu_7_4" { 660 size 32; 661 "tx_stn_gmac" 16; 662 "tx_stn_xgs_0" 8; 663 "tx_stn_xgs_1" 8; 664 } 665 bucket "cpu_7_5" { 666 size 32; 667 "tx_stn_gmac" 16; 668 "tx_stn_xgs_0" 8; 669 "tx_stn_xgs_1" 8; 670 } 671 bucket "cpu_7_6" { 672 size 32; 673 "tx_stn_gmac" 16; 674 "tx_stn_xgs_0" 8; 675 "tx_stn_xgs_1" 8; 676 } 677 bucket "cpu_7_7" { 678 size 32; 679 "tx_stn_gmac" 16; 680 "tx_stn_xgs_0" 8; 681 "tx_stn_xgs_1" 8; 682 } 683 684 685 /*************************************************************/ 686 // GMAC Message Station 687 688 bucket "gmac_rfr_0" { 689 size 32; 690 "tx_stn_cpu_0" 2; 691 "tx_stn_cpu_1" 2; 692 "tx_stn_cpu_2" 4; 693 "tx_stn_cpu_3" 4; 694 "tx_stn_cpu_4" 4; 695 "tx_stn_cpu_5" 4; 696 "tx_stn_cpu_6" 4; 697 "tx_stn_cpu_7" 4; 698 "tx_stn_gmac" 4; 699 } 700 701 bucket "gmac_tx_0" { 702 size 32; 703 "tx_stn_cpu_0" 4; 704 "tx_stn_cpu_1" 4; 705 "tx_stn_cpu_2" 4; 706 "tx_stn_cpu_3" 4; 707 "tx_stn_cpu_4" 4; 708 "tx_stn_cpu_5" 4; 709 "tx_stn_cpu_6" 4; 710 "tx_stn_cpu_7" 4; 711 } 712 713 bucket "gmac_tx_1" { 714 size 32; 715 "tx_stn_cpu_0" 4; 716 "tx_stn_cpu_1" 4; 717 "tx_stn_cpu_2" 4; 718 "tx_stn_cpu_3" 4; 719 "tx_stn_cpu_4" 4; 720 "tx_stn_cpu_5" 4; 721 "tx_stn_cpu_6" 4; 722 "tx_stn_cpu_7" 4; 723 } 724 725 bucket "gmac_tx_2" { 726 size 32; 727 "tx_stn_cpu_0" 4; 728 "tx_stn_cpu_1" 4; 729 "tx_stn_cpu_2" 4; 730 "tx_stn_cpu_3" 4; 731 "tx_stn_cpu_4" 4; 732 "tx_stn_cpu_5" 4; 733 "tx_stn_cpu_6" 4; 734 "tx_stn_cpu_7" 4; 735 } 736 737 bucket "gmac_tx_3" { 738 size 32; 739 "tx_stn_cpu_0" 4; 740 "tx_stn_cpu_1" 4; 741 "tx_stn_cpu_2" 4; 742 "tx_stn_cpu_3" 4; 743 "tx_stn_cpu_4" 4; 744 "tx_stn_cpu_5" 4; 745 "tx_stn_cpu_6" 4; 746 "tx_stn_cpu_7" 4; 747 } 748 749 bucket "gmac_rfr_1" { 750 size 32; 751 "tx_stn_cpu_0" 2; 752 "tx_stn_cpu_1" 2; 753 "tx_stn_cpu_2" 4; 754 "tx_stn_cpu_3" 4; 755 "tx_stn_cpu_4" 4; 756 "tx_stn_cpu_5" 4; 757 "tx_stn_cpu_6" 4; 758 "tx_stn_cpu_7" 4; 759 "tx_stn_gmac" 4; 760 } 761 /*********************************************/ 762 // xgmac 763 bucket "xgs_0_rfr" { 764 size 32; 765 "tx_stn_cpu_0" 2; 766 "tx_stn_cpu_1" 2; 767 "tx_stn_cpu_2" 4; 768 "tx_stn_cpu_3" 4; 769 "tx_stn_cpu_4" 4; 770 "tx_stn_cpu_5" 4; 771 "tx_stn_cpu_6" 4; 772 "tx_stn_cpu_7" 4; 773 "tx_stn_xgs_0" 4; 774 } 775 776 bucket "xgs_0_tx_0" { 777 size 32; 778 "tx_stn_cpu_0" 4; 779 "tx_stn_cpu_1" 4; 780 "tx_stn_cpu_2" 4; 781 "tx_stn_cpu_3" 4; 782 "tx_stn_cpu_4" 4; 783 "tx_stn_cpu_5" 4; 784 "tx_stn_cpu_6" 4; 785 "tx_stn_cpu_7" 4; 786 } 787 788 bucket "xgs_0_tx_1" { 789 size 16; 790 "tx_stn_cpu_0" 2; 791 "tx_stn_cpu_1" 2; 792 "tx_stn_cpu_2" 2; 793 "tx_stn_cpu_3" 2; 794 "tx_stn_cpu_4" 2; 795 "tx_stn_cpu_5" 2; 796 "tx_stn_cpu_6" 2; 797 "tx_stn_cpu_7" 2; 798 } 799 800 bucket "xgs_0_tx_2" { 801 size 16; 802 "tx_stn_cpu_0" 2; 803 "tx_stn_cpu_1" 2; 804 "tx_stn_cpu_2" 2; 805 "tx_stn_cpu_3" 2; 806 "tx_stn_cpu_4" 2; 807 "tx_stn_cpu_5" 2; 808 "tx_stn_cpu_6" 2; 809 "tx_stn_cpu_7" 2; 810 } 811 812 bucket "xgs_0_tx_3" { 813 size 16; 814 "tx_stn_cpu_0" 2; 815 "tx_stn_cpu_1" 2; 816 "tx_stn_cpu_2" 2; 817 "tx_stn_cpu_3" 2; 818 "tx_stn_cpu_4" 2; 819 "tx_stn_cpu_5" 2; 820 "tx_stn_cpu_6" 2; 821 "tx_stn_cpu_7" 2; 822 } 823 824 bucket "xgs_0_tx_4" { 825 size 16; 826 "tx_stn_cpu_0" 2; 827 "tx_stn_cpu_1" 2; 828 "tx_stn_cpu_2" 2; 829 "tx_stn_cpu_3" 2; 830 "tx_stn_cpu_4" 2; 831 "tx_stn_cpu_5" 2; 832 "tx_stn_cpu_6" 2; 833 "tx_stn_cpu_7" 2; 834 } 835 bucket "xgs_0_tx_5" { 836 size 16; 837 "tx_stn_cpu_0" 2; 838 "tx_stn_cpu_1" 2; 839 "tx_stn_cpu_2" 2; 840 "tx_stn_cpu_3" 2; 841 "tx_stn_cpu_4" 2; 842 "tx_stn_cpu_5" 2; 843 "tx_stn_cpu_6" 2; 844 "tx_stn_cpu_7" 2; 845 } 846 847 bucket "xgs_0_tx_6" { 848 size 16; 849 "tx_stn_cpu_0" 2; 850 "tx_stn_cpu_1" 2; 851 "tx_stn_cpu_2" 2; 852 "tx_stn_cpu_3" 2; 853 "tx_stn_cpu_4" 2; 854 "tx_stn_cpu_5" 2; 855 "tx_stn_cpu_6" 2; 856 "tx_stn_cpu_7" 2; 857 } 858 859 bucket "xgs_0_tx_7" { 860 size 16; 861 "tx_stn_cpu_0" 2; 862 "tx_stn_cpu_1" 2; 863 "tx_stn_cpu_2" 2; 864 "tx_stn_cpu_3" 2; 865 "tx_stn_cpu_4" 2; 866 "tx_stn_cpu_5" 2; 867 "tx_stn_cpu_6" 2; 868 "tx_stn_cpu_7" 2; 869 } 870 871 bucket "xgs_0_tx_8" { 872 size 16; 873 "tx_stn_cpu_0" 2; 874 "tx_stn_cpu_1" 2; 875 "tx_stn_cpu_2" 2; 876 "tx_stn_cpu_3" 2; 877 "tx_stn_cpu_4" 2; 878 "tx_stn_cpu_5" 2; 879 "tx_stn_cpu_6" 2; 880 "tx_stn_cpu_7" 2; 881 } 882 883 bucket "xgs_0_tx_9" { 884 size 16; 885 "tx_stn_cpu_0" 2; 886 "tx_stn_cpu_1" 2; 887 "tx_stn_cpu_2" 2; 888 "tx_stn_cpu_3" 2; 889 "tx_stn_cpu_4" 2; 890 "tx_stn_cpu_5" 2; 891 "tx_stn_cpu_6" 2; 892 "tx_stn_cpu_7" 2; 893 } 894 895 bucket "xgs_0_tx_10" { 896 size 16; 897 "tx_stn_cpu_0" 2; 898 "tx_stn_cpu_1" 2; 899 "tx_stn_cpu_2" 2; 900 "tx_stn_cpu_3" 2; 901 "tx_stn_cpu_4" 2; 902 "tx_stn_cpu_5" 2; 903 "tx_stn_cpu_6" 2; 904 "tx_stn_cpu_7" 2; 905 } 906 907 908 bucket "xgs_0_tx_11" { 909 size 16; 910 "tx_stn_cpu_0" 2; 911 "tx_stn_cpu_1" 2; 912 "tx_stn_cpu_2" 2; 913 "tx_stn_cpu_3" 2; 914 "tx_stn_cpu_4" 2; 915 "tx_stn_cpu_5" 2; 916 "tx_stn_cpu_6" 2; 917 "tx_stn_cpu_7" 2; 918 } 919 920 bucket "xgs_0_tx_12" { 921 size 16; 922 "tx_stn_cpu_0" 2; 923 "tx_stn_cpu_1" 2; 924 "tx_stn_cpu_2" 2; 925 "tx_stn_cpu_3" 2; 926 "tx_stn_cpu_4" 2; 927 "tx_stn_cpu_5" 2; 928 "tx_stn_cpu_6" 2; 929 "tx_stn_cpu_7" 2; 930 } 931 932 bucket "xgs_0_tx_13" { 933 size 16; 934 "tx_stn_cpu_0" 2; 935 "tx_stn_cpu_1" 2; 936 "tx_stn_cpu_2" 2; 937 "tx_stn_cpu_3" 2; 938 "tx_stn_cpu_4" 2; 939 "tx_stn_cpu_5" 2; 940 "tx_stn_cpu_6" 2; 941 "tx_stn_cpu_7" 2; 942 } 943 944 bucket "xgs_0_tx_14" { 945 size 16; 946 "tx_stn_cpu_0" 2; 947 "tx_stn_cpu_1" 2; 948 "tx_stn_cpu_2" 2; 949 "tx_stn_cpu_3" 2; 950 "tx_stn_cpu_4" 2; 951 "tx_stn_cpu_5" 2; 952 "tx_stn_cpu_6" 2; 953 "tx_stn_cpu_7" 2; 954 } 955 956 957 bucket "xgs_1_rfr" { 958 size 32; 959 "tx_stn_cpu_0" 2; 960 "tx_stn_cpu_1" 2; 961 "tx_stn_cpu_2" 4; 962 "tx_stn_cpu_3" 4; 963 "tx_stn_cpu_4" 4; 964 "tx_stn_cpu_5" 4; 965 "tx_stn_cpu_6" 4; 966 "tx_stn_cpu_7" 4; 967 "tx_stn_xgs_1" 4; 968 } 969 970 bucket "xgs_1_tx_0" { 971 size 32; 972 "tx_stn_cpu_0" 4; 973 "tx_stn_cpu_1" 4; 974 "tx_stn_cpu_2" 4; 975 "tx_stn_cpu_3" 4; 976 "tx_stn_cpu_4" 4; 977 "tx_stn_cpu_5" 4; 978 "tx_stn_cpu_6" 4; 979 "tx_stn_cpu_7" 4; 980 } 981 982 983 bucket "xgs_1_tx_1" { 984 size 16; 985 "tx_stn_cpu_0" 2; 986 "tx_stn_cpu_1" 2; 987 "tx_stn_cpu_2" 2; 988 "tx_stn_cpu_3" 2; 989 "tx_stn_cpu_4" 2; 990 "tx_stn_cpu_5" 2; 991 "tx_stn_cpu_6" 2; 992 "tx_stn_cpu_7" 2; 993 } 994 995 bucket "xgs_1_tx_2" { 996 size 16; 997 "tx_stn_cpu_0" 2; 998 "tx_stn_cpu_1" 2; 999 "tx_stn_cpu_2" 2; 1000 "tx_stn_cpu_3" 2; 1001 "tx_stn_cpu_4" 2; 1002 "tx_stn_cpu_5" 2; 1003 "tx_stn_cpu_6" 2; 1004 "tx_stn_cpu_7" 2; 1005 } 1006 1007 bucket "xgs_1_tx_3" { 1008 size 16; 1009 "tx_stn_cpu_0" 2; 1010 "tx_stn_cpu_1" 2; 1011 "tx_stn_cpu_2" 2; 1012 "tx_stn_cpu_3" 2; 1013 "tx_stn_cpu_4" 2; 1014 "tx_stn_cpu_5" 2; 1015 "tx_stn_cpu_6" 2; 1016 "tx_stn_cpu_7" 2; 1017 } 1018 1019 bucket "xgs_1_tx_4" { 1020 size 16; 1021 "tx_stn_cpu_0" 2; 1022 "tx_stn_cpu_1" 2; 1023 "tx_stn_cpu_2" 2; 1024 "tx_stn_cpu_3" 2; 1025 "tx_stn_cpu_4" 2; 1026 "tx_stn_cpu_5" 2; 1027 "tx_stn_cpu_6" 2; 1028 "tx_stn_cpu_7" 2; 1029 } 1030 1031 bucket "xgs_1_tx_5" { 1032 size 16; 1033 "tx_stn_cpu_0" 2; 1034 "tx_stn_cpu_1" 2; 1035 "tx_stn_cpu_2" 2; 1036 "tx_stn_cpu_3" 2; 1037 "tx_stn_cpu_4" 2; 1038 "tx_stn_cpu_5" 2; 1039 "tx_stn_cpu_6" 2; 1040 "tx_stn_cpu_7" 2; 1041 } 1042 1043 bucket "xgs_1_tx_6" { 1044 size 16; 1045 "tx_stn_cpu_0" 2; 1046 "tx_stn_cpu_1" 2; 1047 "tx_stn_cpu_2" 2; 1048 "tx_stn_cpu_3" 2; 1049 "tx_stn_cpu_4" 2; 1050 "tx_stn_cpu_5" 2; 1051 "tx_stn_cpu_6" 2; 1052 "tx_stn_cpu_7" 2; 1053 } 1054 1055 bucket "xgs_1_tx_7" { 1056 size 16; 1057 "tx_stn_cpu_0" 2; 1058 "tx_stn_cpu_1" 2; 1059 "tx_stn_cpu_2" 2; 1060 "tx_stn_cpu_3" 2; 1061 "tx_stn_cpu_4" 2; 1062 "tx_stn_cpu_5" 2; 1063 "tx_stn_cpu_6" 2; 1064 "tx_stn_cpu_7" 2; 1065 } 1066 1067 1068 bucket "xgs_1_tx_8" { 1069 size 16; 1070 "tx_stn_cpu_0" 2; 1071 "tx_stn_cpu_1" 2; 1072 "tx_stn_cpu_2" 2; 1073 "tx_stn_cpu_3" 2; 1074 "tx_stn_cpu_4" 2; 1075 "tx_stn_cpu_5" 2; 1076 "tx_stn_cpu_6" 2; 1077 "tx_stn_cpu_7" 2; 1078 } 1079 1080 1081 bucket "xgs_1_tx_9" { 1082 size 16; 1083 "tx_stn_cpu_0" 2; 1084 "tx_stn_cpu_1" 2; 1085 "tx_stn_cpu_2" 2; 1086 "tx_stn_cpu_3" 2; 1087 "tx_stn_cpu_4" 2; 1088 "tx_stn_cpu_5" 2; 1089 "tx_stn_cpu_6" 2; 1090 "tx_stn_cpu_7" 2; 1091 } 1092 1093 1094 bucket "xgs_1_tx_10" { 1095 size 16; 1096 "tx_stn_cpu_0" 2; 1097 "tx_stn_cpu_1" 2; 1098 "tx_stn_cpu_2" 2; 1099 "tx_stn_cpu_3" 2; 1100 "tx_stn_cpu_4" 2; 1101 "tx_stn_cpu_5" 2; 1102 "tx_stn_cpu_6" 2; 1103 "tx_stn_cpu_7" 2; 1104 } 1105 1106 bucket "xgs_1_tx_11" { 1107 size 16; 1108 "tx_stn_cpu_0" 2; 1109 "tx_stn_cpu_1" 2; 1110 "tx_stn_cpu_2" 2; 1111 "tx_stn_cpu_3" 2; 1112 "tx_stn_cpu_4" 2; 1113 "tx_stn_cpu_5" 2; 1114 "tx_stn_cpu_6" 2; 1115 "tx_stn_cpu_7" 2; 1116 } 1117 1118 bucket "xgs_1_tx_12" { 1119 size 16; 1120 "tx_stn_cpu_0" 2; 1121 "tx_stn_cpu_1" 2; 1122 "tx_stn_cpu_2" 2; 1123 "tx_stn_cpu_3" 2; 1124 "tx_stn_cpu_4" 2; 1125 "tx_stn_cpu_5" 2; 1126 "tx_stn_cpu_6" 2; 1127 "tx_stn_cpu_7" 2; 1128 } 1129 1130 bucket "xgs_1_tx_13" { 1131 size 16; 1132 "tx_stn_cpu_0" 2; 1133 "tx_stn_cpu_1" 2; 1134 "tx_stn_cpu_2" 2; 1135 "tx_stn_cpu_3" 2; 1136 "tx_stn_cpu_4" 2; 1137 "tx_stn_cpu_5" 2; 1138 "tx_stn_cpu_6" 2; 1139 "tx_stn_cpu_7" 2; 1140 } 1141 1142 bucket "xgs_1_tx_14" { 1143 size 16; 1144 "tx_stn_cpu_0" 2; 1145 "tx_stn_cpu_1" 2; 1146 "tx_stn_cpu_2" 2; 1147 "tx_stn_cpu_3" 2; 1148 "tx_stn_cpu_4" 2; 1149 "tx_stn_cpu_5" 2; 1150 "tx_stn_cpu_6" 2; 1151 "tx_stn_cpu_7" 2; 1152 } 1153 1154 1155 1156 1157 1158 1159 /*************************************************************/ 1160 // Security Message Station 1161 1162 bucket "sec_pipe_0" { 1163 size 128; 1164 "tx_stn_cpu_0" 16; 1165 "tx_stn_cpu_1" 16; 1166 "tx_stn_cpu_2" 16; 1167 "tx_stn_cpu_3" 16; 1168 "tx_stn_cpu_4" 16; 1169 "tx_stn_cpu_5" 16; 1170 "tx_stn_cpu_6" 16; 1171 "tx_stn_cpu_7" 16; 1172 } 1173 1174 bucket "sec_rsa" { 1175 size 128; 1176 "tx_stn_cpu_0" 16; 1177 "tx_stn_cpu_1" 16; 1178 "tx_stn_cpu_2" 16; 1179 "tx_stn_cpu_3" 16; 1180 "tx_stn_cpu_4" 16; 1181 "tx_stn_cpu_5" 16; 1182 "tx_stn_cpu_6" 16; 1183 "tx_stn_cpu_7" 16; 1184 } 1185
Cache object: b080e342afc27d0d9c183a9fae5ac5b3
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