The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


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FreeBSD/Linux Kernel Cross Reference
sys/mips/rmi/msgring.cfg

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    1 /*-
    2  * Copyright (c) 2003-2009 RMI Corporation
    3  * All rights reserved.
    4  *
    5  * Redistribution and use in source and binary forms, with or without
    6  * modification, are permitted provided that the following conditions
    7  * are met:
    8  * 1. Redistributions of source code must retain the above copyright
    9  *    notice, this list of conditions and the following disclaimer.
   10  * 2. Redistributions in binary form must reproduce the above copyright
   11  *    notice, this list of conditions and the following disclaimer in the
   12  *    documentation and/or other materials provided with the distribution.
   13  * 3. Neither the name of RMI Corporation, nor the names of its contributors,
   14  *    may be used to endorse or promote products derived from this software
   15  *    without specific prior written permission.
   16  *
   17  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
   18  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   19  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   20  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
   21  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
   22  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
   23  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
   24  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
   25  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   26  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   27  * SUCH DAMAGE.
   28  *
   29  * RMI_BSD */
   30 /* 
   31  * This file defines the message ring configuration for phoenix-8. It tries to allow 
   32  * many different point-point communications between the message stations on the message ring
   33  * and as result is _not_ the best configuration for performance
   34  *
   35  * The message ring on phoenix family of processors connects the cpus, gmacs, xgmac/spi4,
   36  * security engine and the general purpose DMA engines. It provides a high bandwidth,
   37  * low latency communication links. On traditional processors, this communication goes through
   38  * which inherently does not scale very well with increasing number of cpus. 
   39  * 
   40  * Message ring has an in-built flow control mechanism. Every agent/station on the ring has to
   41  * have software configured credits to send messages to any agent. Every receiving agent on the
   42  * ring has a 256 entry FIFO that can divided into "buckets". All addressing on the ring is 
   43  * in terms of buckets. There are a total 128 buckets on the ring. The total number of credits 
   44  * across all sending agents should not exceed the bucket size. 
   45  *
   46  * Below are the receiving agents and the max number of buckets they can have
   47  *      CPU 0   : 8 buckets
   48  *      CPU 1   : 8 buckets
   49  *      CPU 2   : 8 buckets
   50  *      CPU 3   : 8 buckets
   51  *      CPU 4   : 8 buckets
   52  *      CPU 5   : 8 buckets
   53  *      CPU 6   : 8 buckets
   54  *      CPU 7   : 8 buckets
   55  * 
   56  *      XGMAC 0 / SPI4 0
   57  *                       TX     :       16 buckets
   58  *                       FREE   :       2  buckets
   59  *      XGMAC 1 / SPI4 1
   60  *                       TX     :       16 buckets
   61  *                       FREE   :       2  buckets
   62  * 
   63  *      GMAC    : 8 buckets     
   64  *      
   65  *      SEC     : 8 buckets
   66  * 
   67  *      DMA     : 8 buckets
   68  *
   69  * The bucket size of a bucket should be aligned to the bucket's starting index in that
   70  * receiving station's FIFO. For example, if sizes of bucket0 and bucket1 of a station 
   71  * are 32 and 32, bucket2's size has to be 64. bucket size 0 is valid.
   72  *
   73  * The format of the file is pretty straight forward. Each bucket definition has the size
   74  * and the list of sending agents to that bucket with the number of credits to send.
   75  * 
   76  * Undefined buckets have a size of 0 and Tx stations have 0 credits to send to that bucket.
   77  *
   78  *  Following are the currently supported bucket names
   79  *  cpu_0_0
   80  *  cpu_0_1
   81  *  cpu_0_2
   82  *  cpu_0_3
   83  *  cpu_0_4
   84  *  cpu_0_5
   85  *  cpu_0_6
   86  *  cpu_0_7
   87  *  
   88  *  cpu_1_0
   89  *  cpu_1_1
   90  *  cpu_1_2
   91  *  cpu_1_3
   92  *  cpu_1_4
   93  *  cpu_1_5
   94  *  cpu_1_6
   95  *  cpu_1_7
   96  *  
   97  *  cpu_2_0
   98  *  cpu_2_1
   99  *  cpu_2_2
  100  *  cpu_2_3
  101  *  cpu_2_4
  102  *  cpu_2_5
  103  *  cpu_2_6
  104  *  cpu_2_7
  105  *  
  106  *  cpu_3_0
  107  *  cpu_3_1
  108  *  cpu_3_2
  109  *  cpu_3_3
  110  *  cpu_3_4
  111  *  cpu_3_5
  112  *  cpu_3_6
  113  *  cpu_3_7
  114  *  
  115  *  cpu_4_0
  116  *  cpu_4_1
  117  *  cpu_4_2
  118  *  cpu_4_3
  119  *  cpu_4_4
  120  *  cpu_4_5
  121  *  cpu_4_6
  122  *  cpu_4_7
  123  *  
  124  *  cpu_5_0
  125  *  cpu_5_1
  126  *  cpu_5_2
  127  *  cpu_5_3
  128  *  cpu_5_4
  129  *  cpu_5_5
  130  *  cpu_5_6
  131  *  cpu_5_7
  132  *  
  133  *  cpu_6_0
  134  *  cpu_6_1
  135  *  cpu_6_2
  136  *  cpu_6_3
  137  *  cpu_6_4
  138  *  cpu_6_5
  139  *  cpu_6_6
  140  *  cpu_6_7
  141  *  
  142  *  cpu_7_0
  143  *  cpu_7_1
  144  *  cpu_7_2
  145  *  cpu_7_3
  146  *  cpu_7_4
  147  *  cpu_7_5
  148  *  cpu_7_6
  149  *  cpu_7_7
  150  *
  151  *  xgs_0_tx_0
  152  *  xgs_0_tx_1
  153  *  xgs_0_tx_2
  154  *  xgs_0_tx_3
  155  *  xgs_0_tx_4
  156  *  xgs_0_tx_5
  157  *  xgs_0_tx_6
  158  *  xgs_0_tx_7
  159  *  xgs_0_tx_8
  160  *  xgs_0_tx_9
  161  *  xgs_0_tx_10
  162  *  xgs_0_tx_11
  163  *  xgs_0_tx_12
  164  *  xgs_0_tx_13
  165  *  xgs_0_tx_14
  166  *  xgs_0_tx_15
  167  *
  168  *  xgs_1_tx_0
  169  *  xgs_1_tx_1
  170  *  xgs_1_tx_2
  171  *  xgs_1_tx_3
  172  *  xgs_1_tx_4
  173  *  xgs_1_tx_5
  174  *  xgs_1_tx_6
  175  *  xgs_1_tx_7
  176  *  xgs_1_tx_8
  177  *  xgs_1_tx_9
  178  *  xgs_1_tx_10
  179  *  xgs_1_tx_11
  180  *  xgs_1_tx_12
  181  *  xgs_1_tx_13
  182  *  xgs_1_tx_14
  183  *  xgs_1_tx_15
  184  *
  185  *  gmac_rsvd_0
  186  *  gmac_rfr_0
  187  *  gmac_tx_0
  188  *  gmac_tx_1
  189  *  gmac_tx_2
  190  *  gmac_tx_3
  191  *  gmac_rsvd_1
  192  *  gmac_rfr_1
  193  *
  194  *  xgs_0_rsvd
  195  *  xgs_0_rfr
  196  *
  197  *  xgs_1_rsvd
  198  *  xgs_1_rfr
  199  *
  200  *  sec_pipe_0
  201  *  sec_pipe_1
  202  *  sec_pipe_2
  203  *  sec_pipe_3
  204  *  sec_rsa
  205  *
  206  * Following are the currently supported Tx Agent/Station names
  207  *
  208  *   tx_stn_cpu_0
  209  *  tx_stn_cpu_1
  210  *  tx_stn_cpu_2
  211  *  tx_stn_cpu_3
  212  *  tx_stn_cpu_4
  213  *  tx_stn_cpu_5
  214  *  tx_stn_cpu_6
  215  *  tx_stn_cpu_7
  216  *
  217  *   tx_stn_xgs_0
  218  *  tx_stn_xgs_1
  219  *
  220  *   tx_stn_gmac
  221  *
  222  *   tx_stn_dma
  223  *
  224  *   tx_stn_sec
  225  *
  226  *
  227  * 
  228  */
  229 
  230 /*************************************************************/
  231 // CPU_0 Message Station 
  232 
  233 bucket "cpu_0_0" { 
  234         size 32;
  235         "tx_stn_xgs_0" 8;
  236         "tx_stn_xgs_1" 8;
  237         "tx_stn_gmac" 8;
  238         "tx_stn_sec"  8;
  239 }
  240 bucket "cpu_0_1" { 
  241         size 32; 
  242         "tx_stn_xgs_0" 8;
  243         "tx_stn_xgs_1" 8;
  244         "tx_stn_gmac" 8;
  245         "tx_stn_sec"  8;
  246 }
  247 bucket "cpu_0_2" { 
  248         size 32; 
  249         "tx_stn_xgs_0" 8;
  250         "tx_stn_xgs_1" 8;
  251         "tx_stn_gmac" 8;
  252         "tx_stn_sec"  8;
  253 }
  254 bucket "cpu_0_3" { 
  255         size 32; 
  256         "tx_stn_xgs_0" 8;
  257         "tx_stn_xgs_1" 8;
  258         "tx_stn_gmac" 8;
  259         "tx_stn_sec"  8;
  260 }
  261 bucket "cpu_0_4" {
  262         size 32;
  263         "tx_stn_gmac" 16;
  264         "tx_stn_xgs_0" 8;
  265         "tx_stn_xgs_1" 8;
  266 }
  267 bucket "cpu_0_5" {
  268         size 32;
  269         "tx_stn_gmac" 16;
  270         "tx_stn_xgs_0" 8;
  271         "tx_stn_xgs_1" 8;
  272 }
  273 bucket "cpu_0_6" {
  274         size 32;
  275         "tx_stn_gmac" 16;
  276         "tx_stn_xgs_0" 8;
  277         "tx_stn_xgs_1" 8;
  278 }
  279 bucket "cpu_0_7" {
  280         size 32;
  281         "tx_stn_gmac" 16;
  282         "tx_stn_xgs_0" 8;
  283         "tx_stn_xgs_1" 8;
  284 }
  285 
  286 /*************************************************************/
  287 // CPU_1 Message Station 
  288 
  289 bucket "cpu_1_0" { 
  290         size 32;
  291         "tx_stn_xgs_0" 8;
  292         "tx_stn_xgs_1" 8;
  293         "tx_stn_gmac" 8;
  294         "tx_stn_sec"  8;
  295 }
  296 bucket "cpu_1_1" { 
  297         size 32; 
  298         "tx_stn_xgs_0" 8;
  299         "tx_stn_xgs_1" 8;
  300         "tx_stn_gmac" 8;
  301         "tx_stn_sec"  8;
  302 }
  303 bucket "cpu_1_2" { 
  304         size 32; 
  305         "tx_stn_xgs_0" 8;
  306         "tx_stn_xgs_1" 8;
  307         "tx_stn_gmac" 8;
  308         "tx_stn_sec"  8;
  309 }
  310 bucket "cpu_1_3" { 
  311         size 32; 
  312         "tx_stn_xgs_0" 8;
  313         "tx_stn_xgs_1" 8;
  314         "tx_stn_gmac" 8;
  315         "tx_stn_sec"  4;
  316     "tx_stn_cpu_0" 4; /* NEEDED BY RMIOS IPSEC */
  317 }
  318 bucket "cpu_1_4" {
  319         size 32;
  320         "tx_stn_gmac" 16;
  321         "tx_stn_xgs_0" 8;
  322         "tx_stn_xgs_1" 8;
  323 }
  324 bucket "cpu_1_5" {
  325         size 32;
  326         "tx_stn_gmac" 16;
  327         "tx_stn_xgs_0" 8;
  328         "tx_stn_xgs_1" 8;
  329 }
  330 bucket "cpu_1_6" {
  331         size 32;
  332         "tx_stn_gmac" 16;
  333         "tx_stn_xgs_0" 8;
  334         "tx_stn_xgs_1" 8;
  335 }
  336 bucket "cpu_1_7" {
  337         size 32;
  338         "tx_stn_gmac" 16;
  339         "tx_stn_xgs_0" 8;
  340         "tx_stn_xgs_1" 8;
  341 }
  342 
  343 /*************************************************************/
  344 // CPU_2 Message Station 
  345 
  346 bucket "cpu_2_0" { 
  347         size 32;
  348         "tx_stn_xgs_0" 8;
  349         "tx_stn_xgs_1" 8;
  350         "tx_stn_gmac" 8;
  351         "tx_stn_sec"  8;
  352 }
  353 bucket "cpu_2_1" { 
  354         size 32; 
  355         "tx_stn_xgs_0" 8;
  356         "tx_stn_xgs_1" 8;
  357         "tx_stn_gmac" 8;
  358         "tx_stn_sec"  8;
  359 }
  360 bucket "cpu_2_2" { 
  361         size 32; 
  362         "tx_stn_xgs_0" 8;
  363         "tx_stn_xgs_1" 8;
  364         "tx_stn_gmac" 8;
  365         "tx_stn_sec"  8;
  366 }
  367 bucket "cpu_2_3" { 
  368         size 32; 
  369         "tx_stn_xgs_0" 8;
  370         "tx_stn_xgs_1" 8;
  371         "tx_stn_gmac" 8;
  372         "tx_stn_sec"  8;
  373 }
  374 bucket "cpu_2_4" {
  375         size 32;
  376         "tx_stn_gmac" 16;
  377         "tx_stn_xgs_0" 8;
  378         "tx_stn_xgs_1" 8;
  379 }
  380 bucket "cpu_2_5" {
  381         size 32;
  382         "tx_stn_gmac" 16;
  383         "tx_stn_xgs_0" 8;
  384         "tx_stn_xgs_1" 8;
  385 }
  386 bucket "cpu_2_6" {
  387         size 32;
  388         "tx_stn_gmac" 16;
  389         "tx_stn_xgs_0" 8;
  390         "tx_stn_xgs_1" 8;
  391 }
  392 bucket "cpu_2_7" {
  393         size 32;
  394         "tx_stn_gmac" 16;
  395         "tx_stn_xgs_0" 8;
  396         "tx_stn_xgs_1" 8;
  397 }
  398 
  399 /*************************************************************/
  400 // CPU_3 Message Station 
  401 
  402 bucket "cpu_3_0" { 
  403         size 32;
  404         "tx_stn_xgs_0" 8;
  405         "tx_stn_xgs_1" 8;
  406         "tx_stn_gmac" 8;
  407         "tx_stn_sec"  8;
  408 }
  409 bucket "cpu_3_1" { 
  410         size 32; 
  411         "tx_stn_xgs_0" 8;
  412         "tx_stn_xgs_1" 8;
  413         "tx_stn_gmac" 8;
  414         "tx_stn_sec"  8;
  415 }
  416 bucket "cpu_3_2" { 
  417         size 32; 
  418         "tx_stn_xgs_0" 8;
  419         "tx_stn_xgs_1" 8;
  420         "tx_stn_gmac" 8;
  421         "tx_stn_sec"  8;
  422 }
  423 bucket "cpu_3_3" { 
  424         size 32; 
  425         "tx_stn_xgs_0" 8;
  426         "tx_stn_xgs_1" 8;
  427         "tx_stn_gmac" 8;
  428         "tx_stn_sec"  8;
  429 }
  430 bucket "cpu_3_4" {
  431         size 32;
  432         "tx_stn_gmac" 16;
  433         "tx_stn_xgs_0" 8;
  434         "tx_stn_xgs_1" 8;
  435 }
  436 bucket "cpu_3_5" {
  437         size 32;
  438         "tx_stn_gmac" 16;
  439         "tx_stn_xgs_0" 8;
  440         "tx_stn_xgs_1" 8;
  441 }
  442 bucket "cpu_3_6" {
  443         size 32;
  444         "tx_stn_gmac" 16;
  445         "tx_stn_xgs_0" 8;
  446         "tx_stn_xgs_1" 8;
  447 }
  448 bucket "cpu_3_7" {
  449         size 32;
  450         "tx_stn_gmac" 16;
  451         "tx_stn_xgs_0" 8;
  452         "tx_stn_xgs_1" 8;
  453 }
  454 
  455 /*************************************************************/
  456 // CPU_4 Message Station 
  457 
  458 bucket "cpu_4_0" { 
  459         size 32;
  460         "tx_stn_xgs_0" 8;
  461         "tx_stn_xgs_1" 8;
  462         "tx_stn_gmac" 8;
  463         "tx_stn_sec"  8;
  464 }
  465 bucket "cpu_4_1" { 
  466         size 32; 
  467         "tx_stn_xgs_0" 8;
  468         "tx_stn_xgs_1" 8;
  469         "tx_stn_gmac" 8;
  470         "tx_stn_sec"  8;
  471 }
  472 bucket "cpu_4_2" { 
  473         size 32; 
  474         "tx_stn_xgs_0" 8;
  475         "tx_stn_xgs_1" 8;
  476         "tx_stn_gmac" 8;
  477         "tx_stn_sec"  8;
  478 }
  479 bucket "cpu_4_3" { 
  480         size 32; 
  481         "tx_stn_xgs_0" 8;
  482         "tx_stn_xgs_1" 8;
  483         "tx_stn_gmac" 8;
  484         "tx_stn_sec"  8;
  485 }
  486 bucket "cpu_4_4" {
  487         size 32;
  488         "tx_stn_gmac" 16;
  489         "tx_stn_xgs_0" 8;
  490         "tx_stn_xgs_1" 8;
  491 }
  492 bucket "cpu_4_5" {
  493         size 32;
  494         "tx_stn_gmac" 16;
  495         "tx_stn_xgs_0" 8;
  496         "tx_stn_xgs_1" 8;
  497 }
  498 bucket "cpu_4_6" {
  499         size 32;
  500         "tx_stn_gmac" 16;
  501         "tx_stn_xgs_0" 8;
  502         "tx_stn_xgs_1" 8;
  503 }
  504 bucket "cpu_4_7" {
  505         size 32;
  506         "tx_stn_gmac" 16;
  507         "tx_stn_xgs_0" 8;
  508         "tx_stn_xgs_1" 8;
  509 }
  510 
  511 /*************************************************************/
  512 // CPU_5 Message Station 
  513 
  514 bucket "cpu_5_0" { 
  515         size 32;
  516         "tx_stn_xgs_0" 8;
  517         "tx_stn_xgs_1" 8;
  518         "tx_stn_gmac" 8;
  519         "tx_stn_sec"  8;
  520 }
  521 bucket "cpu_5_1" { 
  522         size 32; 
  523         "tx_stn_xgs_0" 8;
  524         "tx_stn_xgs_1" 8;
  525         "tx_stn_gmac" 8;
  526         "tx_stn_sec"  8;
  527 }
  528 bucket "cpu_5_2" { 
  529         size 32; 
  530         "tx_stn_xgs_0" 8;
  531         "tx_stn_xgs_1" 8;
  532         "tx_stn_gmac" 8;
  533         "tx_stn_sec"  8;
  534 }
  535 bucket "cpu_5_3" { 
  536         size 32; 
  537         "tx_stn_xgs_0" 8;
  538         "tx_stn_xgs_1" 8;
  539         "tx_stn_gmac" 8;
  540         "tx_stn_sec"  8;
  541 }
  542 bucket "cpu_5_4" {
  543         size 32;
  544         "tx_stn_gmac" 16;
  545         "tx_stn_xgs_0" 8;
  546         "tx_stn_xgs_1" 8;
  547 }
  548 bucket "cpu_5_5" {
  549         size 32;
  550         "tx_stn_gmac" 16;
  551         "tx_stn_xgs_0" 8;
  552         "tx_stn_xgs_1" 8;
  553 }
  554 bucket "cpu_5_6" {
  555         size 32;
  556         "tx_stn_gmac" 16;
  557         "tx_stn_xgs_0" 8;
  558         "tx_stn_xgs_1" 8;
  559 }
  560 bucket "cpu_5_7" {
  561         size 32;
  562         "tx_stn_gmac" 16;
  563         "tx_stn_xgs_0" 8;
  564         "tx_stn_xgs_1" 8;
  565 }
  566 
  567 
  568 /*************************************************************/
  569 // CPU_6 Message Station 
  570 
  571 bucket "cpu_6_0" { 
  572         size 32;
  573         "tx_stn_xgs_0" 8;
  574         "tx_stn_xgs_1" 8;
  575         "tx_stn_gmac" 8;
  576         "tx_stn_sec"  8;
  577 }
  578 bucket "cpu_6_1" { 
  579         size 32; 
  580         "tx_stn_xgs_0" 8;
  581         "tx_stn_xgs_1" 8;
  582         "tx_stn_gmac" 8;
  583         "tx_stn_sec"  8;
  584 }
  585 bucket "cpu_6_2" { 
  586         size 32; 
  587         "tx_stn_xgs_0" 8;
  588         "tx_stn_xgs_1" 8;
  589         "tx_stn_gmac" 8;
  590         "tx_stn_sec"  8;
  591 }
  592 bucket "cpu_6_3" { 
  593         size 32; 
  594         "tx_stn_xgs_0" 8;
  595         "tx_stn_xgs_1" 8;
  596         "tx_stn_gmac" 8;
  597         "tx_stn_sec"  8;
  598 }
  599 bucket "cpu_6_4" {
  600         size 32;
  601         "tx_stn_gmac" 16;
  602         "tx_stn_xgs_0" 8;
  603         "tx_stn_xgs_1" 8;
  604 }
  605 bucket "cpu_6_5" {
  606         size 32;
  607         "tx_stn_gmac" 16;
  608         "tx_stn_xgs_0" 8;
  609         "tx_stn_xgs_1" 8;
  610 }
  611 bucket "cpu_6_6" {
  612         size 32;
  613         "tx_stn_gmac" 16;
  614         "tx_stn_xgs_0" 8;
  615         "tx_stn_xgs_1" 8;
  616 }
  617 bucket "cpu_6_7" {
  618         size 32;
  619         "tx_stn_gmac" 16;
  620         "tx_stn_xgs_0" 8;
  621         "tx_stn_xgs_1" 8;
  622 }
  623 
  624 
  625 /*************************************************************/
  626 // CPU_7 Message Station 
  627 
  628 bucket "cpu_7_0" { 
  629         size 32;
  630         "tx_stn_xgs_0" 8;
  631         "tx_stn_xgs_1" 8;
  632         "tx_stn_gmac" 8;
  633         "tx_stn_sec"  8;
  634 }
  635 bucket "cpu_7_1" { 
  636         size 32; 
  637         "tx_stn_xgs_0" 8;
  638         "tx_stn_xgs_1" 8;
  639         "tx_stn_gmac" 8;
  640         "tx_stn_sec"  8;
  641 }
  642 bucket "cpu_7_2" { 
  643         size 32; 
  644         "tx_stn_xgs_0" 8;
  645         "tx_stn_xgs_1" 8;
  646         "tx_stn_gmac" 8;
  647         "tx_stn_sec"  8;
  648 }
  649 bucket "cpu_7_3" { 
  650         size 32; 
  651         "tx_stn_xgs_0" 8;
  652         "tx_stn_xgs_1" 8;
  653         "tx_stn_gmac" 8;
  654         "tx_stn_sec"  8;
  655 }
  656 bucket "cpu_7_4" {
  657         size 32;
  658         "tx_stn_gmac" 16;
  659         "tx_stn_xgs_0" 8;
  660         "tx_stn_xgs_1" 8;
  661 }
  662 bucket "cpu_7_5" {
  663         size 32;
  664         "tx_stn_gmac" 16;
  665         "tx_stn_xgs_0" 8;
  666         "tx_stn_xgs_1" 8;
  667 }
  668 bucket "cpu_7_6" {
  669         size 32;
  670         "tx_stn_gmac" 16;
  671         "tx_stn_xgs_0" 8;
  672         "tx_stn_xgs_1" 8;
  673 }
  674 bucket "cpu_7_7" {
  675         size 32;
  676         "tx_stn_gmac" 16;
  677         "tx_stn_xgs_0" 8;
  678         "tx_stn_xgs_1" 8;
  679 }
  680 
  681 
  682 /*************************************************************/
  683 // GMAC Message Station 
  684 
  685 bucket "gmac_rfr_0" {
  686         size 32;
  687         "tx_stn_cpu_0" 2;
  688         "tx_stn_cpu_1" 2;
  689         "tx_stn_cpu_2" 4;
  690         "tx_stn_cpu_3" 4;
  691         "tx_stn_cpu_4" 4;
  692         "tx_stn_cpu_5" 4;
  693         "tx_stn_cpu_6" 4;
  694         "tx_stn_cpu_7" 4;
  695         "tx_stn_gmac" 4;
  696 }
  697 
  698 bucket "gmac_tx_0" {
  699         size 32;
  700         "tx_stn_cpu_0" 4;
  701         "tx_stn_cpu_1" 4;
  702         "tx_stn_cpu_2" 4;
  703         "tx_stn_cpu_3" 4;
  704         "tx_stn_cpu_4" 4;
  705         "tx_stn_cpu_5" 4;
  706         "tx_stn_cpu_6" 4;
  707         "tx_stn_cpu_7" 4;
  708 }
  709 
  710 bucket "gmac_tx_1" {
  711         size 32;
  712         "tx_stn_cpu_0" 4;
  713         "tx_stn_cpu_1" 4;
  714         "tx_stn_cpu_2" 4;
  715         "tx_stn_cpu_3" 4;
  716         "tx_stn_cpu_4" 4;
  717         "tx_stn_cpu_5" 4;
  718         "tx_stn_cpu_6" 4;
  719         "tx_stn_cpu_7" 4;
  720 }
  721 
  722 bucket "gmac_tx_2" {
  723         size 32;
  724         "tx_stn_cpu_0" 4;
  725         "tx_stn_cpu_1" 4;
  726         "tx_stn_cpu_2" 4;
  727         "tx_stn_cpu_3" 4;
  728         "tx_stn_cpu_4" 4;
  729         "tx_stn_cpu_5" 4;
  730         "tx_stn_cpu_6" 4;
  731         "tx_stn_cpu_7" 4;
  732 }
  733 
  734 bucket "gmac_tx_3" {
  735         size 32;
  736         "tx_stn_cpu_0" 4;
  737         "tx_stn_cpu_1" 4;
  738         "tx_stn_cpu_2" 4;
  739         "tx_stn_cpu_3" 4;
  740         "tx_stn_cpu_4" 4;
  741         "tx_stn_cpu_5" 4;
  742         "tx_stn_cpu_6" 4;
  743         "tx_stn_cpu_7" 4;
  744 }
  745 
  746 bucket "gmac_rfr_1" {
  747         size 32;
  748         "tx_stn_cpu_0" 2;
  749         "tx_stn_cpu_1" 2;
  750         "tx_stn_cpu_2" 4;
  751         "tx_stn_cpu_3" 4;
  752         "tx_stn_cpu_4" 4;
  753         "tx_stn_cpu_5" 4;
  754         "tx_stn_cpu_6" 4;
  755         "tx_stn_cpu_7" 4;
  756         "tx_stn_gmac" 4;
  757 }
  758 /*********************************************/
  759 // xgmac
  760 bucket "xgs_0_rfr" {
  761     size 32;
  762     "tx_stn_cpu_0" 2;
  763     "tx_stn_cpu_1" 2;
  764     "tx_stn_cpu_2" 4;
  765     "tx_stn_cpu_3" 4;
  766     "tx_stn_cpu_4" 4;
  767     "tx_stn_cpu_5" 4;
  768     "tx_stn_cpu_6" 4;
  769     "tx_stn_cpu_7" 4;
  770     "tx_stn_xgs_0" 4;
  771 }
  772 
  773 bucket "xgs_0_tx_0" {
  774     size 32;
  775     "tx_stn_cpu_0" 4;
  776     "tx_stn_cpu_1" 4;
  777     "tx_stn_cpu_2" 4;
  778     "tx_stn_cpu_3" 4;
  779     "tx_stn_cpu_4" 4;
  780     "tx_stn_cpu_5" 4;
  781     "tx_stn_cpu_6" 4;
  782     "tx_stn_cpu_7" 4;
  783 }
  784 
  785 bucket "xgs_0_tx_1" {
  786   size 16;
  787   "tx_stn_cpu_0" 2;
  788   "tx_stn_cpu_1" 2;
  789   "tx_stn_cpu_2" 2;
  790   "tx_stn_cpu_3" 2;
  791   "tx_stn_cpu_4" 2;
  792   "tx_stn_cpu_5" 2;
  793   "tx_stn_cpu_6" 2;
  794   "tx_stn_cpu_7" 2;
  795 }
  796 
  797 bucket "xgs_0_tx_2" {
  798   size 16;
  799   "tx_stn_cpu_0" 2;
  800   "tx_stn_cpu_1" 2;
  801   "tx_stn_cpu_2" 2;
  802   "tx_stn_cpu_3" 2;
  803   "tx_stn_cpu_4" 2;
  804   "tx_stn_cpu_5" 2;
  805   "tx_stn_cpu_6" 2;
  806   "tx_stn_cpu_7" 2;
  807 }
  808 
  809 bucket "xgs_0_tx_3" {
  810   size 16;
  811   "tx_stn_cpu_0" 2;
  812   "tx_stn_cpu_1" 2;
  813   "tx_stn_cpu_2" 2;
  814   "tx_stn_cpu_3" 2;
  815   "tx_stn_cpu_4" 2;
  816   "tx_stn_cpu_5" 2;
  817   "tx_stn_cpu_6" 2;
  818   "tx_stn_cpu_7" 2;
  819 }
  820 
  821 bucket "xgs_0_tx_4" {
  822   size 16;
  823   "tx_stn_cpu_0" 2;
  824   "tx_stn_cpu_1" 2;
  825   "tx_stn_cpu_2" 2;
  826   "tx_stn_cpu_3" 2;
  827   "tx_stn_cpu_4" 2;
  828   "tx_stn_cpu_5" 2;
  829   "tx_stn_cpu_6" 2;
  830   "tx_stn_cpu_7" 2;
  831 }
  832 bucket "xgs_0_tx_5" {
  833   size 16;
  834   "tx_stn_cpu_0" 2;
  835   "tx_stn_cpu_1" 2;
  836   "tx_stn_cpu_2" 2;
  837   "tx_stn_cpu_3" 2;
  838   "tx_stn_cpu_4" 2;
  839   "tx_stn_cpu_5" 2;
  840   "tx_stn_cpu_6" 2;
  841   "tx_stn_cpu_7" 2;
  842 }
  843 
  844 bucket "xgs_0_tx_6" {
  845   size 16;
  846   "tx_stn_cpu_0" 2;
  847   "tx_stn_cpu_1" 2;
  848   "tx_stn_cpu_2" 2;
  849   "tx_stn_cpu_3" 2;
  850   "tx_stn_cpu_4" 2;
  851   "tx_stn_cpu_5" 2;
  852   "tx_stn_cpu_6" 2;
  853   "tx_stn_cpu_7" 2;
  854 }
  855 
  856 bucket "xgs_0_tx_7" {
  857   size 16;
  858   "tx_stn_cpu_0" 2;
  859   "tx_stn_cpu_1" 2;
  860   "tx_stn_cpu_2" 2;
  861   "tx_stn_cpu_3" 2;
  862   "tx_stn_cpu_4" 2;
  863   "tx_stn_cpu_5" 2;
  864   "tx_stn_cpu_6" 2;
  865   "tx_stn_cpu_7" 2;
  866 }
  867 
  868 bucket "xgs_0_tx_8" {
  869   size 16;
  870   "tx_stn_cpu_0" 2;
  871   "tx_stn_cpu_1" 2;
  872   "tx_stn_cpu_2" 2;
  873   "tx_stn_cpu_3" 2;
  874   "tx_stn_cpu_4" 2;
  875   "tx_stn_cpu_5" 2;
  876   "tx_stn_cpu_6" 2;
  877   "tx_stn_cpu_7" 2;
  878 }
  879 
  880 bucket "xgs_0_tx_9" {
  881   size 16;
  882   "tx_stn_cpu_0" 2;
  883   "tx_stn_cpu_1" 2;
  884   "tx_stn_cpu_2" 2;
  885   "tx_stn_cpu_3" 2;
  886   "tx_stn_cpu_4" 2;
  887   "tx_stn_cpu_5" 2;
  888   "tx_stn_cpu_6" 2;
  889   "tx_stn_cpu_7" 2;
  890 }
  891 
  892 bucket "xgs_0_tx_10" {
  893   size 16;
  894   "tx_stn_cpu_0" 2;
  895   "tx_stn_cpu_1" 2;
  896   "tx_stn_cpu_2" 2;
  897   "tx_stn_cpu_3" 2;
  898   "tx_stn_cpu_4" 2;
  899   "tx_stn_cpu_5" 2;
  900   "tx_stn_cpu_6" 2;
  901   "tx_stn_cpu_7" 2;
  902 }
  903 
  904 
  905 bucket "xgs_0_tx_11" {
  906   size 16;
  907   "tx_stn_cpu_0" 2;
  908   "tx_stn_cpu_1" 2;
  909   "tx_stn_cpu_2" 2;
  910   "tx_stn_cpu_3" 2;
  911   "tx_stn_cpu_4" 2;
  912   "tx_stn_cpu_5" 2;
  913   "tx_stn_cpu_6" 2;
  914   "tx_stn_cpu_7" 2;
  915 }
  916 
  917 bucket "xgs_0_tx_12" {
  918   size 16;
  919   "tx_stn_cpu_0" 2;
  920   "tx_stn_cpu_1" 2;
  921   "tx_stn_cpu_2" 2;
  922   "tx_stn_cpu_3" 2;
  923   "tx_stn_cpu_4" 2;
  924   "tx_stn_cpu_5" 2;
  925   "tx_stn_cpu_6" 2;
  926   "tx_stn_cpu_7" 2;
  927 }
  928 
  929 bucket "xgs_0_tx_13" {
  930   size 16;
  931   "tx_stn_cpu_0" 2;
  932   "tx_stn_cpu_1" 2;
  933   "tx_stn_cpu_2" 2;
  934   "tx_stn_cpu_3" 2;
  935   "tx_stn_cpu_4" 2;
  936   "tx_stn_cpu_5" 2;
  937   "tx_stn_cpu_6" 2;
  938   "tx_stn_cpu_7" 2;
  939 }
  940 
  941 bucket "xgs_0_tx_14" {
  942   size 16;
  943   "tx_stn_cpu_0" 2;
  944   "tx_stn_cpu_1" 2;
  945   "tx_stn_cpu_2" 2;
  946   "tx_stn_cpu_3" 2;
  947   "tx_stn_cpu_4" 2;
  948   "tx_stn_cpu_5" 2;
  949   "tx_stn_cpu_6" 2;
  950   "tx_stn_cpu_7" 2;
  951 }
  952 
  953 
  954 bucket "xgs_1_rfr" {
  955     size 32;
  956     "tx_stn_cpu_0" 2;
  957     "tx_stn_cpu_1" 2;
  958     "tx_stn_cpu_2" 4;
  959     "tx_stn_cpu_3" 4;
  960     "tx_stn_cpu_4" 4;
  961     "tx_stn_cpu_5" 4;
  962     "tx_stn_cpu_6" 4;
  963     "tx_stn_cpu_7" 4;
  964     "tx_stn_xgs_1" 4;
  965 }
  966 
  967 bucket "xgs_1_tx_0" {
  968     size 32;
  969     "tx_stn_cpu_0" 4;
  970     "tx_stn_cpu_1" 4;
  971     "tx_stn_cpu_2" 4;
  972     "tx_stn_cpu_3" 4;
  973     "tx_stn_cpu_4" 4;
  974     "tx_stn_cpu_5" 4;
  975     "tx_stn_cpu_6" 4;
  976     "tx_stn_cpu_7" 4;
  977 }
  978 
  979 
  980 bucket "xgs_1_tx_1" {
  981   size 16;
  982   "tx_stn_cpu_0" 2;
  983   "tx_stn_cpu_1" 2;
  984   "tx_stn_cpu_2" 2;
  985   "tx_stn_cpu_3" 2;
  986   "tx_stn_cpu_4" 2;
  987   "tx_stn_cpu_5" 2;
  988   "tx_stn_cpu_6" 2;
  989   "tx_stn_cpu_7" 2;
  990 }
  991 
  992 bucket "xgs_1_tx_2" {
  993   size 16;
  994   "tx_stn_cpu_0" 2;
  995   "tx_stn_cpu_1" 2;
  996   "tx_stn_cpu_2" 2;
  997   "tx_stn_cpu_3" 2;
  998   "tx_stn_cpu_4" 2;
  999   "tx_stn_cpu_5" 2;
 1000   "tx_stn_cpu_6" 2;
 1001   "tx_stn_cpu_7" 2;
 1002 }
 1003 
 1004 bucket "xgs_1_tx_3" {
 1005   size 16;
 1006   "tx_stn_cpu_0" 2;
 1007   "tx_stn_cpu_1" 2;
 1008   "tx_stn_cpu_2" 2;
 1009   "tx_stn_cpu_3" 2;
 1010   "tx_stn_cpu_4" 2;
 1011   "tx_stn_cpu_5" 2;
 1012   "tx_stn_cpu_6" 2;
 1013   "tx_stn_cpu_7" 2;
 1014 }
 1015 
 1016 bucket "xgs_1_tx_4" {
 1017   size 16;
 1018   "tx_stn_cpu_0" 2;
 1019   "tx_stn_cpu_1" 2;
 1020   "tx_stn_cpu_2" 2;
 1021   "tx_stn_cpu_3" 2;
 1022   "tx_stn_cpu_4" 2;
 1023   "tx_stn_cpu_5" 2;
 1024   "tx_stn_cpu_6" 2;
 1025   "tx_stn_cpu_7" 2;
 1026 }
 1027 
 1028 bucket "xgs_1_tx_5" {
 1029   size 16;
 1030   "tx_stn_cpu_0" 2;
 1031   "tx_stn_cpu_1" 2;
 1032   "tx_stn_cpu_2" 2;
 1033   "tx_stn_cpu_3" 2;
 1034   "tx_stn_cpu_4" 2;
 1035   "tx_stn_cpu_5" 2;
 1036   "tx_stn_cpu_6" 2;
 1037   "tx_stn_cpu_7" 2;
 1038 }
 1039 
 1040 bucket "xgs_1_tx_6" {
 1041   size 16;
 1042   "tx_stn_cpu_0" 2;
 1043   "tx_stn_cpu_1" 2;
 1044   "tx_stn_cpu_2" 2;
 1045   "tx_stn_cpu_3" 2;
 1046   "tx_stn_cpu_4" 2;
 1047   "tx_stn_cpu_5" 2;
 1048   "tx_stn_cpu_6" 2;
 1049   "tx_stn_cpu_7" 2;
 1050 }
 1051 
 1052 bucket "xgs_1_tx_7" {
 1053   size 16;
 1054   "tx_stn_cpu_0" 2;
 1055   "tx_stn_cpu_1" 2;
 1056   "tx_stn_cpu_2" 2;
 1057   "tx_stn_cpu_3" 2;
 1058   "tx_stn_cpu_4" 2;
 1059   "tx_stn_cpu_5" 2;
 1060   "tx_stn_cpu_6" 2;
 1061   "tx_stn_cpu_7" 2;
 1062 }
 1063 
 1064 
 1065 bucket "xgs_1_tx_8" {
 1066   size 16;
 1067   "tx_stn_cpu_0" 2;
 1068   "tx_stn_cpu_1" 2;
 1069   "tx_stn_cpu_2" 2;
 1070   "tx_stn_cpu_3" 2;
 1071   "tx_stn_cpu_4" 2;
 1072   "tx_stn_cpu_5" 2;
 1073   "tx_stn_cpu_6" 2;
 1074   "tx_stn_cpu_7" 2;
 1075 }
 1076 
 1077 
 1078 bucket "xgs_1_tx_9" {
 1079   size 16;
 1080   "tx_stn_cpu_0" 2;
 1081   "tx_stn_cpu_1" 2;
 1082   "tx_stn_cpu_2" 2;
 1083   "tx_stn_cpu_3" 2;
 1084   "tx_stn_cpu_4" 2;
 1085   "tx_stn_cpu_5" 2;
 1086   "tx_stn_cpu_6" 2;
 1087   "tx_stn_cpu_7" 2;
 1088 }
 1089 
 1090 
 1091 bucket "xgs_1_tx_10" {
 1092   size 16;
 1093   "tx_stn_cpu_0" 2;
 1094   "tx_stn_cpu_1" 2;
 1095   "tx_stn_cpu_2" 2;
 1096   "tx_stn_cpu_3" 2;
 1097   "tx_stn_cpu_4" 2;
 1098   "tx_stn_cpu_5" 2;
 1099   "tx_stn_cpu_6" 2;
 1100   "tx_stn_cpu_7" 2;
 1101 }
 1102 
 1103 bucket "xgs_1_tx_11" {
 1104   size 16;
 1105   "tx_stn_cpu_0" 2;
 1106   "tx_stn_cpu_1" 2;
 1107   "tx_stn_cpu_2" 2;
 1108   "tx_stn_cpu_3" 2;
 1109   "tx_stn_cpu_4" 2;
 1110   "tx_stn_cpu_5" 2;
 1111   "tx_stn_cpu_6" 2;
 1112   "tx_stn_cpu_7" 2;
 1113 }
 1114 
 1115 bucket "xgs_1_tx_12" {
 1116   size 16;
 1117   "tx_stn_cpu_0" 2;
 1118   "tx_stn_cpu_1" 2;
 1119   "tx_stn_cpu_2" 2;
 1120   "tx_stn_cpu_3" 2;
 1121   "tx_stn_cpu_4" 2;
 1122   "tx_stn_cpu_5" 2;
 1123   "tx_stn_cpu_6" 2;
 1124   "tx_stn_cpu_7" 2;
 1125 }
 1126 
 1127 bucket "xgs_1_tx_13" {
 1128   size 16;
 1129   "tx_stn_cpu_0" 2;
 1130   "tx_stn_cpu_1" 2;
 1131   "tx_stn_cpu_2" 2;
 1132   "tx_stn_cpu_3" 2;
 1133   "tx_stn_cpu_4" 2;
 1134   "tx_stn_cpu_5" 2;
 1135   "tx_stn_cpu_6" 2;
 1136   "tx_stn_cpu_7" 2;
 1137 }
 1138 
 1139 bucket "xgs_1_tx_14" {
 1140   size 16;
 1141   "tx_stn_cpu_0" 2;
 1142   "tx_stn_cpu_1" 2;
 1143   "tx_stn_cpu_2" 2;
 1144   "tx_stn_cpu_3" 2;
 1145   "tx_stn_cpu_4" 2;
 1146   "tx_stn_cpu_5" 2;
 1147   "tx_stn_cpu_6" 2;
 1148   "tx_stn_cpu_7" 2;
 1149 }
 1150 
 1151 
 1152 
 1153 
 1154 
 1155 
 1156 /*************************************************************/
 1157 // Security Message Station 
 1158 
 1159 bucket "sec_pipe_0" {
 1160         size 128;
 1161         "tx_stn_cpu_0" 16;
 1162         "tx_stn_cpu_1" 16;
 1163         "tx_stn_cpu_2" 16;
 1164         "tx_stn_cpu_3" 16;
 1165         "tx_stn_cpu_4" 16;
 1166         "tx_stn_cpu_5" 16;
 1167         "tx_stn_cpu_6" 16;
 1168         "tx_stn_cpu_7" 16;
 1169 }
 1170 
 1171 bucket "sec_rsa" {
 1172         size 128;
 1173         "tx_stn_cpu_0" 16;
 1174         "tx_stn_cpu_1" 16;
 1175         "tx_stn_cpu_2" 16;
 1176         "tx_stn_cpu_3" 16;
 1177         "tx_stn_cpu_4" 16;
 1178         "tx_stn_cpu_5" 16;
 1179         "tx_stn_cpu_6" 16;
 1180         "tx_stn_cpu_7" 16;
 1181 }
 1182 

Cache object: d7f292533f0c545d3a1a2ce8df155f66


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