1 /*********************************************************************
2 *
3 * Copyright 2003-2006 Raza Microelectronics, Inc. (RMI). All rights
4 * reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 *
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in
14 * the documentation and/or other materials provided with the
15 * distribution.
16 *
17 * THIS SOFTWARE IS PROVIDED BY Raza Microelectronics, Inc. ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
20 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL RMI OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
22 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
23 * SUBSTITUTE GOODS OR SERVICES, LOSS OF USE, DATA, OR PROFITS, OR BUSINESS
24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
25 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
27 * THE POSSIBILITY OF SUCH DAMAGE.
28 *
29 * *****************************RMI_2**********************************/
30
31
32 /*
33 * This file defines the message ring configuration for XLS two core. It tries to allow
34 * many different point-point communications between the message stations on the message ring
35 * and as result is _not_ the best configuration for performance
36 *
37 * The message ring on phoenix family of processors connects the cpus, gmacs, xgmac/spi4,
38 * security engine and the general purpose DMA engines. It provides a high bandwidth,
39 * low latency communication links. On traditional processors, this communication goes through
40 * which inherently does not scale very well with increasing number of cpus.
41 *
42 * Message ring has an in-built flow control mechanism. Every agent/station on the ring has to
43 * have software configured credits to send messages to any agent. Every receiving agent on the
44 * ring has a 256 entry FIFO that can divided into "buckets". All addressing on the ring is
45 * in terms of buckets. There are a total 128 buckets on the ring. The total number of credits
46 * across all sending agents should not exceed the bucket size.
47 *
48 * Below are the receiving agents and the max number of buckets they can have
49 * CPU 0 : 8 buckets
50 * CPU 1 : 8 buckets
51 *
52 * GMAC : 8 buckets
53 *
54 * SEC : 8 buckets
55 *
56 * DMA : 8 buckets
57 *
58 * CMP : Currently disabled.
59 *
60 * The bucket size of a bucket should be aligned to the bucket's starting index in that
61 * receiving station's FIFO. For example, if sizes of bucket0 and bucket1 of a station
62 * are 32 and 32, bucket2's size has to be 64. bucket size 0 is valid.
63 *
64 * The format of the file is pretty straight forward. Each bucket definition has the size
65 * and the list of sending agents to that bucket with the number of credits to send.
66 *
67 * Undefined buckets have a size of 0 and Tx stations have 0 credits to send to that bucket.
68 *
69 * Following are the currently supported bucket names
70 * cpu_0_0
71 * cpu_0_1
72 * cpu_0_2
73 * cpu_0_3
74 * cpu_0_4
75 * cpu_0_5
76 * cpu_0_6
77 * cpu_0_7
78 *
79 * cpu_1_0
80 * cpu_1_1
81 * cpu_1_2
82 * cpu_1_3
83 * cpu_1_4
84 * cpu_1_5
85 * cpu_1_6
86 * cpu_1_7
87 *
88 * enabled only for xls-b0
89 * cpu_2_0
90 * cpu_2_1
91 * cpu_2_2
92 * cpu_2_3
93 * cpu_2_4
94 * cpu_2_5
95 * cpu_2_6
96 * cpu_2_7
97 *
98 * enabled only for xls-b0
99 * cpu_3_0
100 * cpu_3_1
101 * cpu_3_2
102 * cpu_3_3
103 * cpu_3_4
104 * cpu_3_5
105 * cpu_3_6
106 * cpu_3_7
107 *
108 * gmac0_rfr
109 * gmac0_tx_0
110 * gmac0_tx_1
111 * gmac0_tx_2
112 * gmac0_tx_3
113 *
114 * gmac1_rfr
115 * gmac1_tx_0
116 * gmac1_tx_1
117 * gmac1_tx_2
118 * gmac1_tx_3
119 *
120 * sec_pipe_0
121 * sec_rsa
122 *
123 * Following are the currently supported Tx Agent/Station names
124 *
125 * tx_stn_cpu_0
126 * tx_stn_cpu_1
127 *
128 * tx_stn_gmac0
129 * tx_stn_gmac1
130 *
131 * tx_stn_dma
132 *
133 * tx_stn_sec
134 *
135 *
136 */
137
138 /*************************************************************/
139 // CPU_0 Message Station
140
141 bucket "cpu_0_0" {
142 size 32;
143 "tx_stn_gmac0" 8;
144 "tx_stn_gmac1" 8;
145 "tx_stn_sec" 6;
146 "tx_stn_dma" 4;
147 "tx_stn_cmp" 4;
148 "tx_stn_cpu_0" 1;
149 "tx_stn_cpu_1" 1; /* NEEDED BY RMIOS IPSEC */
150 }
151 bucket "cpu_0_1" {
152 size 32;
153 "tx_stn_gmac0" 8;
154 "tx_stn_gmac1" 8;
155 "tx_stn_sec" 8;
156 "tx_stn_dma" 4;
157 "tx_stn_cmp" 4;
158 }
159 bucket "cpu_0_2" {
160 size 32;
161 "tx_stn_gmac0" 8;
162 "tx_stn_gmac1" 8;
163 "tx_stn_sec" 8;
164 "tx_stn_dma" 4;
165 "tx_stn_cmp" 4;
166 }
167 bucket "cpu_0_3" {
168 size 32;
169 "tx_stn_gmac0" 8;
170 "tx_stn_gmac1" 8;
171 "tx_stn_sec" 8;
172 "tx_stn_dma" 4;
173 "tx_stn_cmp" 4;
174 }
175 bucket "cpu_0_4" {
176 size 32;
177 "tx_stn_gmac0" 8;
178 "tx_stn_gmac1" 8;
179 "tx_stn_dma" 4;
180 "tx_stn_cmp" 4;
181 }
182 bucket "cpu_0_5" {
183 size 32;
184 "tx_stn_gmac0" 8;
185 "tx_stn_gmac1" 8;
186 "tx_stn_dma" 4;
187 "tx_stn_cmp" 4;
188 }
189 bucket "cpu_0_6" {
190 size 32;
191 "tx_stn_gmac0" 8;
192 "tx_stn_gmac1" 8;
193 "tx_stn_dma" 4;
194 "tx_stn_cmp" 4;
195 }
196 bucket "cpu_0_7" {
197 size 32;
198 "tx_stn_gmac0" 8;
199 "tx_stn_gmac1" 8;
200 "tx_stn_dma" 4;
201 "tx_stn_cmp" 4;
202 }
203
204 /*************************************************************/
205 // CPU_1 Message Station
206
207 bucket "cpu_1_0" {
208 size 32;
209 "tx_stn_gmac0" 8;
210 "tx_stn_gmac1" 8;
211 "tx_stn_sec" 8;
212 "tx_stn_dma" 4;
213 "tx_stn_cmp" 4;
214 }
215 bucket "cpu_1_1" {
216 size 32;
217 "tx_stn_gmac0" 8;
218 "tx_stn_gmac1" 8;
219 "tx_stn_sec" 8;
220 "tx_stn_dma" 4;
221 "tx_stn_cmp" 4;
222 }
223 bucket "cpu_1_2" {
224 size 32;
225 "tx_stn_gmac0" 8;
226 "tx_stn_gmac1" 8;
227 "tx_stn_sec" 8;
228 "tx_stn_dma" 4;
229 "tx_stn_cmp" 4;
230 }
231 bucket "cpu_1_3" {
232 size 32;
233 "tx_stn_gmac0" 8;
234 "tx_stn_gmac1" 8;
235 "tx_stn_sec" 4;
236 "tx_stn_cpu_0" 8; /* NEEDED BY RMIOS IPSEC */
237 "tx_stn_dma" 2;
238 "tx_stn_cmp" 2;
239 }
240 bucket "cpu_1_4" {
241 size 32;
242 "tx_stn_gmac0" 8;
243 "tx_stn_gmac1" 8;
244 "tx_stn_dma" 4;
245 "tx_stn_cmp" 4;
246 }
247 bucket "cpu_1_5" {
248 size 32;
249 "tx_stn_gmac0" 8;
250 "tx_stn_gmac1" 8;
251 "tx_stn_dma" 4;
252 "tx_stn_cmp" 4;
253 }
254 bucket "cpu_1_6" {
255 size 32;
256 "tx_stn_gmac0" 8;
257 "tx_stn_gmac1" 8;
258 "tx_stn_dma" 4;
259 "tx_stn_cmp" 4;
260 }
261 bucket "cpu_1_7" {
262 size 32;
263 "tx_stn_gmac0" 8;
264 "tx_stn_gmac1" 8;
265 "tx_stn_dma" 4;
266 "tx_stn_cmp" 4;
267 }
268
269 /*************************************************************/
270 // CPU_2 Message Station
271
272 bucket "cpu_2_0" {
273 size 32;
274 "tx_stn_gmac0" 8;
275 "tx_stn_gmac1" 8;
276 "tx_stn_sec" 8;
277 "tx_stn_dma" 4;
278 "tx_stn_cmp" 4;
279 }
280 bucket "cpu_2_1" {
281 size 32;
282 "tx_stn_gmac0" 8;
283 "tx_stn_gmac1" 8;
284 "tx_stn_sec" 8;
285 "tx_stn_dma" 4;
286 "tx_stn_cmp" 4;
287 }
288 bucket "cpu_2_2" {
289 size 32;
290 "tx_stn_gmac0" 8;
291 "tx_stn_gmac1" 8;
292 "tx_stn_sec" 8;
293 "tx_stn_dma" 4;
294 "tx_stn_cmp" 4;
295 }
296 bucket "cpu_2_3" {
297 size 32;
298 "tx_stn_gmac0" 8;
299 "tx_stn_gmac1" 8;
300 "tx_stn_sec" 4;
301 "tx_stn_cpu_0" 8; /* NEEDED BY RMIOS IPSEC */
302 "tx_stn_dma" 2;
303 "tx_stn_cmp" 2;
304 }
305 bucket "cpu_2_4" {
306 size 32;
307 "tx_stn_gmac0" 8;
308 "tx_stn_gmac1" 8;
309 "tx_stn_dma" 4;
310 "tx_stn_cmp" 4;
311 }
312 bucket "cpu_2_5" {
313 size 32;
314 "tx_stn_gmac0" 8;
315 "tx_stn_gmac1" 8;
316 "tx_stn_dma" 4;
317 "tx_stn_cmp" 4;
318 }
319 bucket "cpu_2_6" {
320 size 32;
321 "tx_stn_gmac0" 8;
322 "tx_stn_gmac1" 8;
323 "tx_stn_dma" 4;
324 "tx_stn_cmp" 4;
325 }
326 bucket "cpu_2_7" {
327 size 32;
328 "tx_stn_gmac0" 8;
329 "tx_stn_gmac1" 8;
330 "tx_stn_dma" 4;
331 "tx_stn_cmp" 4;
332 }
333
334
335 /*************************************************************/
336 // CPU_3 Message Station
337 bucket "cpu_3_0" {
338 size 32;
339 "tx_stn_gmac0" 8;
340 "tx_stn_gmac1" 8;
341 "tx_stn_sec" 8;
342 "tx_stn_dma" 4;
343 "tx_stn_cmp" 4;
344 }
345 bucket "cpu_3_1" {
346 size 32;
347 "tx_stn_gmac0" 8;
348 "tx_stn_gmac1" 8;
349 "tx_stn_sec" 8;
350 "tx_stn_dma" 4;
351 "tx_stn_cmp" 4;
352 }
353 bucket "cpu_3_2" {
354 size 32;
355 "tx_stn_gmac0" 8;
356 "tx_stn_gmac1" 8;
357 "tx_stn_sec" 8;
358 "tx_stn_dma" 4;
359 "tx_stn_cmp" 4;
360 }
361 bucket "cpu_3_3" {
362 size 32;
363 "tx_stn_gmac0" 8;
364 "tx_stn_gmac1" 8;
365 "tx_stn_sec" 4;
366 "tx_stn_cpu_0" 8; /* NEEDED BY RMIOS IPSEC */
367 "tx_stn_dma" 2;
368 "tx_stn_cmp" 2;
369 }
370 bucket "cpu_3_4" {
371 size 32;
372 "tx_stn_gmac0" 8;
373 "tx_stn_gmac1" 8;
374 "tx_stn_dma" 4;
375 "tx_stn_cmp" 4;
376 }
377 bucket "cpu_3_5" {
378 size 32;
379 "tx_stn_gmac0" 8;
380 "tx_stn_gmac1" 8;
381 "tx_stn_dma" 4;
382 "tx_stn_cmp" 4;
383 }
384 bucket "cpu_3_6" {
385 size 32;
386 "tx_stn_gmac0" 8;
387 "tx_stn_gmac1" 8;
388 "tx_stn_dma" 4;
389 "tx_stn_cmp" 4;
390 }
391 bucket "cpu_3_7" {
392 size 32;
393 "tx_stn_gmac0" 8;
394 "tx_stn_gmac1" 8;
395 "tx_stn_dma" 4;
396 "tx_stn_cmp" 4;
397 }
398
399 /*************************************************************/
400
401 // GMAC Message Station
402
403 bucket "gmac0_rfr" {
404 size 32;
405 "tx_stn_cpu_0" 4;
406 "tx_stn_cpu_1" 4;
407 "tx_stn_cpu_2" 4;
408 "tx_stn_cpu_3" 4;
409 "tx_stn_gmac0" 8;
410 "tx_stn_gmac1" 8;
411 }
412
413 bucket "gmac0_tx_0" {
414 size 32;
415 "tx_stn_cpu_0" 8;
416 "tx_stn_cpu_1" 8;
417 "tx_stn_cpu_2" 8;
418 "tx_stn_cpu_3" 8;
419 }
420
421 bucket "gmac0_tx_1" {
422 size 32;
423 "tx_stn_cpu_0" 8;
424 "tx_stn_cpu_1" 8;
425 "tx_stn_cpu_2" 8;
426 "tx_stn_cpu_3" 8;
427 }
428
429 bucket "gmac0_tx_2" {
430 size 32;
431 "tx_stn_cpu_0" 8;
432 "tx_stn_cpu_1" 8;
433 "tx_stn_cpu_2" 8;
434 "tx_stn_cpu_3" 8;
435 }
436
437 bucket "gmac0_tx_3" {
438 size 32;
439 "tx_stn_cpu_0" 8;
440 "tx_stn_cpu_1" 8;
441 "tx_stn_cpu_2" 8;
442 "tx_stn_cpu_3" 8;
443 }
444
445 bucket "gmac1_rfr" {
446 size 32;
447 "tx_stn_cpu_0" 4;
448 "tx_stn_cpu_1" 4;
449 "tx_stn_cpu_2" 4;
450 "tx_stn_cpu_3" 4;
451 "tx_stn_gmac0" 8;
452 "tx_stn_gmac1" 8;
453 }
454
455 bucket "gmac1_tx_0" {
456 size 32;
457 "tx_stn_cpu_0" 8;
458 "tx_stn_cpu_1" 8;
459 "tx_stn_cpu_2" 8;
460 "tx_stn_cpu_3" 8;
461 }
462
463 bucket "gmac1_tx_1" {
464 size 32;
465 "tx_stn_cpu_0" 8;
466 "tx_stn_cpu_1" 8;
467 "tx_stn_cpu_2" 8;
468 "tx_stn_cpu_3" 8;
469 }
470
471 bucket "gmac1_tx_2" {
472 size 32;
473 "tx_stn_cpu_0" 8;
474 "tx_stn_cpu_1" 8;
475 "tx_stn_cpu_2" 8;
476 "tx_stn_cpu_3" 8;
477 }
478
479 bucket "gmac1_tx_3" {
480 size 32;
481 "tx_stn_cpu_0" 8;
482 "tx_stn_cpu_1" 8;
483 "tx_stn_cpu_2" 8;
484 "tx_stn_cpu_3" 8;
485 }
486
487 /*************************************************************/
488 // Security Message Station
489
490 bucket "sec_pipe_0" {
491 size 128;
492 "tx_stn_cpu_0" 32;
493 "tx_stn_cpu_1" 32;
494 "tx_stn_cpu_2" 32;
495 "tx_stn_cpu_3" 32;
496 }
497
498 bucket "sec_rsa_ecc" {
499 size 128;
500 "tx_stn_cpu_0" 32;
501 "tx_stn_cpu_1" 32;
502 "tx_stn_cpu_2" 32;
503 "tx_stn_cpu_3" 32;
504 }
505
506 bucket "dma_rsvd_0" {
507 size 64;
508 "tx_stn_cpu_0" 16;
509 "tx_stn_cpu_1" 16;
510 "tx_stn_cpu_2" 16;
511 "tx_stn_cpu_3" 16;
512 }
513 bucket "dma_rsvd_1" {
514 size 64;
515 "tx_stn_cpu_0" 16;
516 "tx_stn_cpu_1" 16;
517 "tx_stn_cpu_2" 16;
518 "tx_stn_cpu_3" 16;
519 }
520
521 bucket "dma_rsvd_2" {
522 size 64;
523 "tx_stn_cpu_0" 16;
524 "tx_stn_cpu_1" 16;
525 "tx_stn_cpu_2" 16;
526 "tx_stn_cpu_3" 16;
527 }
528
529 bucket "dma_rsvd_3" {
530 size 64;
531 "tx_stn_cpu_0" 16;
532 "tx_stn_cpu_1" 16;
533 "tx_stn_cpu_2" 16;
534 "tx_stn_cpu_3" 16;
535 }
536
537 /*************************************************************/
538 // Compression Message Station
539
540 bucket "cmp_0" {
541 size 32;
542 "tx_stn_cpu_0" 16;
543 "tx_stn_cpu_1" 16;
544 }
545
546 bucket "cmp_1" {
547 size 32;
548 "tx_stn_cpu_0" 16;
549 "tx_stn_cpu_1" 16;
550 }
551
552 bucket "cmp_2" {
553 size 32;
554 "tx_stn_cpu_0" 16;
555 "tx_stn_cpu_1" 16;
556 }
557
558 bucket "cmp_3" {
559 size 32;
560 "tx_stn_cpu_0" 16;
561 "tx_stn_cpu_1" 16;
562 }
563
Cache object: d295e2b7563fe830e8b96b32895a9ba7
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