Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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FreeBSD/Linux Kernel Cross Reference
sys/mips/rmi/perfmon_percpu.c
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1 /*- 2 * Copyright (c) 2003-2009 RMI Corporation 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. Neither the name of RMI Corporation, nor the names of its contributors, 14 * may be used to endorse or promote products derived from this software 15 * without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 * 29 * RMI_BSD */ 30 31 #include <sys/param.h> 32 #include <sys/systm.h> 33 #include <sys/kernel.h> 34 #include <sys/smp.h> 35 #include <sys/pcpu.h> 36 #include <mips/rmi/xlrconfig.h> 37 #include <mips/rmi/perfmon_xlrconfig.h> 38 #include <mips/rmi/perfmon.h> 39 #include <mips/rmi/perfmon_utils.h> 40 #include <mips/rmi/pic.h> 41 #include <mips/rmi/msgring.h> 42 43 #define CC_SAMPLE (PERF_CP2_CREDITS <<24) 44 45 #define CC_REG0 16 46 #define CC_REG1 17 47 #define CC_REG2 18 48 #define CC_REG3 19 49 #define CC_REG4 20 50 #define CC_REG5 21 51 #define CC_REG6 22 52 #define CC_REG7 23 53 #define CC_REG8 24 54 #define CC_REG9 25 55 #define CC_REG10 26 56 #define CC_REG11 27 57 #define CC_REG12 28 58 #define CC_REG13 29 59 #define CC_REG14 30 60 #define CC_REG15 31 61 62 extern uint32_t cpu_ltop_map[MAXCPU]; 63 extern struct perf_area *xlr_shared_config_area; 64 65 static __inline__ uint32_t 66 make_cpu_tag(uint32_t val) 67 { 68 return PERF_CP0_COUNTER << 24 | (val & 0xffff); 69 } 70 71 static __inline__ uint32_t 72 make_cp0_perf_control(uint32_t flags, uint32_t thread, uint32_t event) 73 { 74 return (flags & 0x1f) | (thread & 0x03) << 11 | (event & 0x3f) << 5 | 0x01; 75 } 76 77 static __inline__ uint32_t 78 cp0_perf_control_get_thread(uint32_t control_word) 79 { 80 return (control_word & 0x1800) >> 11; 81 } 82 83 static __inline__ uint32_t 84 cp0_perf_control_get_event(uint32_t control_word) 85 { 86 return (control_word & 0x7e0) >> 5; 87 } 88 89 static __inline__ uint32_t 90 read_pic_6_timer_count(void) 91 { 92 xlr_reg_t *mmio = xlr_io_mmio(XLR_IO_PIC_OFFSET); 93 94 /* PIC counts down, convert it to count up */ 95 return 0xffffffffU - xlr_read_reg(mmio, PIC_TIMER_6_COUNTER_0); 96 } 97 98 99 static uint32_t 100 get_num_events(const uint64_t * events) 101 { 102 int total = 0; 103 int thread; 104 105 for (thread = 0; thread < NTHREADS; thread++) { 106 if (events[thread] == 0) 107 continue; 108 total += get_set_bit_count64(events[thread]); 109 } 110 return total; 111 } 112 113 static uint32_t 114 get_first_control_word(uint32_t flags, const uint64_t * events) 115 { 116 int thread, event; 117 118 for (thread = 0; thread < NTHREADS; thread++) { 119 if (events[thread] != 0) 120 break; 121 } 122 if (thread == NTHREADS) 123 return -1; 124 125 event = find_first_set_bit64(events[thread]); 126 return make_cp0_perf_control(flags, thread, event); 127 } 128 129 static uint32_t 130 get_next_control_word(uint32_t current_control_word, const uint64_t * events) 131 { 132 int thread = cp0_perf_control_get_thread(current_control_word); 133 int event = cp0_perf_control_get_event(current_control_word); 134 int i; 135 136 event = find_next_set_bit64(events[thread], event); 137 for (i = 0; event == -1 && i < NTHREADS; i++) { 138 thread = (thread + 1) % NTHREADS; 139 if (events[thread] == 0) 140 continue; 141 event = find_first_set_bit64(events[thread]); 142 } 143 144 ASSERT(event != -1); 145 return make_cp0_perf_control(current_control_word, thread, event); 146 } 147 148 /* Global state per core */ 149 #define MY_CORE_NUM (cpu_ltop_map[PCPU_GET(cpuid)]/NTHREADS) 150 #define my_perf_area (&(xlr_shared_config_area[MY_CORE_NUM])) 151 152 static int num_events_array[NCORES]; 153 static uint32_t saved_timestamp_array[NCORES]; 154 static struct perf_config_data saved_config_array[NCORES]; 155 static int cc_sample_array[NCORES]; 156 157 #define num_events (num_events_array[MY_CORE_NUM]) 158 #define saved_timestamp (saved_timestamp_array[MY_CORE_NUM]) 159 #define saved_config (saved_config_array[MY_CORE_NUM]) 160 #define cc_sample (cc_sample_array[MY_CORE_NUM]) 161 162 static void 163 do_sample_cc_registers(struct sample_q *q, uint32_t mask) 164 { 165 unsigned long flags; 166 167 DPRINT("Sample CC registers %x", mask); 168 msgrng_flags_save(flags); 169 if (mask & 0x00000001) 170 put_sample(q, CC_SAMPLE + 0, read_cc_registers_0123(CC_REG0), 0); 171 if (mask & 0x00000002) 172 put_sample(q, CC_SAMPLE + 1, read_cc_registers_4567(CC_REG0), 0); 173 if (mask & 0x00000004) 174 put_sample(q, CC_SAMPLE + 2, read_cc_registers_0123(CC_REG1), 0); 175 if (mask & 0x00000008) 176 put_sample(q, CC_SAMPLE + 3, read_cc_registers_4567(CC_REG1), 0); 177 if (mask & 0x00000010) 178 put_sample(q, CC_SAMPLE + 4, read_cc_registers_0123(CC_REG2), 0); 179 if (mask & 0x00000020) 180 put_sample(q, CC_SAMPLE + 5, read_cc_registers_4567(CC_REG2), 0); 181 if (mask & 0x00000040) 182 put_sample(q, CC_SAMPLE + 6, read_cc_registers_0123(CC_REG3), 0); 183 if (mask & 0x00000080) 184 put_sample(q, CC_SAMPLE + 7, read_cc_registers_4567(CC_REG3), 0); 185 if (mask & 0x00000100) 186 put_sample(q, CC_SAMPLE + 8, read_cc_registers_0123(CC_REG4), 0); 187 if (mask & 0x00000200) 188 put_sample(q, CC_SAMPLE + 9, read_cc_registers_4567(CC_REG4), 0); 189 if (mask & 0x00000400) 190 put_sample(q, CC_SAMPLE + 10, read_cc_registers_0123(CC_REG5), 0); 191 if (mask & 0x00000800) 192 put_sample(q, CC_SAMPLE + 11, read_cc_registers_4567(CC_REG5), 0); 193 if (mask & 0x00001000) 194 put_sample(q, CC_SAMPLE + 12, read_cc_registers_0123(CC_REG6), 0); 195 if (mask & 0x00002000) 196 put_sample(q, CC_SAMPLE + 13, read_cc_registers_4567(CC_REG6), 0); 197 if (mask & 0x00004000) 198 put_sample(q, CC_SAMPLE + 14, read_cc_registers_0123(CC_REG7), 0); 199 if (mask & 0x00008000) 200 put_sample(q, CC_SAMPLE + 15, read_cc_registers_4567(CC_REG7), 0); 201 if (mask & 0x00010000) 202 put_sample(q, CC_SAMPLE + 16, read_cc_registers_0123(CC_REG8), 0); 203 if (mask & 0x00020000) 204 put_sample(q, CC_SAMPLE + 17, read_cc_registers_4567(CC_REG8), 0); 205 if (mask & 0x00040000) 206 put_sample(q, CC_SAMPLE + 18, read_cc_registers_0123(CC_REG9), 0); 207 if (mask & 0x00080000) 208 put_sample(q, CC_SAMPLE + 19, read_cc_registers_4567(CC_REG9), 0); 209 if (mask & 0x00100000) 210 put_sample(q, CC_SAMPLE + 20, read_cc_registers_0123(CC_REG10), 0); 211 if (mask & 0x00200000) 212 put_sample(q, CC_SAMPLE + 21, read_cc_registers_4567(CC_REG10), 0); 213 if (mask & 0x00400000) 214 put_sample(q, CC_SAMPLE + 22, read_cc_registers_0123(CC_REG11), 0); 215 if (mask & 0x00800000) 216 put_sample(q, CC_SAMPLE + 23, read_cc_registers_4567(CC_REG11), 0); 217 if (mask & 0x01000000) 218 put_sample(q, CC_SAMPLE + 24, read_cc_registers_0123(CC_REG12), 0); 219 if (mask & 0x02000000) 220 put_sample(q, CC_SAMPLE + 24, read_cc_registers_4567(CC_REG12), 0); 221 if (mask & 0x04000000) 222 put_sample(q, CC_SAMPLE + 26, read_cc_registers_0123(CC_REG13), 0); 223 if (mask & 0x08000000) 224 put_sample(q, CC_SAMPLE + 27, read_cc_registers_4567(CC_REG13), 0); 225 if (mask & 0x10000000) 226 put_sample(q, CC_SAMPLE + 28, read_cc_registers_0123(CC_REG14), 0); 227 if (mask & 0x20000000) 228 put_sample(q, CC_SAMPLE + 29, read_cc_registers_4567(CC_REG14), 0); 229 if (mask & 0x40000000) 230 put_sample(q, CC_SAMPLE + 30, read_cc_registers_0123(CC_REG15), 0); 231 if (mask & 0x80000000) 232 put_sample(q, CC_SAMPLE + 31, read_cc_registers_4567(CC_REG15), 0); 233 msgrng_flags_restore(flags); 234 } 235 236 static void 237 reconfigure(void) 238 { 239 uint32_t cntr_cntrl; 240 241 saved_config = my_perf_area->perf_config; 242 num_events = get_num_events(saved_config.events); 243 cc_sample = saved_config.cc_sample_rate; 244 245 DPRINT("%d - reconfigure num_events = %d, events = %llx,%llx,%llx,%llx\n", 246 processor_id(), num_events, saved_config.events[0], 247 saved_config.events[1], saved_config.events[2], saved_config.events[3]); 248 249 if (num_events == 0) 250 return; 251 252 cntr_cntrl = get_first_control_word(saved_config.flags, saved_config.events); 253 write_c0_register(CP0_PERF_COUNTER, PERFCNTRCTL0, cntr_cntrl); 254 write_c0_register(CP0_PERF_COUNTER, PERFCNTR0, 0); /* reset count */ 255 if (num_events > 1) { 256 cntr_cntrl = get_next_control_word(cntr_cntrl, saved_config.events); 257 write_c0_register(CP0_PERF_COUNTER, PERFCNTRCTL1, cntr_cntrl); 258 write_c0_register(CP0_PERF_COUNTER, PERFCNTR1, 0); /* reset count */ 259 } 260 saved_timestamp = read_pic_6_timer_count(); 261 } 262 263 int xlr_perfmon_no_event_count = 0; 264 int xlr_perfmon_sample_count; 265 266 /* timer callback routine */ 267 void 268 xlr_perfmon_sampler(void *dummy) 269 { 270 uint32_t current_ts; 271 uint32_t cntr_cntrl = 0; 272 273 /* xlr_ack_interrupt(XLR_PERFMON_IPI_VECTOR); */ 274 275 if (my_perf_area->perf_config.magic != PERFMON_ACTIVE_MAGIC) 276 return; 277 /* 278 * If there has been a change in configuation, update the 279 * configuration 280 */ 281 if (saved_config.generation != my_perf_area->perf_config.generation) { 282 reconfigure(); 283 return; 284 } 285 /* credit counter samples if reqd */ 286 if (saved_config.cc_register_mask && --cc_sample == 0) { 287 cc_sample = saved_config.cc_sample_rate; 288 do_sample_cc_registers(&my_perf_area->sample_fifo, 289 my_perf_area->perf_config.cc_register_mask); 290 } 291 if (num_events == 0) { 292 xlr_perfmon_no_event_count++; 293 return; 294 } 295 /* put samples in the queue */ 296 current_ts = read_pic_6_timer_count(); 297 cntr_cntrl = read_c0_register(CP0_PERF_COUNTER, PERFCNTRCTL0); 298 put_sample(&my_perf_area->sample_fifo, make_cpu_tag(cntr_cntrl), 299 read_c0_register(CP0_PERF_COUNTER, PERFCNTR0), current_ts - saved_timestamp); 300 xlr_perfmon_sample_count++; 301 write_c0_register(CP0_PERF_COUNTER, PERFCNTR0, 0); /* reset count */ 302 303 if (num_events > 1) { 304 cntr_cntrl = read_c0_register(CP0_PERF_COUNTER, PERFCNTRCTL1); 305 put_sample(&my_perf_area->sample_fifo, make_cpu_tag(cntr_cntrl), 306 read_c0_register(CP0_PERF_COUNTER, PERFCNTR1), current_ts - saved_timestamp); 307 xlr_perfmon_sample_count++; 308 write_c0_register(CP0_PERF_COUNTER, PERFCNTR1, 0); /* reset count */ 309 310 if (num_events > 2) { 311 /* multiplex events */ 312 cntr_cntrl = get_next_control_word(cntr_cntrl, saved_config.events); 313 write_c0_register(CP0_PERF_COUNTER, PERFCNTRCTL0, cntr_cntrl); 314 315 cntr_cntrl = get_next_control_word(cntr_cntrl, saved_config.events); 316 write_c0_register(CP0_PERF_COUNTER, PERFCNTRCTL1, cntr_cntrl); 317 } 318 } 319 saved_timestamp = read_pic_6_timer_count(); 320 } 321 322 /* 323 * Initializes time to gather CPU performance counters and credit counters 324 */ 325 void 326 xlr_perfmon_init_cpu(void *dummy) 327 { 328 int processor = cpu_ltop_map[PCPU_GET(cpuid)]; 329 330 /* run on just one thread per core */ 331 if (processor % 4) 332 return; 333 334 DPRINT("%d : configure with %p", processor, my_perf_area); 335 memset(my_perf_area, 0, sizeof(*my_perf_area)); 336 init_fifo(&my_perf_area->sample_fifo); 337 my_perf_area->perf_config.magic = PERFMON_ENABLED_MAGIC; 338 my_perf_area->perf_config.generation = PERFMON_INITIAL_GENERATION; 339 DPRINT("%d : Initialize", processor); 340 341 return; 342 }
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