Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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FreeBSD/Linux Kernel Cross Reference
sys/mips/rmi/perfmon_xlrconfig.h
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1 /*- 2 * Copyright (c) 2003-2009 RMI Corporation 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. Neither the name of RMI Corporation, nor the names of its contributors, 14 * may be used to endorse or promote products derived from this software 15 * without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 * 29 * RMI_BSD */ 30 31 #ifdef XLR_PERFMON 32 33 #ifndef XLRCONFIG_PERFMON_H 34 #define XLRCONFIG_PERFMON_H 35 36 #include <mips/rmi/perfmon_utils.h> /* for DPRINT */ 37 38 #define NCPUS 32 39 #define NCORES 8 40 #define NTHREADS 4 41 #define PERF_SAMPLE_BUFSZ 32 42 /*select timeout is 512*1024 microsecs */ 43 #define DEFAULT_SYS_SAMPLING_INTERVAL (512*1024) 44 /* default timer value programmed to PIC is 10*1024*1024 */ 45 #define DEFAULT_CPU_SAMPLING_INTERVAL (10*1024) 46 #define DEFAULT_CC_SAMPLE_RATE 16 47 #define DEFAULT_CP0_FLAGS 0x0A 48 #define NUM_L2_BANKS 8 49 #define NUM_DRAM_BANKS 4 50 51 /* CP0 register for timestamp */ 52 #define CP0_COUNT 9 53 #define CP0_EIRR_REG 9 54 #define CP0_EIRR_SEL 6 55 #define CP0_EIMR_REG 9 56 #define CP0_EIMR_SEL 7 57 58 /* CP0 register for perf counters */ 59 #define CP0_PERF_COUNTER 25 60 /* selector values */ 61 #define PERFCNTRCTL0 0 62 #define PERFCNTR0 1 63 #define PERFCNTRCTL1 2 64 #define PERFCNTR1 3 65 66 #define XLR_IO_PIC_OFFSET 0x08000 67 #define PIC_SYS_TIMER_0_BASE 0x120 68 #define PIC_SYS_TIMER_NUM_6 6 69 70 /* CP2 registers for reading credit counters */ 71 #define CC_REG0 16 72 73 #define read_c0_register(reg, sel) \ 74 ({ unsigned int __rv; \ 75 __asm__ __volatile__( \ 76 ".set\tpush\n\t" \ 77 ".set mips32\n\t" \ 78 "mfc0\t%0,$%1,%2\n\t" \ 79 ".set\tpop" \ 80 : "=r" (__rv) : "i" (reg), "i" (sel) ); \ 81 __rv;}) 82 83 #define write_c0_register(reg, sel, value) \ 84 __asm__ __volatile__( \ 85 ".set\tpush\n\t" \ 86 ".set mips32\n\t" \ 87 "mtc0\t%0,$%1,%2\n\t" \ 88 ".set\tpop" \ 89 : : "r" (value), "i" (reg), "i" (sel) ); 90 91 #define read_c2_register(reg, sel) \ 92 ({ unsigned int __rv; \ 93 __asm__ __volatile__( \ 94 ".set\tpush\n\t" \ 95 ".set mips32\n\t" \ 96 "mfc0\t%0,$%1,%2\n\t" \ 97 ".set\tpop" \ 98 : "=r" (__rv) : "i"(reg), "i" (sel) ); \ 99 __rv;}) 100 101 /* 102 * We have 128 registers in C2 credit counters, reading them one at 103 * a time using bitmap will take a lot of code, so we have two functions 104 * to read registers sel0-3 and sel 4-7 into one 32 bit word. 105 */ 106 107 #define read_cc_registers_0123(reg) \ 108 ({ \ 109 unsigned int __rv; \ 110 \ 111 __asm__ __volatile__( \ 112 ".set push\n\t" \ 113 ".set mips32\n\t" \ 114 ".set noreorder\n\t" \ 115 "mfc2 %0, $%1, 0\n\t" \ 116 "mfc2 $8, $%1, 1\n\t" \ 117 "sll %0, %0, 8\n\t" \ 118 "or %0, %0, $8\n\t" \ 119 "mfc2 $8, $%1, 2\n\t" \ 120 "sll %0, %0, 8\n\t" \ 121 "or %0, %0, $8\n\t" \ 122 "mfc2 $8, $%1, 3\n\t" \ 123 "sll %0, %0, 8\n\t" \ 124 "or %0, %0, $8\n\t" \ 125 ".set pop" \ 126 : "=r" (__rv) : "i"(reg) : "$8"); \ 127 \ 128 __rv; \ 129 }) 130 131 #define read_cc_registers_4567(reg) \ 132 ({ \ 133 unsigned int __rv; \ 134 \ 135 __asm__ __volatile__( \ 136 ".set push\n\t" \ 137 ".set mips32\n\t" \ 138 ".set noreorder\n\t" \ 139 "mfc2 %0, $%1, 4\n\t" \ 140 "mfc2 $8, $%1, 5\n\t" \ 141 "sll %0, %0, 8\n\t" \ 142 "or %0, %0, $8\n\t" \ 143 "mfc2 $8, $%1, 6\n\t" \ 144 "sll %0, %0, 8\n\t" \ 145 "or %0, %0, $8\n\t" \ 146 "mfc2 $8, $%1, 7\n\t" \ 147 "sll %0, %0, 8\n\t" \ 148 "or %0, %0, $8\n\t" \ 149 ".set pop" \ 150 : "=r" (__rv) :"i"(reg) : "$8"); \ 151 \ 152 __rv; \ 153 }) 154 155 #endif 156 #endif
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