The Design and Implementation of the FreeBSD Operating System, Second Edition
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FreeBSD/Linux Kernel Cross Reference
sys/mips/rmi/pic.h

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    1 /*-
    2  * Copyright (c) 2003-2009 RMI Corporation
    3  * All rights reserved.
    4  *
    5  * Redistribution and use in source and binary forms, with or without
    6  * modification, are permitted provided that the following conditions
    7  * are met:
    8  * 1. Redistributions of source code must retain the above copyright
    9  *    notice, this list of conditions and the following disclaimer.
   10  * 2. Redistributions in binary form must reproduce the above copyright
   11  *    notice, this list of conditions and the following disclaimer in the
   12  *    documentation and/or other materials provided with the distribution.
   13  * 3. Neither the name of RMI Corporation, nor the names of its contributors,
   14  *    may be used to endorse or promote products derived from this software
   15  *    without specific prior written permission.
   16  *
   17  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
   18  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   19  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   20  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
   21  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
   22  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
   23  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
   24  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
   25  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   26  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   27  * SUCH DAMAGE.
   28  *
   29  * RMI_BSD
   30  * $FreeBSD: stable/8/sys/mips/rmi/pic.h 215938 2010-11-27 12:26:40Z jchandra $
   31  */
   32 #ifndef _RMI_PIC_H_
   33 #define _RMI_PIC_H_
   34 
   35 #include <sys/cdefs.h>
   36 #include <sys/lock.h>
   37 #include <sys/mutex.h>
   38 #include <mips/rmi/iomap.h>
   39 
   40 #define PIC_IRT_WD_INDEX                0
   41 #define PIC_IRT_TIMER_INDEX(i)          (1 + (i))
   42 #define PIC_IRT_UART_0_INDEX            9
   43 #define PIC_IRT_UART_1_INDEX            10
   44 #define PIC_IRT_I2C_0_INDEX             11
   45 #define PIC_IRT_I2C_1_INDEX             12
   46 #define PIC_IRT_PCMCIA_INDEX            13
   47 #define PIC_IRT_GPIO_INDEX              14
   48 #define PIC_IRT_HYPER_INDEX             15
   49 #define PIC_IRT_PCIX_INDEX              16
   50 #define PIC_IRT_GMAC0_INDEX             17
   51 #define PIC_IRT_GMAC1_INDEX             18
   52 #define PIC_IRT_GMAC2_INDEX             19
   53 #define PIC_IRT_GMAC3_INDEX             20
   54 #define PIC_IRT_XGS0_INDEX              21
   55 #define PIC_IRT_XGS1_INDEX              22
   56 #define PIC_IRT_HYPER_FATAL_INDEX       23
   57 #define PIC_IRT_PCIX_FATAL_INDEX        24
   58 #define PIC_IRT_BRIDGE_AERR_INDEX       25
   59 #define PIC_IRT_BRIDGE_BERR_INDEX       26
   60 #define PIC_IRT_BRIDGE_TB_INDEX         27
   61 #define PIC_IRT_BRIDGE_AERR_NMI_INDEX   28
   62 
   63 /* numbering for XLS */
   64 #define PIC_IRT_BRIDGE_ERR_INDEX        25
   65 #define PIC_IRT_PCIE_LINK0_INDEX        26
   66 #define PIC_IRT_PCIE_LINK1_INDEX        27
   67 #define PIC_IRT_PCIE_LINK2_INDEX        23
   68 #define PIC_IRT_PCIE_LINK3_INDEX        24
   69 #define PIC_IRT_PCIE_B0_LINK2_INDEX     28
   70 #define PIC_IRT_PCIE_B0_LINK3_INDEX     29
   71 #define PIC_IRT_PCIE_INT_INDEX          28
   72 #define PIC_IRT_PCIE_FATAL_INDEX        29
   73 #define PIC_IRT_GPIO_B_INDEX            30
   74 #define PIC_IRT_USB_INDEX               31
   75 #define PIC_NUM_IRTS                    32
   76 
   77 #define PIC_CLOCK_TIMER                 7
   78 
   79 #define PIC_CTRL                        0x00
   80 #define PIC_IPI                         0x04
   81 #define PIC_INT_ACK                     0x06
   82 
   83 #define WD_MAX_VAL_0                    0x08
   84 #define WD_MAX_VAL_1                    0x09
   85 #define WD_MASK_0                       0x0a
   86 #define WD_MASK_1                       0x0b
   87 #define WD_HEARBEAT_0                   0x0c
   88 #define WD_HEARBEAT_1                   0x0d
   89 
   90 #define PIC_IRT_0_BASE                  0x40
   91 #define PIC_IRT_1_BASE                  0x80
   92 #define PIC_TIMER_MAXVAL_0_BASE         0x100
   93 #define PIC_TIMER_MAXVAL_1_BASE         0x110
   94 #define PIC_TIMER_COUNT_0_BASE          0x120
   95 #define PIC_TIMER_COUNT_1_BASE          0x130
   96 
   97 #define PIC_IRT_0(picintr)      (PIC_IRT_0_BASE + (picintr))
   98 #define PIC_IRT_1(picintr)      (PIC_IRT_1_BASE + (picintr))
   99 
  100 #define PIC_TIMER_MAXVAL_0(i)   (PIC_TIMER_MAXVAL_0_BASE + (i))
  101 #define PIC_TIMER_MAXVAL_1(i)   (PIC_TIMER_MAXVAL_1_BASE + (i))
  102 #define PIC_TIMER_COUNT_0(i)    (PIC_TIMER_COUNT_0_BASE + (i))
  103 #define PIC_TIMER_COUNT_1(i)    (PIC_TIMER_COUNT_0_BASE + (i))
  104 #define PIC_TIMER_HZ            66000000U
  105 
  106 /*
  107  * We use a simple mapping form PIC interrupts to CPU IRQs.
  108  * The PIC interrupts 0-31 are mapped to CPU irq's 8-39.
  109  * this leaves the lower 0-7 for the cpu interrupts (like 
  110  * count/compare, msgrng) and 40-63 for IPIs
  111  */
  112 #define PIC_IRQ_BASE            8
  113 #define PIC_INTR_TO_IRQ(i)      (PIC_IRQ_BASE + (i))
  114 #define PIC_IRQ_TO_INTR(i)      ((i) - PIC_IRQ_BASE)
  115 
  116 #define PIC_WD_IRQ              (PIC_IRQ_BASE + PIC_IRT_WD_INDEX)
  117 #define PIC_TIMER_IRQ(i)        (PIC_IRQ_BASE + PIC_IRT_TIMER_INDEX(i))
  118 #define PIC_CLOCK_IRQ           PIC_TIMER_IRQ(PIC_CLOCK_TIMER)
  119 
  120 #define PIC_UART_0_IRQ          (PIC_IRQ_BASE + PIC_IRT_UART_0_INDEX)
  121 #define PIC_UART_1_IRQ          (PIC_IRQ_BASE + PIC_IRT_UART_1_INDEX)
  122 #define PIC_I2C_0_IRQ           (PIC_IRQ_BASE + PIC_IRT_I2C_0_INDEX)
  123 #define PIC_I2C_1_IRQ           (PIC_IRQ_BASE + PIC_IRT_I2C_1_INDEX)
  124 #define PIC_PCMCIA_IRQ          (PIC_IRQ_BASE + PIC_IRT_PCMCIA_INDEX)
  125 #define PIC_GPIO_IRQ            (PIC_IRQ_BASE + PIC_IRT_GPIO_INDEX)
  126 #define PIC_HYPER_IRQ           (PIC_IRQ_BASE + PIC_IRT_HYPER_INDEX)
  127 #define PIC_PCIX_IRQ            (PIC_IRQ_BASE + PIC_IRT_PCIX_INDEX)
  128 #define PIC_GMAC_0_IRQ          (PIC_IRQ_BASE + PIC_IRT_GMAC0_INDEX)
  129 #define PIC_GMAC_1_IRQ          (PIC_IRQ_BASE + PIC_IRT_GMAC1_INDEX)
  130 #define PIC_GMAC_2_IRQ          (PIC_IRQ_BASE + PIC_IRT_GMAC2_INDEX)
  131 #define PIC_GMAC_3_IRQ          (PIC_IRQ_BASE + PIC_IRT_GMAC3_INDEX)
  132 #define PIC_XGS_0_IRQ           (PIC_IRQ_BASE + PIC_IRT_XGS0_INDEX)
  133 #define PIC_XGS_1_IRQ           (PIC_IRQ_BASE + PIC_IRT_XGS1_INDEX)
  134 #define PIC_HYPER_FATAL_IRQ     (PIC_IRQ_BASE + PIC_IRT_HYPER_FATAL_INDEX)
  135 #define PIC_PCIX_FATAL_IRQ      (PIC_IRQ_BASE + PIC_IRT_PCIX_FATAL_INDEX)
  136 #define PIC_BRIDGE_AERR_IRQ     (PIC_IRQ_BASE + PIC_IRT_BRIDGE_AERR_INDEX)
  137 #define PIC_BRIDGE_BERR_IRQ     (PIC_IRQ_BASE + PIC_IRT_BRIDGE_BERR_INDEX)
  138 #define PIC_BRIDGE_TB_IRQ       (PIC_IRQ_BASE + PIC_IRT_BRIDGE_TB_INDEX)
  139 #define PIC_BRIDGE_AERR_NMI_IRQ (PIC_IRQ_BASE + PIC_IRT_BRIDGE_AERR_NMI_INDEX)
  140 #define PIC_BRIDGE_ERR_IRQ      (PIC_IRQ_BASE + PIC_IRT_BRIDGE_ERR_INDEX)
  141 #define PIC_PCIE_LINK0_IRQ      (PIC_IRQ_BASE + PIC_IRT_PCIE_LINK0_INDEX)
  142 #define PIC_PCIE_LINK1_IRQ      (PIC_IRQ_BASE + PIC_IRT_PCIE_LINK1_INDEX)
  143 #define PIC_PCIE_LINK2_IRQ      (PIC_IRQ_BASE + PIC_IRT_PCIE_LINK2_INDEX)
  144 #define PIC_PCIE_LINK3_IRQ      (PIC_IRQ_BASE + PIC_IRT_PCIE_LINK3_INDEX)
  145 #define PIC_PCIE_B0_LINK2_IRQ   (PIC_IRQ_BASE + PIC_IRT_PCIE_B0_LINK2_INDEX)
  146 #define PIC_PCIE_B0_LINK3_IRQ   (PIC_IRQ_BASE + PIC_IRT_PCIE_B0_LINK3_INDEX)
  147 #define PIC_PCIE_INT_IRQ        (PIC_IRQ_BASE + PIC_IRT_PCIE_INT_INDEX)
  148 #define PIC_PCIE_FATAL_IRQ      (PIC_IRQ_BASE + PIC_IRT_PCIE_FATAL_INDEX)
  149 #define PIC_GPIO_B_IRQ          (PIC_IRQ_BASE + PIC_IRT_GPIO_B_INDEX)
  150 #define PIC_USB_IRQ             (PIC_IRQ_BASE + PIC_IRT_USB_INDEX)
  151 
  152 #define PIC_IRQ_IS_PICINTR(irq) ((irq) >= PIC_IRQ_BASE &&               \
  153                                  (irq) < PIC_IRQ_BASE + PIC_NUM_IRTS)
  154 #define PIC_IS_EDGE_TRIGGERED(i) ((i) >= PIC_IRT_TIMER_INDEX(0) &&      \
  155                                   (i) <= PIC_IRT_TIMER_INDEX(7))
  156 
  157 extern struct mtx xlr_pic_lock;
  158 
  159 static __inline uint32_t 
  160 pic_read_control(void)
  161 {
  162         xlr_reg_t *mmio = xlr_io_mmio(XLR_IO_PIC_OFFSET);
  163         uint32_t reg;
  164 
  165         mtx_lock_spin(&xlr_pic_lock);
  166         xlr_read_reg(mmio, PIC_CTRL);
  167         mtx_unlock_spin(&xlr_pic_lock);
  168         return (reg);
  169 }
  170 
  171 static __inline void 
  172 pic_write_control(uint32_t control)
  173 {
  174         xlr_reg_t *mmio = xlr_io_mmio(XLR_IO_PIC_OFFSET);
  175 
  176         mtx_lock_spin(&xlr_pic_lock);
  177         xlr_write_reg(mmio, PIC_CTRL, control);
  178         mtx_unlock_spin(&xlr_pic_lock);
  179 }
  180 
  181 static __inline void 
  182 pic_update_control(__uint32_t control)
  183 {
  184         xlr_reg_t *mmio = xlr_io_mmio(XLR_IO_PIC_OFFSET);
  185 
  186         mtx_lock_spin(&xlr_pic_lock);
  187         xlr_write_reg(mmio, PIC_CTRL, (control | xlr_read_reg(mmio, PIC_CTRL)));
  188         mtx_unlock_spin(&xlr_pic_lock);
  189 }
  190 
  191 static __inline void 
  192 pic_ack(int picintr)
  193 {
  194         xlr_reg_t *mmio = xlr_io_mmio(XLR_IO_PIC_OFFSET);
  195 
  196         xlr_write_reg(mmio, PIC_INT_ACK, 1U << picintr);
  197 }
  198 
  199 static __inline
  200 void pic_send_ipi(int cpu, int ipi)
  201 {
  202         xlr_reg_t *mmio = xlr_io_mmio(XLR_IO_PIC_OFFSET);
  203         int tid, pid;
  204 
  205         tid = cpu & 0x3;
  206         pid = (cpu >> 2) & 0x7;
  207         xlr_write_reg(mmio, PIC_IPI, (pid << 20) | (tid << 16) | ipi);
  208 }
  209 
  210 static __inline
  211 void pic_setup_intr(int picintr, int irq, uint32_t cpumask, int level)
  212 {
  213         xlr_reg_t *mmio = xlr_io_mmio(XLR_IO_PIC_OFFSET);
  214 
  215         mtx_lock_spin(&xlr_pic_lock);
  216         xlr_write_reg(mmio, PIC_IRT_0(picintr), cpumask);
  217         xlr_write_reg(mmio, PIC_IRT_1(picintr), ((1 << 31) | (level << 30) |
  218             (1 << 6) | irq));
  219         mtx_unlock_spin(&xlr_pic_lock);
  220 }
  221 
  222 static __inline void 
  223 pic_init_timer(int timer)
  224 {
  225         xlr_reg_t *mmio = xlr_io_mmio(XLR_IO_PIC_OFFSET);
  226         uint32_t val;
  227  
  228         mtx_lock_spin(&xlr_pic_lock);
  229         val = xlr_read_reg(mmio, PIC_CTRL);
  230         val |= (1 << (8 + timer));
  231         xlr_write_reg(mmio, PIC_CTRL, val);
  232         mtx_unlock_spin(&xlr_pic_lock);
  233 }
  234  
  235 static __inline void
  236 pic_set_timer(int timer, uint64_t maxval)
  237 {
  238         xlr_reg_t *mmio = xlr_io_mmio(XLR_IO_PIC_OFFSET);
  239 
  240         xlr_write_reg(mmio, PIC_TIMER_MAXVAL_0(timer),
  241             (maxval & 0xffffffff)); 
  242         xlr_write_reg(mmio, PIC_TIMER_MAXVAL_1(timer), 
  243             (maxval >> 32) & 0xffffffff);
  244 }
  245 
  246 static __inline uint32_t
  247 pic_timer_count32(int timer)
  248  {
  249         xlr_reg_t *mmio = xlr_io_mmio(XLR_IO_PIC_OFFSET);
  250 
  251         return (xlr_read_reg(mmio, PIC_TIMER_COUNT_0(timer))); 
  252 }
  253 
  254 /*
  255  * The timer can wrap 32 bits between the two reads, so we
  256  * need additional logic to detect that.
  257  */
  258 static __inline uint64_t
  259 pic_timer_count(int timer)
  260 {
  261         xlr_reg_t *mmio = xlr_io_mmio(XLR_IO_PIC_OFFSET);
  262         uint32_t tu1, tu2, tl;
  263 
  264         tu1 = xlr_read_reg(mmio, PIC_TIMER_COUNT_1(timer)); 
  265         tl = xlr_read_reg(mmio, PIC_TIMER_COUNT_0(timer)); 
  266         tu2 = xlr_read_reg(mmio, PIC_TIMER_COUNT_1(timer)); 
  267         if (tu2 != tu1)
  268                 tl = xlr_read_reg(mmio, PIC_TIMER_COUNT_0(timer));
  269         return (((uint64_t)tu2 << 32) | tl);
  270 }
  271 
  272 #endif  /* _RMI_PIC_H_ */

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