The Design and Implementation of the FreeBSD Operating System, Second Edition
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FreeBSD/Linux Kernel Cross Reference
sys/mips/rmi/xlr_pci.c

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    1 /*-
    2  * Copyright (c) 2003-2009 RMI Corporation
    3  * All rights reserved.
    4  *
    5  * Redistribution and use in source and binary forms, with or without
    6  * modification, are permitted provided that the following conditions
    7  * are met:
    8  * 1. Redistributions of source code must retain the above copyright
    9  *    notice, this list of conditions and the following disclaimer.
   10  * 2. Redistributions in binary form must reproduce the above copyright
   11  *    notice, this list of conditions and the following disclaimer in the
   12  *    documentation and/or other materials provided with the distribution.
   13  * 3. Neither the name of RMI Corporation, nor the names of its contributors,
   14  *    may be used to endorse or promote products derived from this software
   15  *    without specific prior written permission.
   16  *
   17  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
   18  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   19  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   20  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
   21  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
   22  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
   23  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
   24  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
   25  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   26  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   27  * SUCH DAMAGE.
   28  *
   29  * RMI_BSD */
   30 #include <sys/cdefs.h>
   31 __FBSDID("$FreeBSD: stable/8/sys/mips/rmi/xlr_pci.c 230714 2012-01-29 01:22:48Z marius $");
   32 
   33 #include <sys/param.h>
   34 #include <sys/systm.h>
   35 #include <sys/types.h>
   36 #include <sys/kernel.h>
   37 #include <sys/module.h>
   38 #include <sys/malloc.h>
   39 #include <sys/bus.h>
   40 #include <sys/endian.h>
   41 #include <sys/rman.h>
   42 
   43 #include <vm/vm.h>
   44 #include <vm/vm_param.h>
   45 #include <vm/pmap.h>
   46 
   47 #include <dev/pci/pcivar.h>
   48 #include <dev/pci/pcireg.h>
   49 
   50 #include <machine/bus.h>
   51 #include <machine/md_var.h>
   52 #include <machine/intr_machdep.h>
   53 #include <machine/cpuregs.h>
   54 
   55 #include <mips/rmi/rmi_mips_exts.h>
   56 #include <mips/rmi/interrupt.h>
   57 #include <mips/rmi/iomap.h>
   58 #include <mips/rmi/pic.h>
   59 #include <mips/rmi/board.h>
   60 #include <mips/rmi/pcibus.h>
   61 
   62 #include "pcib_if.h"
   63 
   64 #define pci_cfg_offset(bus,slot,devfn,where) (((bus)<<16) + ((slot) << 11)+((devfn)<<8)+(where))
   65 #define PCIE_LINK_STATE    0x4000
   66 
   67 #define LSU_CFG0_REGID       0
   68 #define LSU_CERRLOG_REGID    9
   69 #define LSU_CERROVF_REGID    10
   70 #define LSU_CERRINT_REGID    11
   71 
   72 /* MSI support */
   73 #define MSI_MIPS_ADDR_DEST              0x000ff000
   74 #define MSI_MIPS_ADDR_RH                0x00000008
   75 #define MSI_MIPS_ADDR_RH_OFF            0x00000000
   76 #define MSI_MIPS_ADDR_RH_ON             0x00000008
   77 #define MSI_MIPS_ADDR_DM                0x00000004
   78 #define MSI_MIPS_ADDR_DM_PHYSICAL       0x00000000
   79 #define MSI_MIPS_ADDR_DM_LOGICAL        0x00000004
   80 
   81 /* Fields in data for Intel MSI messages. */
   82 #define MSI_MIPS_DATA_TRGRMOD           0x00008000      /* Trigger mode */
   83 #define MSI_MIPS_DATA_TRGREDG           0x00000000      /* edge */
   84 #define MSI_MIPS_DATA_TRGRLVL           0x00008000      /* level */
   85 
   86 #define MSI_MIPS_DATA_LEVEL             0x00004000      /* Polarity. */
   87 #define MSI_MIPS_DATA_DEASSERT          0x00000000
   88 #define MSI_MIPS_DATA_ASSERT            0x00004000
   89 
   90 #define MSI_MIPS_DATA_DELMOD            0x00000700      /* Delivery Mode */
   91 #define MSI_MIPS_DATA_DELFIXED          0x00000000      /* fixed */
   92 #define MSI_MIPS_DATA_DELLOPRI          0x00000100      /* lowest priority */
   93 
   94 #define MSI_MIPS_DATA_INTVEC            0x000000ff
   95 
   96 /*
   97  * Build Intel MSI message and data values from a source.  AMD64 systems
   98  * seem to be compatible, so we use the same function for both.
   99  */
  100 #define MIPS_MSI_ADDR(cpu)                                             \
  101         (MSI_MIPS_ADDR_BASE | (cpu) << 12 |                            \
  102          MSI_MIPS_ADDR_RH_OFF | MSI_MIPS_ADDR_DM_PHYSICAL)
  103 
  104 #define MIPS_MSI_DATA(irq)                                             \
  105         (MSI_MIPS_DATA_TRGRLVL | MSI_MIPS_DATA_DELFIXED |              \
  106          MSI_MIPS_DATA_ASSERT | (irq))
  107 
  108 #define DEBUG
  109 #ifdef DEBUG
  110 #define dbg_devprintf   device_printf
  111 #else
  112 #define dbg_devprintf(dev, fmt, ...)
  113 #endif
  114 
  115 struct xlr_pcib_softc {
  116         bus_dma_tag_t   sc_pci_dmat;    /* PCI DMA tag pointer */
  117 };
  118 
  119 static devclass_t pcib_devclass;
  120 static void *xlr_pci_config_base;
  121 static struct rman irq_rman, port_rman, mem_rman;
  122 
  123 static void
  124 xlr_pci_init_resources(void)
  125 {
  126 
  127         irq_rman.rm_start = 0;
  128         irq_rman.rm_end = 255;
  129         irq_rman.rm_type = RMAN_ARRAY;
  130         irq_rman.rm_descr = "PCI Mapped Interrupts";
  131         if (rman_init(&irq_rman)
  132             || rman_manage_region(&irq_rman, 0, 255))
  133                 panic("pci_init_resources irq_rman");
  134 
  135         port_rman.rm_start = 0;
  136         port_rman.rm_end = ~0ul;
  137         port_rman.rm_type = RMAN_ARRAY;
  138         port_rman.rm_descr = "I/O ports";
  139         if (rman_init(&port_rman)
  140             || rman_manage_region(&port_rman, 0x10000000, 0x1fffffff))
  141                 panic("pci_init_resources port_rman");
  142 
  143         mem_rman.rm_start = 0;
  144         mem_rman.rm_end = ~0ul;
  145         mem_rman.rm_type = RMAN_ARRAY;
  146         mem_rman.rm_descr = "I/O memory";
  147         if (rman_init(&mem_rman)
  148             || rman_manage_region(&mem_rman, 0xd0000000, 0xdfffffff))
  149                 panic("pci_init_resources mem_rman");
  150 }
  151 
  152 static int
  153 xlr_pcib_probe(device_t dev)
  154 {
  155 
  156         if (xlr_board_info.is_xls)
  157                 device_set_desc(dev, "XLS PCIe bus");
  158         else
  159                 device_set_desc(dev, "XLR PCI bus");
  160 
  161         xlr_pci_init_resources();
  162         xlr_pci_config_base = (void *)MIPS_PHYS_TO_KSEG1(DEFAULT_PCI_CONFIG_BASE);
  163 
  164         return (0);
  165 }
  166 
  167 static int
  168 xlr_pcib_read_ivar(device_t dev, device_t child, int which, uintptr_t *result)
  169 {
  170 
  171         switch (which) {
  172         case PCIB_IVAR_DOMAIN:
  173                 *result = 0;
  174                 return (0);
  175         case PCIB_IVAR_BUS:
  176                 *result = 0;
  177                 return (0);
  178         }
  179         return (ENOENT);
  180 }
  181 
  182 static int
  183 xlr_pcib_write_ivar(device_t dev, device_t child, int which, uintptr_t result)
  184 {
  185         switch (which) {
  186         case PCIB_IVAR_DOMAIN:
  187                 return (EINVAL);
  188         case PCIB_IVAR_BUS:
  189                 return (EINVAL);
  190         }
  191         return (ENOENT);
  192 }
  193 
  194 static int
  195 xlr_pcib_maxslots(device_t dev)
  196 {
  197 
  198         return (PCI_SLOTMAX);
  199 }
  200 
  201 static __inline__ void 
  202 disable_and_clear_cache_error(void)
  203 {
  204         uint64_t lsu_cfg0;
  205 
  206         lsu_cfg0 = read_xlr_ctrl_register(CPU_BLOCKID_LSU, LSU_CFG0_REGID);
  207         lsu_cfg0 = lsu_cfg0 & ~0x2e;
  208         write_xlr_ctrl_register(CPU_BLOCKID_LSU, LSU_CFG0_REGID, lsu_cfg0);
  209         /* Clear cache error log */
  210         write_xlr_ctrl_register(CPU_BLOCKID_LSU, LSU_CERRLOG_REGID, 0);
  211 }
  212 
  213 static __inline__ void 
  214 clear_and_enable_cache_error(void)
  215 {
  216         uint64_t lsu_cfg0 = 0;
  217 
  218         /* first clear the cache error logging register */
  219         write_xlr_ctrl_register(CPU_BLOCKID_LSU, LSU_CERRLOG_REGID, 0);
  220         write_xlr_ctrl_register(CPU_BLOCKID_LSU, LSU_CERROVF_REGID, 0);
  221         write_xlr_ctrl_register(CPU_BLOCKID_LSU, LSU_CERRINT_REGID, 0);
  222 
  223         lsu_cfg0 = read_xlr_ctrl_register(CPU_BLOCKID_LSU, LSU_CFG0_REGID);
  224         lsu_cfg0 = lsu_cfg0 | 0x2e;
  225         write_xlr_ctrl_register(CPU_BLOCKID_LSU, LSU_CFG0_REGID, lsu_cfg0);
  226 }
  227 
  228 static uint32_t 
  229 pci_cfg_read_32bit(uint32_t addr)
  230 {
  231         uint32_t temp = 0;
  232         uint32_t *p = (uint32_t *)xlr_pci_config_base + addr / sizeof(uint32_t);
  233         uint64_t cerr_cpu_log = 0;
  234 
  235         disable_and_clear_cache_error();
  236         temp = bswap32(*p);
  237 
  238         /* Read cache err log */
  239         cerr_cpu_log = read_xlr_ctrl_register(CPU_BLOCKID_LSU,
  240             LSU_CERRLOG_REGID);
  241         if (cerr_cpu_log) {
  242                 /* Device don't exist. */
  243                 temp = ~0x0;
  244         }
  245         clear_and_enable_cache_error();
  246         return (temp);
  247 }
  248 
  249 static u_int32_t
  250 xlr_pcib_read_config(device_t dev, u_int b, u_int s, u_int f,
  251                         u_int reg, int width)
  252 {
  253         uint32_t data = 0;
  254 
  255         if ((width == 2) && (reg & 1))
  256                 return 0xFFFFFFFF;
  257         else if ((width == 4) && (reg & 3))
  258                 return 0xFFFFFFFF;
  259 
  260         data = pci_cfg_read_32bit(pci_cfg_offset(b, s, f, reg));
  261 
  262         if (width == 1)
  263                 return ((data >> ((reg & 3) << 3)) & 0xff);
  264         else if (width == 2)
  265                 return ((data >> ((reg & 3) << 3)) & 0xffff);
  266         else
  267                 return (data);
  268 }
  269 
  270 static void
  271 xlr_pcib_write_config(device_t dev, u_int b, u_int s, u_int f,
  272                 u_int reg, u_int32_t val, int width)
  273 {
  274         uint32_t cfgaddr = pci_cfg_offset(b, s, f, reg);
  275         uint32_t data = 0, *p;
  276 
  277         if ((width == 2) && (reg & 1))
  278                 return;
  279         else if ((width == 4) && (reg & 3))
  280                 return;
  281 
  282         if (width == 1) {
  283                 data = pci_cfg_read_32bit(cfgaddr);
  284                 data = (data & ~(0xff << ((reg & 3) << 3))) |
  285                     (val << ((reg & 3) << 3));
  286         } else if (width == 2) {
  287                 data = pci_cfg_read_32bit(cfgaddr);
  288                 data = (data & ~(0xffff << ((reg & 3) << 3))) |
  289                     (val << ((reg & 3) << 3));
  290         } else {
  291                 data = val;
  292         }
  293 
  294         p = (uint32_t *)xlr_pci_config_base + cfgaddr / sizeof(uint32_t);
  295         *p = bswap32(data);
  296 
  297         return;
  298 }
  299 
  300 static int 
  301 xlr_pcib_attach(device_t dev)
  302 {
  303         struct xlr_pcib_softc *sc;
  304         sc = device_get_softc(dev);
  305         
  306         /*
  307          * XLR C revision chips cannot do DMA above 2G physical address
  308          * create a parent tag with this lowaddr
  309          */
  310         if (xlr_is_c_revision()) {
  311                 if (bus_dma_tag_create(bus_get_dma_tag(dev), 1, 0,
  312                     0x7fffffff, ~0, NULL, NULL, 0x7fffffff,
  313                     0xff, 0x7fffffff, 0, NULL, NULL, &sc->sc_pci_dmat) != 0)
  314                         panic("%s: bus_dma_tag_create failed", __func__);
  315         }
  316         device_add_child(dev, "pci", 0);
  317         bus_generic_attach(dev);
  318         return (0);
  319 }
  320 
  321 static void
  322 xlr_pcib_identify(driver_t * driver, device_t parent)
  323 {
  324 
  325         BUS_ADD_CHILD(parent, 0, "pcib", 0);
  326 }
  327 
  328 /*
  329  * XLS PCIe can have upto 4 links, and each link has its on IRQ
  330  * Find the link on which the device is on 
  331  */
  332 static int
  333 xls_pcie_link(device_t pcib, device_t dev)
  334 {
  335         device_t parent, tmp;
  336 
  337         /* find the lane on which the slot is connected to */
  338         printf("xls_pcie_link : bus %s dev %s\n", device_get_nameunit(pcib),
  339                 device_get_nameunit(dev));
  340         tmp = dev;
  341         while (1) {
  342                 parent = device_get_parent(tmp);
  343                 if (parent == NULL || parent == pcib) {
  344                         device_printf(dev, "Cannot find parent bus\n");
  345                         return (-1);
  346                 }
  347                 if (strcmp(device_get_nameunit(parent), "pci0") == 0)
  348                         break;
  349                 tmp = parent;
  350         }
  351         return (pci_get_slot(tmp));
  352 }
  353 
  354 /*
  355  * Find the IRQ for the link, each link has a different interrupt 
  356  * at the XLS pic
  357  */
  358 static int
  359 xls_pcie_link_irq(int link)
  360 {
  361 
  362         switch (link) {
  363         case 0:
  364                 return (PIC_PCIE_LINK0_IRQ);
  365         case 1:
  366                 return (PIC_PCIE_LINK1_IRQ);
  367         case 2:
  368                 if (xlr_is_xls_b0())
  369                         return (PIC_PCIE_B0_LINK2_IRQ);
  370                 else
  371                         return (PIC_PCIE_LINK2_IRQ);
  372         case 3:
  373                 if (xlr_is_xls_b0())
  374                         return (PIC_PCIE_B0_LINK3_IRQ);
  375                 else
  376                         return (PIC_PCIE_LINK3_IRQ);
  377         }
  378         return (-1);
  379 }
  380 
  381 static int
  382 xlr_alloc_msi(device_t pcib, device_t dev, int count, int maxcount, int *irqs)
  383 {
  384         int i, link;
  385 
  386         /*
  387          * Each link has 32 MSIs that can be allocated, but for now
  388          * we only support one device per link.
  389          * msi_alloc() equivalent is needed when we start supporting 
  390          * bridges on the PCIe link.
  391          */
  392         link = xls_pcie_link(pcib, dev);
  393         if (link == -1)
  394                 return (ENXIO);
  395 
  396         /*
  397          * encode the irq so that we know it is a MSI interrupt when we
  398          * setup interrupts
  399          */
  400         for (i = 0; i < count; i++)
  401                 irqs[i] = 64 + link * 32 + i;
  402 
  403         return (0);
  404 }
  405 
  406 static int
  407 xlr_release_msi(device_t pcib, device_t dev, int count, int *irqs)
  408 {
  409         device_printf(dev, "%s: msi release %d\n", device_get_nameunit(pcib),
  410             count);
  411         return (0);
  412 }
  413 
  414 static int
  415 xlr_map_msi(device_t pcib, device_t dev, int irq, uint64_t *addr,
  416     uint32_t *data)
  417 {
  418         int msi;
  419 
  420         if (irq >= 64) {
  421                 msi = irq - 64;
  422                 *addr = MIPS_MSI_ADDR(0);
  423                 *data = MIPS_MSI_DATA(msi);
  424                 return (0);
  425         } else {
  426                 device_printf(dev, "%s: map_msi for irq %d  - ignored", 
  427                     device_get_nameunit(pcib), irq);
  428                 return (ENXIO);
  429         }
  430 }
  431 
  432 static void
  433 bridge_pcix_ack(int irq)
  434 {
  435 
  436         xlr_read_reg(xlr_io_mmio(XLR_IO_PCIX_OFFSET), 0x140 >> 2);
  437 }
  438 
  439 static void
  440 bridge_pcie_ack(int irq)
  441 {
  442         uint32_t reg;
  443         xlr_reg_t *pcie_mmio_le = xlr_io_mmio(XLR_IO_PCIE_1_OFFSET);
  444 
  445         switch (irq) {
  446         case PIC_PCIE_LINK0_IRQ:
  447                 reg = PCIE_LINK0_MSI_STATUS;
  448                 break;
  449         case PIC_PCIE_LINK1_IRQ:
  450                 reg = PCIE_LINK1_MSI_STATUS;
  451                 break;
  452         case PIC_PCIE_LINK2_IRQ:
  453         case PIC_PCIE_B0_LINK2_IRQ:
  454                 reg = PCIE_LINK2_MSI_STATUS;
  455                 break;
  456         case PIC_PCIE_LINK3_IRQ:
  457         case PIC_PCIE_B0_LINK3_IRQ:
  458                 reg = PCIE_LINK3_MSI_STATUS;
  459                 break;
  460         default:
  461                 return;
  462         }
  463         xlr_write_reg(pcie_mmio_le, reg>>2, 0xffffffff);
  464 }
  465 
  466 static int
  467 mips_platform_pci_setup_intr(device_t dev, device_t child,
  468     struct resource *irq, int flags, driver_filter_t *filt,
  469     driver_intr_t *intr, void *arg, void **cookiep)
  470 {
  471         int error = 0;
  472         int xlrirq;
  473 
  474         error = rman_activate_resource(irq);
  475         if (error)
  476                 return error;
  477         if (rman_get_start(irq) != rman_get_end(irq)) {
  478                 device_printf(dev, "Interrupt allocation %lu != %lu\n",
  479                     rman_get_start(irq), rman_get_end(irq));
  480                 return (EINVAL);
  481         }
  482         xlrirq = rman_get_start(irq);
  483 
  484         if (strcmp(device_get_name(dev), "pcib") != 0)
  485                 return (0);
  486 
  487         if (xlr_board_info.is_xls == 0) {
  488                 xlr_establish_intr(device_get_name(child), filt,
  489                     intr, arg, PIC_PCIX_IRQ, flags, cookiep, bridge_pcix_ack);
  490                 pic_setup_intr(PIC_IRT_PCIX_INDEX, PIC_PCIX_IRQ, 0x1, 1);
  491         } else {
  492                 /* 
  493                  * temporary hack for MSI, we support just one device per
  494                  * link, and assign the link interrupt to the device interrupt
  495                  */
  496                 if (xlrirq >= 64) {
  497                         xlrirq -= 64;
  498                         if (xlrirq % 32 != 0)
  499                                 return (0);
  500                         xlrirq = xls_pcie_link_irq(xlrirq / 32);
  501                         if (xlrirq == -1)
  502                                 return (EINVAL);
  503                 }
  504                 xlr_establish_intr(device_get_name(child), filt,
  505                     intr, arg, xlrirq, flags, cookiep, bridge_pcie_ack);
  506                 pic_setup_intr(xlrirq - PIC_IRQ_BASE, xlrirq, 0x1, 1);
  507         }
  508 
  509         return (bus_generic_setup_intr(dev, child, irq, flags, filt, intr,
  510             arg, cookiep));
  511 }
  512 
  513 static int
  514 mips_platform_pci_teardown_intr(device_t dev, device_t child,
  515     struct resource *irq, void *cookie)
  516 {
  517         if (strcmp(device_get_name(child), "pci") == 0) {
  518                 /* if needed reprogram the pic to clear pcix related entry */
  519                 device_printf(dev, "teardown intr\n");
  520         }
  521         return (bus_generic_teardown_intr(dev, child, irq, cookie));
  522 }
  523 
  524 static struct resource *
  525 xlr_pci_alloc_resource(device_t bus, device_t child, int type, int *rid,
  526         u_long start, u_long end, u_long count, u_int flags)
  527 {
  528         struct rman *rm;
  529         struct resource *rv;
  530         vm_offset_t va;
  531         int needactivate = flags & RF_ACTIVE;
  532 
  533         switch (type) {
  534         case SYS_RES_IRQ:
  535                 rm = &irq_rman;
  536                 break;
  537 
  538         case SYS_RES_IOPORT:
  539                 rm = &port_rman;
  540                 break;
  541 
  542         case SYS_RES_MEMORY:
  543                 rm = &mem_rman;
  544                 break;
  545 
  546         default:
  547                 return (0);
  548         }
  549 
  550         rv = rman_reserve_resource(rm, start, end, count, flags, child);
  551         if (rv == 0)
  552                 return (0);
  553 
  554         rman_set_rid(rv, *rid);
  555 
  556         if (type == SYS_RES_MEMORY || type == SYS_RES_IOPORT) {
  557                 va = (vm_offset_t)pmap_mapdev(start, count);
  558                 rman_set_bushandle(rv, va);
  559                 /* bushandle is same as virtual addr */
  560                 rman_set_virtual(rv, (void *)va);
  561                 rman_set_bustag(rv, rmi_pci_bus_space);
  562         }
  563 
  564         if (needactivate) {
  565                 if (bus_activate_resource(child, type, *rid, rv)) {
  566                         rman_release_resource(rv);
  567                         return (NULL);
  568                 }
  569         }
  570         return (rv);
  571 }
  572 
  573 static int
  574 xlr_pci_release_resource(device_t bus, device_t child, int type, int rid,
  575                        struct resource *r)
  576 {
  577 
  578         return (rman_release_resource(r));
  579 }
  580 
  581 static bus_dma_tag_t
  582 xlr_pci_get_dma_tag(device_t bus, device_t child)
  583 {
  584         struct xlr_pcib_softc *sc;
  585 
  586         sc = device_get_softc(bus);
  587         return (sc->sc_pci_dmat);
  588 }
  589 
  590 static int
  591 xlr_pci_activate_resource(device_t bus, device_t child, int type, int rid,
  592                       struct resource *r)
  593 {
  594 
  595         return (rman_activate_resource(r));
  596 }
  597 
  598 static int
  599 xlr_pci_deactivate_resource(device_t bus, device_t child, int type, int rid,
  600                           struct resource *r)
  601 {
  602 
  603         return (rman_deactivate_resource(r));
  604 }
  605 
  606 static int
  607 mips_pci_route_interrupt(device_t bus, device_t dev, int pin)
  608 {
  609         int irq, link;
  610 
  611         /*
  612          * Validate requested pin number.
  613          */
  614         if ((pin < 1) || (pin > 4))
  615                 return (255);
  616 
  617         if (xlr_board_info.is_xls) {
  618                 link = xls_pcie_link(bus, dev);
  619                 irq = xls_pcie_link_irq(link);
  620                 if (irq != -1)
  621                         return (irq);
  622         } else {
  623                 if (pin == 1)
  624                         return (PIC_PCIX_IRQ);
  625         }
  626 
  627         return (255);
  628 }
  629 
  630 static device_method_t xlr_pcib_methods[] = {
  631         /* Device interface */
  632         DEVMETHOD(device_identify, xlr_pcib_identify),
  633         DEVMETHOD(device_probe, xlr_pcib_probe),
  634         DEVMETHOD(device_attach, xlr_pcib_attach),
  635 
  636         /* Bus interface */
  637         DEVMETHOD(bus_read_ivar, xlr_pcib_read_ivar),
  638         DEVMETHOD(bus_write_ivar, xlr_pcib_write_ivar),
  639         DEVMETHOD(bus_alloc_resource, xlr_pci_alloc_resource),
  640         DEVMETHOD(bus_release_resource, xlr_pci_release_resource),
  641         DEVMETHOD(bus_get_dma_tag, xlr_pci_get_dma_tag),
  642         DEVMETHOD(bus_activate_resource, xlr_pci_activate_resource),
  643         DEVMETHOD(bus_deactivate_resource, xlr_pci_deactivate_resource),
  644         DEVMETHOD(bus_setup_intr, mips_platform_pci_setup_intr),
  645         DEVMETHOD(bus_teardown_intr, mips_platform_pci_teardown_intr),
  646 
  647         /* pcib interface */
  648         DEVMETHOD(pcib_maxslots, xlr_pcib_maxslots),
  649         DEVMETHOD(pcib_read_config, xlr_pcib_read_config),
  650         DEVMETHOD(pcib_write_config, xlr_pcib_write_config),
  651         DEVMETHOD(pcib_route_interrupt, mips_pci_route_interrupt),
  652 
  653         DEVMETHOD(pcib_alloc_msi, xlr_alloc_msi),
  654         DEVMETHOD(pcib_release_msi, xlr_release_msi),
  655         DEVMETHOD(pcib_map_msi, xlr_map_msi),
  656 
  657         DEVMETHOD_END
  658 };
  659 
  660 static driver_t xlr_pcib_driver = {
  661         "pcib",
  662         xlr_pcib_methods,
  663         sizeof(struct xlr_pcib_softc),
  664 };
  665 
  666 DRIVER_MODULE(pcib, iodi, xlr_pcib_driver, pcib_devclass, 0, 0);

Cache object: 269259824e0a1fc66500c6ccb834a718


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