1 /*-
2 * Copyright (c) 2010 Aleksandr Rybalko.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 *
26 * $FreeBSD$
27 */
28 #ifndef _RT305X_GPIO_H_
29 #define _RT305X_GPIO_H_
30
31 #define NGPIO 52
32
33 #define RGMII_GPIO_MODE_MASK (0x0fffULL<<40)
34 #define SDRAM_GPIO_MODE_MASK (0xffffULL<<24)
35 #define MDIO_GPIO_MODE_MASK (0x0003ULL<<22)
36 #define JTAG_GPIO_MODE_MASK (0x001fULL<<17)
37 #define UARTL_GPIO_MODE_MASK (0x0003ULL<<15)
38 #define UARTF_GPIO_MODE_MASK (0x00ffULL<<7)
39 #define SPI_GPIO_MODE_MASK (0x000fULL<<3)
40 #define I2C_GPIO_MODE_MASK (0x0003ULL<<1)
41
42 #define GPIO23_00_INT 0x00 /* Programmed I/O Int Status */
43 #define GPIO23_00_EDGE 0x04 /* Programmed I/O Edge Status */
44 #define GPIO23_00_RENA 0x08 /* Programmed I/O Int on Rising */
45 #define GPIO23_00_FENA 0x0C /* Programmed I/O Int on Falling */
46 #define GPIO23_00_DATA 0x20 /* Programmed I/O Data */
47 #define GPIO23_00_DIR 0x24 /* Programmed I/O Direction */
48 #define GPIO23_00_POL 0x28 /* Programmed I/O Pin Polarity */
49 #define GPIO23_00_SET 0x2C /* Set PIO Data Bit */
50 #define GPIO23_00_RESET 0x30 /* Clear PIO Data bit */
51 #define GPIO23_00_TOG 0x34 /* Toggle PIO Data bit */
52
53 #define GPIO39_24_INT 0x38
54 #define GPIO39_24_EDGE 0x3c
55 #define GPIO39_24_RENA 0x40
56 #define GPIO39_24_FENA 0x44
57 #define GPIO39_24_DATA 0x48
58 #define GPIO39_24_DIR 0x4c
59 #define GPIO39_24_POL 0x50
60 #define GPIO39_24_SET 0x54
61 #define GPIO39_24_RESET 0x58
62 #define GPIO39_24_TOG 0x5c
63
64 #define GPIO51_40_INT 0x60
65 #define GPIO51_40_EDGE 0x64
66 #define GPIO51_40_RENA 0x68
67 #define GPIO51_40_FENA 0x6C
68 #define GPIO51_40_DATA 0x70
69 #define GPIO51_40_DIR 0x74
70 #define GPIO51_40_POL 0x78
71 #define GPIO51_40_SET 0x7C
72 #define GPIO51_40_RESET 0x80
73 #define GPIO51_40_TOG 0x84
74
75 #define GPIO_REG(g, n) \
76 ((g<24)?(GPIO23_00_##n):(g<40)?(GPIO39_24_##n):(GPIO51_40_##n))
77 #define GPIO_MASK(g) \
78 ((g<24)?(1<<g):(g<40)?(1<<(g-24)):(1<<(g-40)))
79 #define GPIO_BIT_SHIFT(g) ((g<24)?(g):(g<40)?(g-24):(g-40))
80
81 #define GPIO_READ(r, g, n) \
82 bus_read_4(r->gpio_mem_res, GPIO_REG(g, n))
83 #define GPIO_WRITE(r, g, n, v) \
84 bus_write_4(r->gpio_mem_res, GPIO_REG(g, n), v)
85 #define GPIO_READ_ALL(r, n) \
86 (((uint64_t)bus_read_4(r->gpio_mem_res, GPIO23_00_##n)) | \
87 (((uint64_t)bus_read_4(r->gpio_mem_res, GPIO39_24_##n)) << 24) |\
88 (((uint64_t)bus_read_4(r->gpio_mem_res, GPIO51_40_##n)) << 40))
89 #define GPIO_WRITE_ALL(r, n, v) \
90 {bus_write_4(r->gpio_mem_res,GPIO23_00_##n, v &0x00ffffff);\
91 bus_write_4(r->gpio_mem_res, GPIO39_24_##n, (v>>24)&0x0000ffff);\
92 bus_write_4(r->gpio_mem_res, GPIO51_40_##n, (v>>40)&0x00000fff);}
93
94
95 #define GPIO_BIT_CLR(r, g, n) \
96 bus_write_4(r->gpio_mem_res, GPIO_REG(g, n), \
97 bus_read_4(r->gpio_mem_res, GPIO_REG(g, n)) & ~GPIO_MASK(g))
98 #define GPIO_BIT_SET(r, g, n) \
99 bus_write_4(r->gpio_mem_res, GPIO_REG(g, n), \
100 bus_read_4(r->gpio_mem_res, GPIO_REG(g, n)) | GPIO_MASK(g))
101
102 #define GPIO_BIT_GET(r, g, n) \
103 ((bus_read_4(r->gpio_mem_res, GPIO_REG(g, n)) >> \
104 GPIO_BIT_SHIFT(g)) & 1)
105
106 #define GPIO_LOCK(_sc) mtx_lock(&(_sc)->gpio_mtx)
107 #define GPIO_UNLOCK(_sc) mtx_unlock(&(_sc)->gpio_mtx)
108 #define GPIO_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->gpio_mtx, MA_OWNED)
109
110 #endif /* _RT305X_GPIO_H_ */
111
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