The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


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FreeBSD/Linux Kernel Cross Reference
sys/mips/rt305x/rt305x_sysctl.c

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    1 /*-
    2  * Copyright (c) 2010 Aleksandr Rybalko.
    3  * All rights reserved.
    4  *
    5  * Redistribution and use in source and binary forms, with or without
    6  * modification, are permitted provided that the following conditions
    7  * are met:
    8  * 1. Redistributions of source code must retain the above copyright
    9  *    notice, this list of conditions and the following disclaimer.
   10  * 2. Redistributions in binary form must reproduce the above copyright
   11  *    notice, this list of conditions and the following disclaimer in the
   12  *    documentation and/or other materials provided with the distribution.
   13  *
   14  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
   15  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   16  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   17  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
   18  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
   19  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
   20  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
   21  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
   22  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   23  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   24  * SUCH DAMAGE.
   25  */
   26 
   27 #include <sys/cdefs.h>
   28 __FBSDID("$FreeBSD$");
   29 
   30 #include <sys/param.h>
   31 #include <sys/systm.h>
   32 #include <sys/bus.h>
   33 #include <sys/interrupt.h>
   34 #include <sys/kernel.h>
   35 #include <sys/module.h>
   36 #include <sys/rman.h>
   37 #include <sys/malloc.h>
   38 
   39 #include <machine/bus.h>
   40 
   41 #include <mips/rt305x/rt305xreg.h>
   42 #include <mips/rt305x/rt305x_sysctlvar.h>
   43 
   44 
   45 static int      rt305x_sysctl_probe(device_t);
   46 static int      rt305x_sysctl_attach(device_t);
   47 static int      rt305x_sysctl_detach(device_t);
   48 
   49 
   50 static struct rt305x_sysctl_softc *rt305x_sysctl_softc = NULL;
   51 
   52 static void
   53 rt305x_sysctl_dump_config(device_t dev)
   54 {
   55         uint32_t val;
   56 #define DUMPREG(r)                                                      \
   57         val = rt305x_sysctl_get(r); printf("    " #r "=%#08x\n", val)
   58 
   59         val = rt305x_sysctl_get(SYSCTL_CHIPID0_3);
   60         printf("\tChip ID: \"%c%c%c%c", 
   61             (val >> 0 ) & 0xff, 
   62             (val >> 8 ) & 0xff, 
   63             (val >> 16) & 0xff, 
   64             (val >> 24) & 0xff);
   65         val = rt305x_sysctl_get(SYSCTL_CHIPID4_7);
   66         printf("%c%c%c%c\"\n", 
   67             (val >> 0 ) & 0xff, 
   68             (val >> 8 ) & 0xff, 
   69             (val >> 16) & 0xff, 
   70             (val >> 24) & 0xff);
   71 
   72         DUMPREG(SYSCTL_SYSCFG);
   73 #if !defined(RT5350) && !defined(MT7620)
   74         if ( val & SYSCTL_SYSCFG_INIC_EE_SDRAM)
   75                 printf("\tGet SDRAM config from EEPROM\n");
   76         if ( val & SYSCTL_SYSCFG_INIC_8MB_SDRAM)
   77                 printf("\tBootstrap flag is set\n");
   78         printf("\tGE0 mode %u\n",
   79             ((val & SYSCTL_SYSCFG_GE0_MODE_MASK) >> 
   80                 SYSCTL_SYSCFG_GE0_MODE_SHIFT));
   81         if ( val & SYSCTL_SYSCFG_BOOT_ADDR_1F00)
   82                 printf("\tBoot from 0x1f000000\n");
   83         if ( val & SYSCTL_SYSCFG_BYPASS_PLL)
   84                 printf("\tBypass PLL\n");
   85         if ( val & SYSCTL_SYSCFG_BIG_ENDIAN)
   86                 printf("\tBig Endian\n");
   87         if ( val & SYSCTL_SYSCFG_CPU_CLK_SEL_384MHZ)
   88                 printf("\tClock is 384MHz\n");
   89         printf("\tBoot from %u\n",
   90             ((val & SYSCTL_SYSCFG_BOOT_FROM_MASK) >> 
   91                 SYSCTL_SYSCFG_BOOT_FROM_SHIFT));
   92         printf("\tBootstrap test code %u\n",
   93             ((val & SYSCTL_SYSCFG_TEST_CODE_MASK) >> 
   94                 SYSCTL_SYSCFG_TEST_CODE_SHIFT));
   95         printf("\tSRAM_CS mode %u\n",
   96             ((val & SYSCTL_SYSCFG_SRAM_CS_MODE_MASK) >> 
   97                 SYSCTL_SYSCFG_SRAM_CS_MODE_SHIFT));
   98         printf("\t%umA SDRAM_CLK driving\n",
   99             (val & SYSCTL_SYSCFG_SDRAM_CLK_DRV)?12:8);
  100 
  101         DUMPREG(SYSCTL_CLKCFG0);
  102         printf("\tSDRAM_CLK_SKEW %uns\n", (val >> 30) & 0x03);
  103 
  104         DUMPREG(SYSCTL_CLKCFG1);
  105         if ( val & SYSCTL_CLKCFG1_PBUS_DIV_CLK_BY2)
  106                 printf("\tPbus clock is 1/2 of System clock\n");
  107         if ( val & SYSCTL_CLKCFG1_OTG_CLK_EN)
  108                 printf("\tUSB OTG clock is enabled\n");
  109         if ( val & SYSCTL_CLKCFG1_I2S_CLK_EN)
  110                 printf("\tI2S clock is enabled\n");
  111         printf("\tI2S clock is %s\n", 
  112             (val & SYSCTL_CLKCFG1_I2S_CLK_SEL_EXT)?
  113                 "external":"internal 15.625MHz");
  114         printf("\tI2S clock divider %u\n",
  115             ((val & SYSCTL_CLKCFG1_I2S_CLK_DIV_MASK) >> 
  116                 SYSCTL_CLKCFG1_I2S_CLK_DIV_SHIFT));
  117         if ( val & SYSCTL_CLKCFG1_PCM_CLK_EN)
  118                 printf("\tPCM clock is enabled\n");
  119 
  120         printf("\tPCM clock is %s\n", 
  121             (val & SYSCTL_CLKCFG1_PCM_CLK_SEL_EXT)?
  122                 "external":"internal 15.625MHz");
  123         printf("\tPCM clock divider %u\n",
  124             ((val & SYSCTL_CLKCFG1_PCM_CLK_DIV_MASK) >> 
  125                 SYSCTL_CLKCFG1_PCM_CLK_DIV_SHIFT));
  126         DUMPREG(SYSCTL_GPIOMODE);
  127 #endif
  128 #undef DUMPREG
  129 
  130         return;
  131 }
  132 
  133 static int
  134 rt305x_sysctl_probe(device_t dev)
  135 {
  136         device_set_desc(dev, "RT305X System Control driver");
  137         return (0);
  138 }
  139 
  140 static int
  141 rt305x_sysctl_attach(device_t dev)
  142 {
  143         struct rt305x_sysctl_softc *sc = device_get_softc(dev);
  144         int error = 0;
  145 
  146         KASSERT((device_get_unit(dev) == 0),
  147             ("rt305x_sysctl: Only one sysctl module supported"));
  148 
  149         if (rt305x_sysctl_softc != NULL)
  150                 return (ENXIO);
  151         rt305x_sysctl_softc = sc;
  152 
  153 
  154         /* Map control/status registers. */
  155         sc->mem_rid = 0;
  156         sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
  157             &sc->mem_rid, RF_ACTIVE);
  158 
  159         if (sc->mem_res == NULL) {
  160                 device_printf(dev, "couldn't map memory\n");
  161                 error = ENXIO;
  162                 rt305x_sysctl_detach(dev);
  163                 return(error);
  164         }
  165 #ifdef notyet
  166         sc->irq_rid = 0;
  167         if ((sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, 
  168             &sc->irq_rid, RF_SHAREABLE | RF_ACTIVE)) == NULL) {
  169                 device_printf(dev, "unable to allocate IRQ resource\n");
  170                 return (ENXIO);
  171         }
  172 
  173         if ((bus_setup_intr(dev, sc->irq_res, INTR_TYPE_MISC, 
  174             rt305x_sysctl_intr, NULL, sc, &sc->sysctl_ih))) {
  175                 device_printf(dev,
  176                     "WARNING: unable to register interrupt handler\n");
  177                 return (ENXIO);
  178         }
  179 #endif
  180         rt305x_sysctl_dump_config(dev);
  181 
  182         return (bus_generic_attach(dev));
  183 }
  184 
  185 static int
  186 rt305x_sysctl_detach(device_t dev)
  187 {
  188         struct rt305x_sysctl_softc *sc = device_get_softc(dev);
  189 
  190         bus_generic_detach(dev);
  191 
  192         if (sc->mem_res)
  193                 bus_release_resource(dev, SYS_RES_MEMORY, sc->mem_rid,
  194                     sc->mem_res);
  195 #ifdef notyet
  196         if (sc->irq_res)
  197                 bus_release_resource(dev, SYS_RES_IRQ, sc->irq_rid,
  198                     sc->irq_res);
  199 #endif
  200         return(0);
  201 }
  202 
  203 #ifdef notyet
  204 static int
  205 rt305x_sysctl_intr(void *arg)
  206 {
  207         return (FILTER_HANDLED);
  208 }
  209 #endif
  210 
  211 uint32_t
  212 rt305x_sysctl_get(uint32_t reg)
  213 {
  214         struct rt305x_sysctl_softc *sc = rt305x_sysctl_softc;
  215         return (bus_read_4(sc->mem_res, reg));
  216 }
  217 
  218 void
  219 rt305x_sysctl_set(uint32_t reg, uint32_t val)
  220 {
  221         struct rt305x_sysctl_softc *sc = rt305x_sysctl_softc;
  222         bus_write_4(sc->mem_res, reg, val);
  223         return;
  224 }
  225 
  226 
  227 static device_method_t rt305x_sysctl_methods[] = {
  228         DEVMETHOD(device_probe,                 rt305x_sysctl_probe),
  229         DEVMETHOD(device_attach,                rt305x_sysctl_attach),
  230         DEVMETHOD(device_detach,                rt305x_sysctl_detach),
  231 
  232         {0, 0},
  233 };
  234 
  235 static driver_t rt305x_sysctl_driver = {
  236         "rt305x_sysctl",
  237         rt305x_sysctl_methods,
  238         sizeof(struct rt305x_sysctl_softc),
  239 };
  240 static devclass_t rt305x_sysctl_devclass;
  241 
  242 DRIVER_MODULE(rt305x_sysctl, obio, rt305x_sysctl_driver, rt305x_sysctl_devclass, 0, 0);

Cache object: 2721adc514f16f1fb3b5fd049dad0678


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