1 /*-
2 * Copyright (c) 2007 Bruce M. Simpson.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 */
26
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD: releng/8.1/sys/mips/sentry5/s5_machdep.c 183372 2008-09-26 04:45:56Z imp $");
29
30 #include <sys/param.h>
31 #include <machine/cpuregs.h>
32
33 #include <mips/sentry5/s5reg.h>
34
35 #include "opt_ddb.h"
36
37 #include <sys/param.h>
38 #include <sys/conf.h>
39 #include <sys/kernel.h>
40 #include <sys/systm.h>
41 #include <sys/imgact.h>
42 #include <sys/bio.h>
43 #include <sys/buf.h>
44 #include <sys/bus.h>
45 #include <sys/cpu.h>
46 #include <sys/cons.h>
47 #include <sys/exec.h>
48 #include <sys/ucontext.h>
49 #include <sys/proc.h>
50 #include <sys/kdb.h>
51 #include <sys/ptrace.h>
52 #include <sys/reboot.h>
53 #include <sys/signalvar.h>
54 #include <sys/sysent.h>
55 #include <sys/sysproto.h>
56 #include <sys/user.h>
57
58 #include <vm/vm.h>
59 #include <vm/vm_object.h>
60 #include <vm/vm_page.h>
61 #include <vm/vm_pager.h>
62
63 #include <machine/cache.h>
64 #include <machine/clock.h>
65 #include <machine/cpu.h>
66 #include <machine/cpuinfo.h>
67 #include <machine/cpufunc.h>
68 #include <machine/cpuregs.h>
69 #include <machine/hwfunc.h>
70 #include <machine/intr_machdep.h>
71 #include <machine/locore.h>
72 #include <machine/md_var.h>
73 #include <machine/pte.h>
74 #include <machine/sigframe.h>
75 #include <machine/trap.h>
76 #include <machine/vmparam.h>
77
78 #ifdef CFE
79 #include <dev/cfe/cfe_api.h>
80 #endif
81
82 #ifdef CFE
83 extern uint32_t cfe_handle;
84 extern uint32_t cfe_vector;
85 #endif
86
87 extern int *edata;
88 extern int *end;
89
90 static void
91 mips_init(void)
92 {
93 int i;
94
95 printf("entry: mips_init()\n");
96
97 #ifdef CFE
98 /*
99 * Query DRAM memory map from CFE.
100 */
101 physmem = 0;
102 for (i = 0; i < 10; i += 2) {
103 int result;
104 uint64_t addr, len, type;
105
106 result = cfe_enummem(i, 0, &addr, &len, &type);
107 if (result < 0) {
108 phys_avail[i] = phys_avail[i + 1] = 0;
109 break;
110 }
111 if (type != CFE_MI_AVAILABLE)
112 continue;
113
114 phys_avail[i] = addr;
115 if (i == 0 && addr == 0) {
116 /*
117 * If this is the first physical memory segment probed
118 * from CFE, omit the region at the start of physical
119 * memory where the kernel has been loaded.
120 */
121 phys_avail[i] += MIPS_KSEG0_TO_PHYS((vm_offset_t)&end);
122 }
123 phys_avail[i + 1] = addr + len;
124 physmem += len;
125 }
126
127 realmem = btoc(physmem);
128 #endif
129
130 physmem = realmem;
131
132 init_param1();
133 init_param2(physmem);
134 mips_cpu_init();
135 pmap_bootstrap();
136 mips_proc0_init();
137 mutex_init();
138 #ifdef DDB
139 kdb_init();
140 #endif
141 }
142
143 void
144 platform_halt(void)
145 {
146
147 }
148
149
150 void
151 platform_identify(void)
152 {
153
154 }
155
156 void
157 platform_reset(void)
158 {
159
160 #if defined(CFE)
161 cfe_exit(0, 0);
162 #else
163 *((volatile uint8_t *)MIPS_PHYS_TO_KSEG1(SENTRY5_EXTIFADR)) = 0x80;
164 #endif
165 }
166
167 void
168 platform_trap_enter(void)
169 {
170
171 }
172
173 void
174 platform_trap_exit(void)
175 {
176
177 }
178
179 void
180 platform_start(__register_t a0 __unused, __register_t a1 __unused,
181 __register_t a2 __unused, __register_t a3 __unused)
182 {
183 vm_offset_t kernend;
184 uint64_t platform_counter_freq;
185
186 /* clear the BSS and SBSS segments */
187 kernend = round_page((vm_offset_t)&end);
188 memset(&edata, 0, kernend - (vm_offset_t)(&edata));
189
190 #ifdef CFE
191 /*
192 * Initialize CFE firmware trampolines before
193 * we initialize the low-level console.
194 */
195 if (cfe_handle != 0)
196 cfe_init(cfe_handle, cfe_vector);
197 #endif
198 cninit();
199
200 #ifdef CFE
201 if (cfe_handle == 0)
202 panic("CFE was not detected by locore.\n");
203 #endif
204 mips_init();
205
206 # if 0
207 /*
208 * Probe the Broadcom Sentry5's on-chip PLL clock registers
209 * and discover the CPU pipeline clock and bus clock
210 * multipliers from this.
211 * XXX: Wrong place. You have to ask the ChipCommon
212 * or External Interface cores on the SiBa.
213 */
214 uint32_t busmult, cpumult, refclock, clkcfg1;
215 #define S5_CLKCFG1_REFCLOCK_MASK 0x0000001F
216 #define S5_CLKCFG1_BUSMULT_MASK 0x000003E0
217 #define S5_CLKCFG1_BUSMULT_SHIFT 5
218 #define S5_CLKCFG1_CPUMULT_MASK 0xFFFFFC00
219 #define S5_CLKCFG1_CPUMULT_SHIFT 10
220
221 counter_freq = 100000000; /* XXX */
222
223 clkcfg1 = s5_rd_clkcfg1();
224 printf("clkcfg1 = 0x%08x\n", clkcfg1);
225
226 refclock = clkcfg1 & 0x1F;
227 busmult = ((clkcfg1 & 0x000003E0) >> 5) + 1;
228 cpumult = ((clkcfg1 & 0xFFFFFC00) >> 10) + 1;
229
230 printf("refclock = %u\n", refclock);
231 printf("busmult = %u\n", busmult);
232 printf("cpumult = %u\n", cpumult);
233
234 counter_freq = cpumult * refclock;
235 # else
236 platform_counter_freq = 200 * 1000 * 1000; /* Sentry5 is 200MHz */
237 # endif
238
239 mips_timer_init_params(platform_counter_freq, 0);
240 }
Cache object: bd10270a6cdfb174df55dfde27732cf2
|