1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
3 *
4 * Copyright (c) 2009 Neelkanth Natu
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 */
28
29 #include <sys/param.h>
30 #include <sys/types.h>
31 #include <sys/kernel.h>
32 #include <sys/systm.h>
33 #include <sys/module.h>
34 #include <sys/bus.h>
35 #include <sys/rman.h>
36 #include <sys/pcpu.h>
37 #include <sys/smp.h>
38
39 #include <vm/vm.h>
40 #include <vm/vm_param.h>
41 #include <vm/vm_kern.h>
42 #include <vm/vm_extern.h>
43 #include <vm/pmap.h>
44
45 #include <dev/pci/pcireg.h>
46 #include <dev/pci/pcivar.h>
47 #include <dev/pci/pcib_private.h>
48
49 #include <machine/resource.h>
50 #include <machine/bus.h>
51
52 #include "pcib_if.h"
53
54 #include "sb_bus_space.h"
55 #include "sb_scd.h"
56
57 __FBSDID("$FreeBSD: releng/12.0/sys/mips/sibyte/sb_zbpci.c 326259 2017-11-27 15:07:26Z pfg $");
58
59 static struct {
60 vm_offset_t vaddr;
61 vm_paddr_t paddr;
62 } zbpci_config_space[MAXCPU];
63
64 static const vm_paddr_t CFG_PADDR_BASE = 0xFE000000;
65 static const u_long PCI_IOSPACE_ADDR = 0xFC000000;
66 static const u_long PCI_IOSPACE_SIZE = 0x02000000;
67
68 #define PCI_MATCH_BYTE_LANES_START 0x40000000
69 #define PCI_MATCH_BYTE_LANES_END 0x5FFFFFFF
70 #define PCI_MATCH_BYTE_LANES_SIZE 0x20000000
71
72 #define PCI_MATCH_BIT_LANES_MASK (1 << 29)
73 #define PCI_MATCH_BIT_LANES_START 0x60000000
74 #define PCI_MATCH_BIT_LANES_END 0x7FFFFFFF
75 #define PCI_MATCH_BIT_LANES_SIZE 0x20000000
76
77 static struct rman port_rman;
78
79 static int
80 zbpci_probe(device_t dev)
81 {
82
83 device_set_desc(dev, "Broadcom/Sibyte PCI I/O Bridge");
84 return (0);
85 }
86
87 static int
88 zbpci_attach(device_t dev)
89 {
90 int n, rid, size;
91 vm_offset_t va;
92 struct resource *res;
93
94 /*
95 * Reserve the physical memory window used to map PCI I/O space.
96 */
97 rid = 0;
98 res = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid,
99 PCI_IOSPACE_ADDR,
100 PCI_IOSPACE_ADDR + PCI_IOSPACE_SIZE - 1,
101 PCI_IOSPACE_SIZE, 0);
102 if (res == NULL)
103 panic("Cannot allocate resource for PCI I/O space mapping.");
104
105 port_rman.rm_start = 0;
106 port_rman.rm_end = PCI_IOSPACE_SIZE - 1;
107 port_rman.rm_type = RMAN_ARRAY;
108 port_rman.rm_descr = "PCI I/O ports";
109 if (rman_init(&port_rman) != 0 ||
110 rman_manage_region(&port_rman, 0, PCI_IOSPACE_SIZE - 1) != 0)
111 panic("%s: port_rman", __func__);
112
113 /*
114 * Reserve the physical memory that is used to read/write to the
115 * pci config space but don't activate it. We are using a page worth
116 * of KVA as a window over this region.
117 */
118 rid = 1;
119 size = (PCI_BUSMAX + 1) * (PCI_SLOTMAX + 1) * (PCI_FUNCMAX + 1) * 256;
120 res = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid, CFG_PADDR_BASE,
121 CFG_PADDR_BASE + size - 1, size, 0);
122 if (res == NULL)
123 panic("Cannot allocate resource for config space accesses.");
124
125 /*
126 * Allocate the entire "match bit lanes" address space.
127 */
128 #if _BYTE_ORDER == _BIG_ENDIAN
129 rid = 2;
130 res = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid,
131 PCI_MATCH_BIT_LANES_START,
132 PCI_MATCH_BIT_LANES_END,
133 PCI_MATCH_BIT_LANES_SIZE, 0);
134 if (res == NULL)
135 panic("Cannot allocate resource for pci match bit lanes.");
136 #endif /* _BYTE_ORDER ==_BIG_ENDIAN */
137
138 /*
139 * Allocate KVA for accessing PCI config space.
140 */
141 va = kva_alloc(PAGE_SIZE * mp_ncpus);
142 if (va == 0) {
143 device_printf(dev, "Cannot allocate virtual addresses for "
144 "config space access.\n");
145 return (ENOMEM);
146 }
147
148 for (n = 0; n < mp_ncpus; ++n)
149 zbpci_config_space[n].vaddr = va + n * PAGE_SIZE;
150
151 /*
152 * Sibyte has the PCI bus hierarchy rooted at bus 0 and HT-PCI
153 * hierarchy rooted at bus 1.
154 */
155 if (device_add_child(dev, "pci", 0) == NULL)
156 panic("zbpci_attach: could not add pci bus 0.\n");
157
158 if (device_add_child(dev, "pci", 1) == NULL)
159 panic("zbpci_attach: could not add pci bus 1.\n");
160
161 if (bootverbose)
162 device_printf(dev, "attached.\n");
163
164 return (bus_generic_attach(dev));
165 }
166
167 static struct resource *
168 zbpci_alloc_resource(device_t bus, device_t child, int type, int *rid,
169 rman_res_t start, rman_res_t end, rman_res_t count, u_int flags)
170 {
171 struct resource *res;
172
173 /*
174 * Handle PCI I/O port resources here and pass everything else to nexus.
175 */
176 if (type != SYS_RES_IOPORT) {
177 res = bus_generic_alloc_resource(bus, child, type, rid,
178 start, end, count, flags);
179 return (res);
180 }
181
182 res = rman_reserve_resource(&port_rman, start, end, count,
183 flags, child);
184 if (res == NULL)
185 return (NULL);
186
187 rman_set_rid(res, *rid);
188
189 /* Activate the resource is requested */
190 if (flags & RF_ACTIVE) {
191 if (bus_activate_resource(child, type, *rid, res) != 0) {
192 rman_release_resource(res);
193 return (NULL);
194 }
195 }
196
197 return (res);
198 }
199
200 static int
201 zbpci_activate_resource(device_t bus, device_t child, int type, int rid,
202 struct resource *res)
203 {
204 int error;
205 void *vaddr;
206 u_long orig_paddr, paddr, psize;
207
208 paddr = rman_get_start(res);
209 psize = rman_get_size(res);
210 orig_paddr = paddr;
211
212 #if _BYTE_ORDER == _BIG_ENDIAN
213 /*
214 * The CFE allocates PCI memory resources that map to the
215 * "match byte lanes" address space. This address space works
216 * best for DMA transfers because it does not do any automatic
217 * byte swaps when data crosses the pci-cpu interface.
218 *
219 * This also makes it sub-optimal for accesses to PCI device
220 * registers because it exposes the little-endian nature of
221 * the PCI bus to the big-endian CPU. The Sibyte has another
222 * address window called the "match bit lanes" window which
223 * automatically swaps bytes when data crosses the pci-cpu
224 * interface.
225 *
226 * We "assume" that any bus_space memory accesses done by the
227 * CPU to a PCI device are register/configuration accesses and
228 * are done through the "match bit lanes" window. Any DMA
229 * transfers will continue to be through the "match byte lanes"
230 * window because the PCI BAR registers will not be changed.
231 */
232 if (type == SYS_RES_MEMORY) {
233 if (paddr >= PCI_MATCH_BYTE_LANES_START &&
234 paddr + psize - 1 <= PCI_MATCH_BYTE_LANES_END) {
235 paddr |= PCI_MATCH_BIT_LANES_MASK;
236 rman_set_start(res, paddr);
237 rman_set_end(res, paddr + psize - 1);
238 }
239 }
240 #endif
241
242 if (type != SYS_RES_IOPORT) {
243 error = bus_generic_activate_resource(bus, child, type,
244 rid, res);
245 #if _BYTE_ORDER == _BIG_ENDIAN
246 if (type == SYS_RES_MEMORY) {
247 rman_set_start(res, orig_paddr);
248 rman_set_end(res, orig_paddr + psize - 1);
249 }
250 #endif
251 return (error);
252 }
253
254 /*
255 * Map the I/O space resource through the memory window starting
256 * at PCI_IOSPACE_ADDR.
257 */
258 vaddr = pmap_mapdev(paddr + PCI_IOSPACE_ADDR, psize);
259
260 rman_set_virtual(res, vaddr);
261 rman_set_bustag(res, mips_bus_space_generic);
262 rman_set_bushandle(res, (bus_space_handle_t)vaddr);
263
264 return (rman_activate_resource(res));
265 }
266
267 static int
268 zbpci_release_resource(device_t bus, device_t child, int type, int rid,
269 struct resource *r)
270 {
271 int error;
272
273 if (type != SYS_RES_IOPORT)
274 return (bus_generic_release_resource(bus, child, type, rid, r));
275
276 if (rman_get_flags(r) & RF_ACTIVE) {
277 error = bus_deactivate_resource(child, type, rid, r);
278 if (error)
279 return (error);
280 }
281
282 return (rman_release_resource(r));
283 }
284
285 static int
286 zbpci_deactivate_resource(device_t bus, device_t child, int type, int rid,
287 struct resource *r)
288 {
289 vm_offset_t va;
290
291 if (type != SYS_RES_IOPORT) {
292 return (bus_generic_deactivate_resource(bus, child, type,
293 rid, r));
294 }
295
296 va = (vm_offset_t)rman_get_virtual(r);
297 pmap_unmapdev(va, rman_get_size(r));
298
299 return (rman_deactivate_resource(r));
300 }
301
302 static int
303 zbpci_read_ivar(device_t dev, device_t child, int which, uintptr_t *result)
304 {
305
306 switch (which) {
307 case PCIB_IVAR_DOMAIN:
308 *result = 0; /* single PCI domain */
309 return (0);
310 case PCIB_IVAR_BUS:
311 *result = device_get_unit(child); /* PCI bus 0 or 1 */
312 return (0);
313 default:
314 return (ENOENT);
315 }
316 }
317
318 /*
319 * We rely on the CFE to have configured the intline correctly to point to
320 * one of PCI-A/PCI-B/PCI-C/PCI-D in the interupt mapper.
321 */
322 static int
323 zbpci_route_interrupt(device_t pcib, device_t dev, int pin)
324 {
325
326 return (PCI_INVALID_IRQ);
327 }
328
329 /*
330 * This function is expected to be called in a critical section since it
331 * changes the per-cpu pci config space va-to-pa mappings.
332 */
333 static vm_offset_t
334 zbpci_config_space_va(int bus, int slot, int func, int reg, int bytes)
335 {
336 int cpu;
337 vm_offset_t va_page;
338 vm_paddr_t pa, pa_page;
339
340 if (bus <= PCI_BUSMAX && slot <= PCI_SLOTMAX && func <= PCI_FUNCMAX &&
341 reg <= PCI_REGMAX && (bytes == 1 || bytes == 2 || bytes == 4) &&
342 ((reg & (bytes - 1)) == 0)) {
343 cpu = PCPU_GET(cpuid);
344 va_page = zbpci_config_space[cpu].vaddr;
345 pa = CFG_PADDR_BASE |
346 (bus << 16) | (slot << 11) | (func << 8) | reg;
347 #if _BYTE_ORDER == _BIG_ENDIAN
348 pa = pa ^ (4 - bytes);
349 #endif
350 pa_page = rounddown2(pa, PAGE_SIZE);
351 if (zbpci_config_space[cpu].paddr != pa_page) {
352 pmap_kremove(va_page);
353 pmap_kenter_attr(va_page, pa_page, PTE_C_UNCACHED);
354 zbpci_config_space[cpu].paddr = pa_page;
355 }
356 return (va_page + (pa - pa_page));
357 } else {
358 return (0);
359 }
360 }
361
362 static uint32_t
363 zbpci_read_config(device_t dev, u_int b, u_int s, u_int f, u_int r, int w)
364 {
365 uint32_t data;
366 vm_offset_t va;
367
368 critical_enter();
369
370 va = zbpci_config_space_va(b, s, f, r, w);
371 if (va == 0) {
372 panic("zbpci_read_config: invalid %d/%d/%d[%d] %d\n",
373 b, s, f, r, w);
374 }
375
376 switch (w) {
377 case 4:
378 data = *(uint32_t *)va;
379 break;
380 case 2:
381 data = *(uint16_t *)va;
382 break;
383 case 1:
384 data = *(uint8_t *)va;
385 break;
386 default:
387 panic("zbpci_read_config: invalid width %d\n", w);
388 }
389
390 critical_exit();
391
392 return (data);
393 }
394
395 static void
396 zbpci_write_config(device_t d, u_int b, u_int s, u_int f, u_int r,
397 uint32_t data, int w)
398 {
399 vm_offset_t va;
400
401 critical_enter();
402
403 va = zbpci_config_space_va(b, s, f, r, w);
404 if (va == 0) {
405 panic("zbpci_write_config: invalid %d/%d/%d[%d] %d/%d\n",
406 b, s, f, r, data, w);
407 }
408
409 switch (w) {
410 case 4:
411 *(uint32_t *)va = data;
412 break;
413 case 2:
414 *(uint16_t *)va = data;
415 break;
416 case 1:
417 *(uint8_t *)va = data;
418 break;
419 default:
420 panic("zbpci_write_config: invalid width %d\n", w);
421 }
422
423 critical_exit();
424 }
425
426 static device_method_t zbpci_methods[] ={
427 /* Device interface */
428 DEVMETHOD(device_probe, zbpci_probe),
429 DEVMETHOD(device_attach, zbpci_attach),
430 DEVMETHOD(device_detach, bus_generic_detach),
431 DEVMETHOD(device_shutdown, bus_generic_shutdown),
432 DEVMETHOD(device_suspend, bus_generic_suspend),
433 DEVMETHOD(device_resume, bus_generic_resume),
434
435 /* Bus interface */
436 DEVMETHOD(bus_read_ivar, zbpci_read_ivar),
437 DEVMETHOD(bus_write_ivar, bus_generic_write_ivar),
438 DEVMETHOD(bus_alloc_resource, zbpci_alloc_resource),
439 DEVMETHOD(bus_activate_resource, zbpci_activate_resource),
440 DEVMETHOD(bus_deactivate_resource, zbpci_deactivate_resource),
441 DEVMETHOD(bus_release_resource, zbpci_release_resource),
442 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr),
443 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr),
444 DEVMETHOD(bus_add_child, bus_generic_add_child),
445
446 /* pcib interface */
447 DEVMETHOD(pcib_maxslots, pcib_maxslots),
448 DEVMETHOD(pcib_read_config, zbpci_read_config),
449 DEVMETHOD(pcib_write_config, zbpci_write_config),
450 DEVMETHOD(pcib_route_interrupt, zbpci_route_interrupt),
451 DEVMETHOD(pcib_request_feature, pcib_request_feature_allow),
452
453 { 0, 0 }
454 };
455
456 /*
457 * The "zbpci" class inherits from the "pcib" base class. Therefore in
458 * addition to drivers that belong to the "zbpci" class we will also
459 * consider drivers belonging to the "pcib" when probing children of
460 * "zbpci".
461 */
462 DEFINE_CLASS_1(zbpci, zbpci_driver, zbpci_methods, 0, pcib_driver);
463
464 static devclass_t zbpci_devclass;
465
466 DRIVER_MODULE(zbpci, zbbus, zbpci_driver, zbpci_devclass, 0, 0);
467
468 /*
469 * Big endian bus space routines
470 */
471 #if _BYTE_ORDER == _BIG_ENDIAN
472
473 /*
474 * The CPU correctly deals with the big-endian to little-endian swap if
475 * we are accessing 4 bytes at a time. However if we want to read 1 or 2
476 * bytes then we need to fudge the address generated by the CPU such that
477 * it generates the right byte enables on the PCI bus.
478 */
479 static bus_addr_t
480 sb_match_bit_lane_addr(bus_addr_t addr, int bytes)
481 {
482 vm_offset_t pa;
483
484 pa = vtophys(addr);
485
486 if (pa >= PCI_MATCH_BIT_LANES_START && pa <= PCI_MATCH_BIT_LANES_END)
487 return (addr ^ (4 - bytes));
488 else
489 return (addr);
490 }
491
492 uint8_t
493 sb_big_endian_read8(bus_addr_t addr)
494 {
495 bus_addr_t addr2;
496
497 addr2 = sb_match_bit_lane_addr(addr, 1);
498 return (readb(addr2));
499 }
500
501 uint16_t
502 sb_big_endian_read16(bus_addr_t addr)
503 {
504 bus_addr_t addr2;
505
506 addr2 = sb_match_bit_lane_addr(addr, 2);
507 return (readw(addr2));
508 }
509
510 uint32_t
511 sb_big_endian_read32(bus_addr_t addr)
512 {
513 bus_addr_t addr2;
514
515 addr2 = sb_match_bit_lane_addr(addr, 4);
516 return (readl(addr2));
517 }
518
519 void
520 sb_big_endian_write8(bus_addr_t addr, uint8_t val)
521 {
522 bus_addr_t addr2;
523
524 addr2 = sb_match_bit_lane_addr(addr, 1);
525 writeb(addr2, val);
526 }
527
528 void
529 sb_big_endian_write16(bus_addr_t addr, uint16_t val)
530 {
531 bus_addr_t addr2;
532
533 addr2 = sb_match_bit_lane_addr(addr, 2);
534 writew(addr2, val);
535 }
536
537 void
538 sb_big_endian_write32(bus_addr_t addr, uint32_t val)
539 {
540 bus_addr_t addr2;
541
542 addr2 = sb_match_bit_lane_addr(addr, 4);
543 writel(addr2, val);
544 }
545 #endif /* _BIG_ENDIAN */
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