io.h

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    1 enum {
    2         IrqCLOCK        = 0,
    3         IrqKBD          = 1,
    4         IrqUART1        = 3,
    5         IrqUART0        = 4,
    6         IrqPCMCIA       = 5,
    7         IrqFLOPPY       = 6,
    8         IrqLPT          = 7,
    9         IrqIRQ7         = 7,
   10         IrqAUX          = 12,           /* PS/2 port */
   11         IrqIRQ13        = 13,           /* coprocessor on 386 */
   12         IrqATA0         = 14,
   13         IrqATA1         = 15,
   14         MaxIrqPIC       = 15,
   15 
   16         VectorPIC       = 32,
   17         MaxVectorPIC    = VectorPIC+MaxIrqPIC,
   18 };
   19 
   20 typedef struct Vctl {
   21         Vctl*   next;                   /* handlers on this vector */
   22 
   23         char    name[KNAMELEN]; /* of driver */
   24         int     isintr;                 /* interrupt or fault/trap */
   25         int     irq;
   26         int     tbdf;
   27         int     (*isr)(int);            /* get isr bit for this irq */
   28         int     (*eoi)(int);            /* eoi */
   29 
   30         void    (*f)(Ureg*, void*);     /* handler to call */
   31         void*   a;                      /* argument to call it with */
   32 } Vctl;
   33 
   34 enum {
   35         BusCBUS         = 0,            /* Corollary CBUS */
   36         BusCBUSII,                      /* Corollary CBUS II */
   37         BusEISA,                        /* Extended ISA */
   38         BusFUTURE,                      /* IEEE Futurebus */
   39         BusINTERN,                      /* Internal bus */
   40         BusISA,                         /* Industry Standard Architecture */
   41         BusMBI,                         /* Multibus I */
   42         BusMBII,                        /* Multibus II */
   43         BusMCA,                         /* Micro Channel Architecture */
   44         BusMPI,                         /* MPI */
   45         BusMPSA,                        /* MPSA */
   46         BusNUBUS,                       /* Apple Macintosh NuBus */
   47         BusPCI,                         /* Peripheral Component Interconnect */
   48         BusPCMCIA,                      /* PC Memory Card International Association */
   49         BusTC,                          /* DEC TurboChannel */
   50         BusVL,                          /* VESA Local bus */
   51         BusVME,                         /* VMEbus */
   52         BusXPRESS,                      /* Express System Bus */
   53 };
   54 
   55 #define MKBUS(t,b,d,f)  (((t)<<24)|(((b)&0xFF)<<16)|(((d)&0x1F)<<11)|(((f)&0x07)<<8))
   56 #define BUSFNO(tbdf)    (((tbdf)>>8)&0x07)
   57 #define BUSDNO(tbdf)    (((tbdf)>>11)&0x1F)
   58 #define BUSBNO(tbdf)    (((tbdf)>>16)&0xFF)
   59 #define BUSTYPE(tbdf)   ((tbdf)>>24)
   60 #define BUSDF(tbdf)             ((tbdf)&0x000FF00)
   61 #define BUSBDF(tbdf)    ((tbdf)&0x0FFFF00)
   62 #define BUSUNKNOWN      (-1)
   63 
   64 enum {
   65         MaxEISA         = 16,
   66         EISAconfig      = 0xC80,
   67 };
   68 
   69 /*
   70  * PCI support code.
   71  */
   72 enum {                                  /* type 0 and type 1 pre-defined header */
   73         PciVID          = 0x00,         /* vendor ID */
   74         PciDID          = 0x02,         /* device ID */
   75         PciPCR          = 0x04,         /* command */
   76         PciPSR          = 0x06,         /* status */
   77         PciRID          = 0x08,         /* revision ID */
   78         PciCCRp         = 0x09,         /* programming interface class code */
   79         PciCCRu         = 0x0A,         /* sub-class code */
   80         PciCCRb         = 0x0B,         /* base class code */
   81         PciCLS          = 0x0C,         /* cache line size */
   82         PciLTR          = 0x0D,         /* latency timer */
   83         PciHDT          = 0x0E,         /* header type */
   84         PciBST          = 0x0F,         /* BIST */
   85 
   86         PciBAR0         = 0x10,         /* base address */
   87         PciBAR1         = 0x14,
   88 
   89         PciINTL         = 0x3C,         /* interrupt line */
   90         PciINTP         = 0x3D,         /* interrupt pin */
   91 };
   92 
   93 enum {                                  /* type 0 pre-defined header */
   94         PciCIS          = 0x28,         /* cardbus CIS pointer */
   95         PciSVID         = 0x2C,         /* subsystem vendor ID */
   96         PciSID          = 0x2E,         /* cardbus CIS pointer */
   97         PciEBAR0        = 0x30,         /* expansion ROM base address */
   98         PciMGNT         = 0x3E,         /* burst period length */
   99         PciMLT          = 0x3F,         /* maximum latency between bursts */
  100 };
  101 
  102 enum {                                  /* type 1 pre-defined header */
  103         PciPBN          = 0x18,         /* primary bus number */
  104         PciSBN          = 0x19,         /* secondary bus number */
  105         PciUBN          = 0x1A,         /* subordinate bus number */
  106         PciSLTR         = 0x1B,         /* secondary latency timer */
  107         PciIBR          = 0x1C,         /* I/O base */
  108         PciILR          = 0x1D,         /* I/O limit */
  109         PciSPSR         = 0x1E,         /* secondary status */
  110         PciMBR          = 0x20,         /* memory base */
  111         PciMLR          = 0x22,         /* memory limit */
  112         PciPMBR         = 0x24,         /* prefetchable memory base */
  113         PciPMLR         = 0x26,         /* prefetchable memory limit */
  114         PciPUBR         = 0x28,         /* prefetchable base upper 32 bits */
  115         PciPULR         = 0x2C,         /* prefetchable limit upper 32 bits */
  116         PciIUBR         = 0x30,         /* I/O base upper 16 bits */
  117         PciIULR         = 0x32,         /* I/O limit upper 16 bits */
  118         PciEBAR1        = 0x28,         /* expansion ROM base address */
  119         PciBCR          = 0x3E,         /* bridge control register */
  120 };
  121 
  122 enum {                                  /* type 2 pre-defined header */
  123         PciCBExCA       = 0x10,
  124         PciCBSPSR       = 0x16,
  125         PciCBPBN        = 0x18,         /* primary bus number */
  126         PciCBSBN        = 0x19,         /* secondary bus number */
  127         PciCBUBN        = 0x1A,         /* subordinate bus number */
  128         PciCBSLTR       = 0x1B,         /* secondary latency timer */
  129         PciCBMBR0       = 0x1C,
  130         PciCBMLR0       = 0x20,
  131         PciCBMBR1       = 0x24,
  132         PciCBMLR1       = 0x28,
  133         PciCBIBR0       = 0x2C,         /* I/O base */
  134         PciCBILR0       = 0x30,         /* I/O limit */
  135         PciCBIBR1       = 0x34,         /* I/O base */
  136         PciCBILR1       = 0x38,         /* I/O limit */
  137         PciCBSVID       = 0x40,         /* subsystem vendor ID */
  138         PciCBSID        = 0x42,         /* subsystem ID */
  139         PciCBLMBAR      = 0x44,         /* legacy mode base address */
  140 };
  141 
  142 typedef struct Pcisiz Pcisiz;
  143 struct Pcisiz
  144 {
  145         Pcidev* dev;
  146         int     siz;
  147         int     bar;
  148 };
  149 
  150 typedef struct Pcidev Pcidev;
  151 typedef struct Pcidev {
  152         int     tbdf;                   /* type+bus+device+function */
  153         ushort  vid;                    /* vendor ID */
  154         ushort  did;                    /* device ID */
  155 
  156         uchar   rid;
  157         uchar   ccrp;
  158         uchar   ccru;
  159         uchar   ccrb;
  160 
  161         struct {
  162                 ulong   bar;            /* base address */
  163                 int     size;
  164         } mem[6];
  165 
  166         uchar   intl;                   /* interrupt line */
  167 
  168         Pcidev* list;
  169         Pcidev* link;                   /* next device on this bno */
  170 
  171         Pcidev* bridge;                 /* down a bus */
  172         struct {
  173                 ulong   bar;
  174                 int     size;
  175         } ioa, mema;
  176         ulong   pcr;
  177 };
  178 
  179 #define PCIWINDOW       0x80000000
  180 #define PCIWADDR(va)    (PADDR(va)+PCIWINDOW)

Cache object: b4090ac3dce8fcdd8914d43786514233

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FreeBSD/Linux Kernel Cross Reference sys/mtx/io.h

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sys/mtx/io.h