The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


[ source navigation ] [ diff markup ] [ identifier search ] [ freetext search ] [ file search ] [ list types ] [ track identifier ]

FreeBSD/Linux Kernel Cross Reference
sys/mtx/mem.h

Version: -  FREEBSD  -  FREEBSD-12-STABLE  -  FREEBSD-12-0  -  FREEBSD-11-STABLE  -  FREEBSD-11-2  -  FREEBSD-11-1  -  FREEBSD-11-0  -  FREEBSD-10-STABLE  -  FREEBSD-10-4  -  FREEBSD-10-3  -  FREEBSD-10-2  -  FREEBSD-10-1  -  FREEBSD-10-0  -  FREEBSD-9-STABLE  -  FREEBSD-9-3  -  FREEBSD-9-2  -  FREEBSD-9-1  -  FREEBSD-9-0  -  FREEBSD-8-STABLE  -  FREEBSD-8-4  -  FREEBSD-8-3  -  FREEBSD-8-2  -  FREEBSD-8-1  -  FREEBSD-8-0  -  FREEBSD-7-STABLE  -  FREEBSD-7-4  -  FREEBSD-7-3  -  FREEBSD-7-2  -  FREEBSD-7-1  -  FREEBSD-7-0  -  FREEBSD-6-STABLE  -  FREEBSD-6-4  -  FREEBSD-6-3  -  FREEBSD-6-2  -  FREEBSD-6-1  -  FREEBSD-6-0  -  FREEBSD-5-STABLE  -  FREEBSD-5-5  -  FREEBSD-5-4  -  FREEBSD-5-3  -  FREEBSD-5-2  -  FREEBSD-5-1  -  FREEBSD-5-0  -  FREEBSD-4-STABLE  -  FREEBSD-3-STABLE  -  FREEBSD22  -  linux-2.6  -  linux-2.4.22  -  MK83  -  MK84  -  PLAN9  -  DFBSD  -  NETBSD  -  NETBSD5  -  NETBSD4  -  NETBSD3  -  NETBSD20  -  OPENBSD  -  xnu-517  -  xnu-792  -  xnu-792.6.70  -  xnu-1228  -  xnu-1456.1.26  -  xnu-1699.24.8  -  xnu-2050.18.24  -  OPENSOLARIS  -  minix-3-1-1 
SearchContext: -  none  -  3  -  10 

    1 /*
    2  * Memory and machine-specific definitions.  Used in C and assembler.
    3  */
    4 
    5 /*
    6  * Sizes
    7  */
    8 
    9 #define BI2BY           8                       /* bits per byte */
   10 #define BI2WD           32                      /* bits per word */
   11 #define BY2WD           4                       /* bytes per word */
   12 #define         BY2V            8                       /* bytes per vlong */
   13 #define BY2PG           4096            /* bytes per page */
   14 #define WD2PG           (BY2PG/BY2WD)   /* words per page */
   15 #define PGSHIFT         12                      /* log(BY2PG) */
   16 #define         ROUND(s, sz)    (((s)+(sz-1))&~(sz-1))
   17 #define         PGROUND(s)      ROUND(s, BY2PG)
   18 #define CACHELINELOG    4
   19 #define CACHELINESZ     (1<<CACHELINELOG)
   20 #define BLOCKALIGN      CACHELINESZ
   21 
   22 #define MHz     1000000
   23 
   24 #define BY2PTE          8                               /* bytes per pte entry */
   25 #define BY2PTEG         64                              /* bytes per pte group */
   26 
   27 #define MAXMACH 1                               /* max # cpus system can run */
   28 #define MACHSIZE        BY2PG
   29 #define KSTACK          4096                    /* Size of kernel stack */
   30 
   31 /*
   32  * Time
   33  */
   34 #define HZ              100                     /* clock frequency */
   35 #define TK2SEC(t)       ((t)/HZ)                /* ticks to seconds */
   36 
   37 /*
   38  * Standard PPC Special Purpose Registers (OEA and VEA)
   39  */
   40 #define DSISR   18
   41 #define DAR     19              /* Data Address Register */
   42 #define DEC     22              /* Decrementer */
   43 #define SDR1    25
   44 #define SRR0    26              /* Saved Registers (exception) */
   45 #define SRR1    27
   46 #define SPRG0   272             /* Supervisor Private Registers */
   47 #define SPRG1   273
   48 #define SPRG2   274
   49 #define SPRG3   275
   50 #define ASR     280             /* Address Space Register */
   51 #define EAR     282             /* External Access Register (optional) */
   52 #define TBRU    269             /* Time base Upper/Lower (Reading) */
   53 #define TBRL    268
   54 #define TBWU    284             /* Time base Upper/Lower (Writing) */
   55 #define TBWL    285
   56 #define PVR     287             /* Processor Version */
   57 #define IABR    1010    /* Instruction Address Breakpoint Register (optional) */
   58 #define DABR    1013    /* Data Address Breakpoint Register (optional) */
   59 #define FPECR   1022    /* Floating-Point Exception Cause Register (optional) */
   60 #define PIR     1023    /* Processor Identification Register (optional) */
   61 
   62 #define IBATU(i)        (528+2*(i))     /* Instruction BAT register (upper) */
   63 #define IBATL(i)        (529+2*(i))     /* Instruction BAT register (lower) */
   64 #define DBATU(i)        (536+2*(i))     /* Data BAT register (upper) */
   65 #define DBATL(i)        (537+2*(i))     /* Data BAT register (lower) */
   66 
   67 /*
   68  * PPC604e-specific Special Purpose Registers (OEA)
   69  */
   70 #define HID0            1008    /* Hardware Implementation Dependant Register 0 */
   71 #define HID1            1009    /* Hardware Implementation Dependant Register 1 */
   72 #define PMC1            953             /* Performance Monitor Counter 1 */
   73 #define PMC2            954             /* Performance Monitor Counter 2 */
   74 #define PMC3            957             /* Performance Monitor Counter 3 */
   75 #define PMC4            958             /* Performance Monitor Counter 4 */
   76 #define MMCR0   952             /* Monitor Control Register 0 */
   77 #define MMCR1   956             /* Monitor Control Register 0 */
   78 #define SIA             955             /* Sampled Instruction Address */
   79 #define SDA             959             /* Sampled Data Address */
   80 
   81 #define BIT(i)  (1<<(31-(i)))   /* Silly backwards register bit numbering scheme */
   82 
   83 /*
   84  * Bit encodings for Machine State Register (MSR)
   85  */
   86 #define MSR_POW         BIT(13)         /* Enable Power Management */
   87 #define MSR_ILE         BIT(15)         /* Interrupt Little-Endian enable */
   88 #define MSR_EE          BIT(16)         /* External Interrupt enable */
   89 #define MSR_PR          BIT(17)         /* Supervisor/User privelege */
   90 #define MSR_FP          BIT(18)         /* Floating Point enable */
   91 #define MSR_ME          BIT(19)         /* Machine Check enable */
   92 #define MSR_FE0         BIT(20)         /* Floating Exception mode 0 */
   93 #define MSR_SE          BIT(21)         /* Single Step (optional) */
   94 #define MSR_BE          BIT(22)         /* Branch Trace (optional) */
   95 #define MSR_FE1         BIT(23)         /* Floating Exception mode 1 */
   96 #define MSR_IP          BIT(25)         /* Exception prefix 0x000/0xFFF */
   97 #define MSR_IR          BIT(26)         /* Instruction MMU enable */
   98 #define MSR_DR          BIT(27)         /* Data MMU enable */
   99 #define MSR_PM          BIT(29)         /* Performance Monitor marked mode (604e specific) */
  100 #define MSR_RI          BIT(30)         /* Recoverable Exception */
  101 #define MSR_LE          BIT(31)         /* Little-Endian enable */
  102 
  103 /*
  104  * Exception codes (trap vectors)
  105  */
  106 #define CRESET  0x01
  107 #define CMCHECK 0x02
  108 #define CDSI            0x03
  109 #define CISI            0x04
  110 #define CEI             0x05
  111 #define CALIGN  0x06
  112 #define CPROG           0x07
  113 #define CFPU            0x08
  114 #define CDEC            0x09
  115 #define CSYSCALL        0x0C
  116 #define CTRACE  0x0D    /* optional */
  117 #define CFPA            0x0E            /* optional */
  118 
  119 /* PPC604e-specific: */
  120 #define CPERF           0x0F            /* performance monitoring */
  121 #define CIBREAK 0x13
  122 #define CSMI            0x14
  123 
  124 /*
  125  * Magic registers
  126  */
  127 
  128 #define MACH    30              /* R30 is m-> */
  129 #define USER            29              /* R29 is up-> */
  130 
  131 
  132 /*
  133  *  virtual MMU
  134  */
  135 #define PTEMAPMEM       (1024*1024)     
  136 #define PTEPERTAB       (PTEMAPMEM/BY2PG)
  137 #define SEGMAPSIZE      1984
  138 #define SSEGMAPSIZE     16
  139 #define PPN(x)          ((x)&~(BY2PG-1))
  140 
  141 /*
  142  *  First pte word
  143  */
  144 #define PTE0(v, vsid, h, va)    (((v)<<31)|((vsid)<<7)|((h)<<6)|(((va)>>22)&0x3f))
  145 
  146 /*
  147  *  Second pte word; WIMG & PP(RW/RO) common to page table and BATs
  148  */
  149 #define PTE1_W  BIT(25)
  150 #define PTE1_I  BIT(26)
  151 #define PTE1_M  BIT(27)
  152 #define PTE1_G  BIT(28)
  153 
  154 #define PTE1_RW BIT(30)
  155 #define PTE1_RO BIT(31)
  156 
  157 /*
  158  *  PTE bits for fault.c.  These belong to the second PTE word.  Validity is
  159  *  implied for putmmu(), and we always set PTE0_V.  PTEVALID is used
  160  *  here to set cache policy bits on a global basis.
  161  */
  162 #define PTEVALID                0
  163 #define PTEWRITE                PTE1_RW
  164 #define PTERONLY        PTE1_RO
  165 #define PTEUNCACHED     PTE1_I
  166 
  167 /*
  168  * Address spaces
  169  */
  170 
  171 #define UZERO   0                       /* base of user address space */
  172 #define UTZERO  (UZERO+BY2PG)           /* first address in user text */
  173 #define USTKTOP (TSTKTOP-TSTKSIZ*BY2PG) /* byte just beyond user stack */
  174 #define TSTKTOP KZERO   /* top of temporary stack */
  175 #define TSTKSIZ 100
  176 #define KZERO   0x80000000              /* base of kernel address space */
  177 #define KTZERO  (KZERO+0x4000)  /* first address in kernel text */
  178 #define USTKSIZE        (4*1024*1024)           /* size of user stack */
  179 #define UREGSIZE        ((8+32)*4)
  180 
  181 #define PCIMEM0         0xf0000000
  182 #define PCISIZE0                0x0e000000
  183 #define PCIMEM1         0xc0000000
  184 #define PCISIZE1                0x30000000
  185 #define IOMEM           0xfe000000
  186 #define IOSIZE          0x00800000
  187 #define FALCON          0xfef80000
  188 #define RAVEN           0xfeff0000
  189 #define FLASHA          0xff000000
  190 #define FLASHB          0xff800000
  191 #define FLASHAorB       0xfff00000
  192 
  193 #define isphys(x) (((ulong)x&KZERO)!=0)
  194 
  195 #define getpgcolor(a)   0

Cache object: 83904c75728c0aafaa4db23c8e4328b1


[ source navigation ] [ diff markup ] [ identifier search ] [ freetext search ] [ file search ] [ list types ] [ track identifier ]


This page is part of the FreeBSD/Linux Linux Kernel Cross-Reference, and was automatically generated using a modified version of the LXR engine.