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FreeBSD/Linux Kernel Cross Reference
sys/net/iflib.c
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1 /*- 2 * Copyright (c) 2014-2018, Matthew Macy <mmacy@mattmacy.io> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright notice, 9 * this list of conditions and the following disclaimer. 10 * 11 * 2. Neither the name of Matthew Macy nor the names of its 12 * contributors may be used to endorse or promote products derived from 13 * this software without specific prior written permission. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 __FBSDID("$FreeBSD: releng/12.0/sys/net/iflib.c 340735 2018-11-21 17:33:19Z shurd $"); 30 31 #include "opt_inet.h" 32 #include "opt_inet6.h" 33 #include "opt_acpi.h" 34 #include "opt_sched.h" 35 36 #include <sys/param.h> 37 #include <sys/types.h> 38 #include <sys/bus.h> 39 #include <sys/eventhandler.h> 40 #include <sys/jail.h> 41 #include <sys/kernel.h> 42 #include <sys/lock.h> 43 #include <sys/md5.h> 44 #include <sys/mutex.h> 45 #include <sys/module.h> 46 #include <sys/kobj.h> 47 #include <sys/rman.h> 48 #include <sys/proc.h> 49 #include <sys/sbuf.h> 50 #include <sys/smp.h> 51 #include <sys/socket.h> 52 #include <sys/sockio.h> 53 #include <sys/sysctl.h> 54 #include <sys/syslog.h> 55 #include <sys/taskqueue.h> 56 #include <sys/limits.h> 57 58 #include <net/if.h> 59 #include <net/if_var.h> 60 #include <net/if_types.h> 61 #include <net/if_media.h> 62 #include <net/bpf.h> 63 #include <net/ethernet.h> 64 #include <net/mp_ring.h> 65 #include <net/vnet.h> 66 67 #include <netinet/in.h> 68 #include <netinet/in_pcb.h> 69 #include <netinet/tcp_lro.h> 70 #include <netinet/in_systm.h> 71 #include <netinet/if_ether.h> 72 #include <netinet/ip.h> 73 #include <netinet/ip6.h> 74 #include <netinet/tcp.h> 75 #include <netinet/ip_var.h> 76 #include <netinet/netdump/netdump.h> 77 #include <netinet6/ip6_var.h> 78 79 #include <machine/bus.h> 80 #include <machine/in_cksum.h> 81 82 #include <vm/vm.h> 83 #include <vm/pmap.h> 84 85 #include <dev/led/led.h> 86 #include <dev/pci/pcireg.h> 87 #include <dev/pci/pcivar.h> 88 #include <dev/pci/pci_private.h> 89 90 #include <net/iflib.h> 91 #include <net/iflib_private.h> 92 93 #include "ifdi_if.h" 94 95 #if defined(__i386__) || defined(__amd64__) 96 #include <sys/memdesc.h> 97 #include <machine/bus.h> 98 #include <machine/md_var.h> 99 #include <machine/specialreg.h> 100 #include <x86/include/busdma_impl.h> 101 #include <x86/iommu/busdma_dmar.h> 102 #endif 103 104 #ifdef PCI_IOV 105 #include <dev/pci/pci_iov.h> 106 #endif 107 108 #include <sys/bitstring.h> 109 /* 110 * enable accounting of every mbuf as it comes in to and goes out of 111 * iflib's software descriptor references 112 */ 113 #define MEMORY_LOGGING 0 114 /* 115 * Enable mbuf vectors for compressing long mbuf chains 116 */ 117 118 /* 119 * NB: 120 * - Prefetching in tx cleaning should perhaps be a tunable. The distance ahead 121 * we prefetch needs to be determined by the time spent in m_free vis a vis 122 * the cost of a prefetch. This will of course vary based on the workload: 123 * - NFLX's m_free path is dominated by vm-based M_EXT manipulation which 124 * is quite expensive, thus suggesting very little prefetch. 125 * - small packet forwarding which is just returning a single mbuf to 126 * UMA will typically be very fast vis a vis the cost of a memory 127 * access. 128 */ 129 130 131 /* 132 * File organization: 133 * - private structures 134 * - iflib private utility functions 135 * - ifnet functions 136 * - vlan registry and other exported functions 137 * - iflib public core functions 138 * 139 * 140 */ 141 MALLOC_DEFINE(M_IFLIB, "iflib", "ifnet library"); 142 143 struct iflib_txq; 144 typedef struct iflib_txq *iflib_txq_t; 145 struct iflib_rxq; 146 typedef struct iflib_rxq *iflib_rxq_t; 147 struct iflib_fl; 148 typedef struct iflib_fl *iflib_fl_t; 149 150 struct iflib_ctx; 151 152 static void iru_init(if_rxd_update_t iru, iflib_rxq_t rxq, uint8_t flid); 153 static void iflib_timer(void *arg); 154 155 typedef struct iflib_filter_info { 156 driver_filter_t *ifi_filter; 157 void *ifi_filter_arg; 158 struct grouptask *ifi_task; 159 void *ifi_ctx; 160 } *iflib_filter_info_t; 161 162 struct iflib_ctx { 163 KOBJ_FIELDS; 164 /* 165 * Pointer to hardware driver's softc 166 */ 167 void *ifc_softc; 168 device_t ifc_dev; 169 if_t ifc_ifp; 170 171 cpuset_t ifc_cpus; 172 if_shared_ctx_t ifc_sctx; 173 struct if_softc_ctx ifc_softc_ctx; 174 175 struct sx ifc_ctx_sx; 176 struct mtx ifc_state_mtx; 177 178 iflib_txq_t ifc_txqs; 179 iflib_rxq_t ifc_rxqs; 180 uint32_t ifc_if_flags; 181 uint32_t ifc_flags; 182 uint32_t ifc_max_fl_buf_size; 183 184 int ifc_link_state; 185 int ifc_link_irq; 186 int ifc_watchdog_events; 187 struct cdev *ifc_led_dev; 188 struct resource *ifc_msix_mem; 189 190 struct if_irq ifc_legacy_irq; 191 struct grouptask ifc_admin_task; 192 struct grouptask ifc_vflr_task; 193 struct iflib_filter_info ifc_filter_info; 194 struct ifmedia ifc_media; 195 196 struct sysctl_oid *ifc_sysctl_node; 197 uint16_t ifc_sysctl_ntxqs; 198 uint16_t ifc_sysctl_nrxqs; 199 uint16_t ifc_sysctl_qs_eq_override; 200 uint16_t ifc_sysctl_rx_budget; 201 uint16_t ifc_sysctl_tx_abdicate; 202 203 qidx_t ifc_sysctl_ntxds[8]; 204 qidx_t ifc_sysctl_nrxds[8]; 205 struct if_txrx ifc_txrx; 206 #define isc_txd_encap ifc_txrx.ift_txd_encap 207 #define isc_txd_flush ifc_txrx.ift_txd_flush 208 #define isc_txd_credits_update ifc_txrx.ift_txd_credits_update 209 #define isc_rxd_available ifc_txrx.ift_rxd_available 210 #define isc_rxd_pkt_get ifc_txrx.ift_rxd_pkt_get 211 #define isc_rxd_refill ifc_txrx.ift_rxd_refill 212 #define isc_rxd_flush ifc_txrx.ift_rxd_flush 213 #define isc_rxd_refill ifc_txrx.ift_rxd_refill 214 #define isc_rxd_refill ifc_txrx.ift_rxd_refill 215 #define isc_legacy_intr ifc_txrx.ift_legacy_intr 216 eventhandler_tag ifc_vlan_attach_event; 217 eventhandler_tag ifc_vlan_detach_event; 218 uint8_t ifc_mac[ETHER_ADDR_LEN]; 219 char ifc_mtx_name[16]; 220 }; 221 222 223 void * 224 iflib_get_softc(if_ctx_t ctx) 225 { 226 227 return (ctx->ifc_softc); 228 } 229 230 device_t 231 iflib_get_dev(if_ctx_t ctx) 232 { 233 234 return (ctx->ifc_dev); 235 } 236 237 if_t 238 iflib_get_ifp(if_ctx_t ctx) 239 { 240 241 return (ctx->ifc_ifp); 242 } 243 244 struct ifmedia * 245 iflib_get_media(if_ctx_t ctx) 246 { 247 248 return (&ctx->ifc_media); 249 } 250 251 uint32_t 252 iflib_get_flags(if_ctx_t ctx) 253 { 254 return (ctx->ifc_flags); 255 } 256 257 void 258 iflib_set_mac(if_ctx_t ctx, uint8_t mac[ETHER_ADDR_LEN]) 259 { 260 261 bcopy(mac, ctx->ifc_mac, ETHER_ADDR_LEN); 262 } 263 264 if_softc_ctx_t 265 iflib_get_softc_ctx(if_ctx_t ctx) 266 { 267 268 return (&ctx->ifc_softc_ctx); 269 } 270 271 if_shared_ctx_t 272 iflib_get_sctx(if_ctx_t ctx) 273 { 274 275 return (ctx->ifc_sctx); 276 } 277 278 #define IP_ALIGNED(m) ((((uintptr_t)(m)->m_data) & 0x3) == 0x2) 279 #define CACHE_PTR_INCREMENT (CACHE_LINE_SIZE/sizeof(void*)) 280 #define CACHE_PTR_NEXT(ptr) ((void *)(((uintptr_t)(ptr)+CACHE_LINE_SIZE-1) & (CACHE_LINE_SIZE-1))) 281 282 #define LINK_ACTIVE(ctx) ((ctx)->ifc_link_state == LINK_STATE_UP) 283 #define CTX_IS_VF(ctx) ((ctx)->ifc_sctx->isc_flags & IFLIB_IS_VF) 284 285 #define RX_SW_DESC_MAP_CREATED (1 << 0) 286 #define TX_SW_DESC_MAP_CREATED (1 << 1) 287 #define RX_SW_DESC_INUSE (1 << 3) 288 #define TX_SW_DESC_MAPPED (1 << 4) 289 290 #define M_TOOBIG M_PROTO1 291 292 typedef struct iflib_sw_rx_desc_array { 293 bus_dmamap_t *ifsd_map; /* bus_dma maps for packet */ 294 struct mbuf **ifsd_m; /* pkthdr mbufs */ 295 caddr_t *ifsd_cl; /* direct cluster pointer for rx */ 296 uint8_t *ifsd_flags; 297 } iflib_rxsd_array_t; 298 299 typedef struct iflib_sw_tx_desc_array { 300 bus_dmamap_t *ifsd_map; /* bus_dma maps for packet */ 301 struct mbuf **ifsd_m; /* pkthdr mbufs */ 302 uint8_t *ifsd_flags; 303 } if_txsd_vec_t; 304 305 306 /* magic number that should be high enough for any hardware */ 307 #define IFLIB_MAX_TX_SEGS 128 308 /* bnxt supports 64 with hardware LRO enabled */ 309 #define IFLIB_MAX_RX_SEGS 64 310 #define IFLIB_RX_COPY_THRESH 128 311 #define IFLIB_MAX_RX_REFRESH 32 312 /* The minimum descriptors per second before we start coalescing */ 313 #define IFLIB_MIN_DESC_SEC 16384 314 #define IFLIB_DEFAULT_TX_UPDATE_FREQ 16 315 #define IFLIB_QUEUE_IDLE 0 316 #define IFLIB_QUEUE_HUNG 1 317 #define IFLIB_QUEUE_WORKING 2 318 /* maximum number of txqs that can share an rx interrupt */ 319 #define IFLIB_MAX_TX_SHARED_INTR 4 320 321 /* this should really scale with ring size - this is a fairly arbitrary value */ 322 #define TX_BATCH_SIZE 32 323 324 #define IFLIB_RESTART_BUDGET 8 325 326 327 #define CSUM_OFFLOAD (CSUM_IP_TSO|CSUM_IP6_TSO|CSUM_IP| \ 328 CSUM_IP_UDP|CSUM_IP_TCP|CSUM_IP_SCTP| \ 329 CSUM_IP6_UDP|CSUM_IP6_TCP|CSUM_IP6_SCTP) 330 struct iflib_txq { 331 qidx_t ift_in_use; 332 qidx_t ift_cidx; 333 qidx_t ift_cidx_processed; 334 qidx_t ift_pidx; 335 uint8_t ift_gen; 336 uint8_t ift_br_offset; 337 uint16_t ift_npending; 338 uint16_t ift_db_pending; 339 uint16_t ift_rs_pending; 340 /* implicit pad */ 341 uint8_t ift_txd_size[8]; 342 uint64_t ift_processed; 343 uint64_t ift_cleaned; 344 uint64_t ift_cleaned_prev; 345 #if MEMORY_LOGGING 346 uint64_t ift_enqueued; 347 uint64_t ift_dequeued; 348 #endif 349 uint64_t ift_no_tx_dma_setup; 350 uint64_t ift_no_desc_avail; 351 uint64_t ift_mbuf_defrag_failed; 352 uint64_t ift_mbuf_defrag; 353 uint64_t ift_map_failed; 354 uint64_t ift_txd_encap_efbig; 355 uint64_t ift_pullups; 356 uint64_t ift_last_timer_tick; 357 358 struct mtx ift_mtx; 359 struct mtx ift_db_mtx; 360 361 /* constant values */ 362 if_ctx_t ift_ctx; 363 struct ifmp_ring *ift_br; 364 struct grouptask ift_task; 365 qidx_t ift_size; 366 uint16_t ift_id; 367 struct callout ift_timer; 368 369 if_txsd_vec_t ift_sds; 370 uint8_t ift_qstatus; 371 uint8_t ift_closed; 372 uint8_t ift_update_freq; 373 struct iflib_filter_info ift_filter_info; 374 bus_dma_tag_t ift_desc_tag; 375 bus_dma_tag_t ift_tso_desc_tag; 376 iflib_dma_info_t ift_ifdi; 377 #define MTX_NAME_LEN 16 378 char ift_mtx_name[MTX_NAME_LEN]; 379 char ift_db_mtx_name[MTX_NAME_LEN]; 380 bus_dma_segment_t ift_segs[IFLIB_MAX_TX_SEGS] __aligned(CACHE_LINE_SIZE); 381 #ifdef IFLIB_DIAGNOSTICS 382 uint64_t ift_cpu_exec_count[256]; 383 #endif 384 } __aligned(CACHE_LINE_SIZE); 385 386 struct iflib_fl { 387 qidx_t ifl_cidx; 388 qidx_t ifl_pidx; 389 qidx_t ifl_credits; 390 uint8_t ifl_gen; 391 uint8_t ifl_rxd_size; 392 #if MEMORY_LOGGING 393 uint64_t ifl_m_enqueued; 394 uint64_t ifl_m_dequeued; 395 uint64_t ifl_cl_enqueued; 396 uint64_t ifl_cl_dequeued; 397 #endif 398 /* implicit pad */ 399 400 bitstr_t *ifl_rx_bitmap; 401 qidx_t ifl_fragidx; 402 /* constant */ 403 qidx_t ifl_size; 404 uint16_t ifl_buf_size; 405 uint16_t ifl_cltype; 406 uma_zone_t ifl_zone; 407 iflib_rxsd_array_t ifl_sds; 408 iflib_rxq_t ifl_rxq; 409 uint8_t ifl_id; 410 bus_dma_tag_t ifl_desc_tag; 411 iflib_dma_info_t ifl_ifdi; 412 uint64_t ifl_bus_addrs[IFLIB_MAX_RX_REFRESH] __aligned(CACHE_LINE_SIZE); 413 caddr_t ifl_vm_addrs[IFLIB_MAX_RX_REFRESH]; 414 qidx_t ifl_rxd_idxs[IFLIB_MAX_RX_REFRESH]; 415 } __aligned(CACHE_LINE_SIZE); 416 417 static inline qidx_t 418 get_inuse(int size, qidx_t cidx, qidx_t pidx, uint8_t gen) 419 { 420 qidx_t used; 421 422 if (pidx > cidx) 423 used = pidx - cidx; 424 else if (pidx < cidx) 425 used = size - cidx + pidx; 426 else if (gen == 0 && pidx == cidx) 427 used = 0; 428 else if (gen == 1 && pidx == cidx) 429 used = size; 430 else 431 panic("bad state"); 432 433 return (used); 434 } 435 436 #define TXQ_AVAIL(txq) (txq->ift_size - get_inuse(txq->ift_size, txq->ift_cidx, txq->ift_pidx, txq->ift_gen)) 437 438 #define IDXDIFF(head, tail, wrap) \ 439 ((head) >= (tail) ? (head) - (tail) : (wrap) - (tail) + (head)) 440 441 struct iflib_rxq { 442 /* If there is a separate completion queue - 443 * these are the cq cidx and pidx. Otherwise 444 * these are unused. 445 */ 446 qidx_t ifr_size; 447 qidx_t ifr_cq_cidx; 448 qidx_t ifr_cq_pidx; 449 uint8_t ifr_cq_gen; 450 uint8_t ifr_fl_offset; 451 452 if_ctx_t ifr_ctx; 453 iflib_fl_t ifr_fl; 454 uint64_t ifr_rx_irq; 455 uint16_t ifr_id; 456 uint8_t ifr_lro_enabled; 457 uint8_t ifr_nfl; 458 uint8_t ifr_ntxqirq; 459 uint8_t ifr_txqid[IFLIB_MAX_TX_SHARED_INTR]; 460 struct lro_ctrl ifr_lc; 461 struct grouptask ifr_task; 462 struct iflib_filter_info ifr_filter_info; 463 iflib_dma_info_t ifr_ifdi; 464 465 /* dynamically allocate if any drivers need a value substantially larger than this */ 466 struct if_rxd_frag ifr_frags[IFLIB_MAX_RX_SEGS] __aligned(CACHE_LINE_SIZE); 467 #ifdef IFLIB_DIAGNOSTICS 468 uint64_t ifr_cpu_exec_count[256]; 469 #endif 470 } __aligned(CACHE_LINE_SIZE); 471 472 typedef struct if_rxsd { 473 caddr_t *ifsd_cl; 474 struct mbuf **ifsd_m; 475 iflib_fl_t ifsd_fl; 476 qidx_t ifsd_cidx; 477 } *if_rxsd_t; 478 479 /* multiple of word size */ 480 #ifdef __LP64__ 481 #define PKT_INFO_SIZE 6 482 #define RXD_INFO_SIZE 5 483 #define PKT_TYPE uint64_t 484 #else 485 #define PKT_INFO_SIZE 11 486 #define RXD_INFO_SIZE 8 487 #define PKT_TYPE uint32_t 488 #endif 489 #define PKT_LOOP_BOUND ((PKT_INFO_SIZE/3)*3) 490 #define RXD_LOOP_BOUND ((RXD_INFO_SIZE/4)*4) 491 492 typedef struct if_pkt_info_pad { 493 PKT_TYPE pkt_val[PKT_INFO_SIZE]; 494 } *if_pkt_info_pad_t; 495 typedef struct if_rxd_info_pad { 496 PKT_TYPE rxd_val[RXD_INFO_SIZE]; 497 } *if_rxd_info_pad_t; 498 499 CTASSERT(sizeof(struct if_pkt_info_pad) == sizeof(struct if_pkt_info)); 500 CTASSERT(sizeof(struct if_rxd_info_pad) == sizeof(struct if_rxd_info)); 501 502 503 static inline void 504 pkt_info_zero(if_pkt_info_t pi) 505 { 506 if_pkt_info_pad_t pi_pad; 507 508 pi_pad = (if_pkt_info_pad_t)pi; 509 pi_pad->pkt_val[0] = 0; pi_pad->pkt_val[1] = 0; pi_pad->pkt_val[2] = 0; 510 pi_pad->pkt_val[3] = 0; pi_pad->pkt_val[4] = 0; pi_pad->pkt_val[5] = 0; 511 #ifndef __LP64__ 512 pi_pad->pkt_val[6] = 0; pi_pad->pkt_val[7] = 0; pi_pad->pkt_val[8] = 0; 513 pi_pad->pkt_val[9] = 0; pi_pad->pkt_val[10] = 0; 514 #endif 515 } 516 517 static device_method_t iflib_pseudo_methods[] = { 518 DEVMETHOD(device_attach, noop_attach), 519 DEVMETHOD(device_detach, iflib_pseudo_detach), 520 DEVMETHOD_END 521 }; 522 523 driver_t iflib_pseudodriver = { 524 "iflib_pseudo", iflib_pseudo_methods, sizeof(struct iflib_ctx), 525 }; 526 527 static inline void 528 rxd_info_zero(if_rxd_info_t ri) 529 { 530 if_rxd_info_pad_t ri_pad; 531 int i; 532 533 ri_pad = (if_rxd_info_pad_t)ri; 534 for (i = 0; i < RXD_LOOP_BOUND; i += 4) { 535 ri_pad->rxd_val[i] = 0; 536 ri_pad->rxd_val[i+1] = 0; 537 ri_pad->rxd_val[i+2] = 0; 538 ri_pad->rxd_val[i+3] = 0; 539 } 540 #ifdef __LP64__ 541 ri_pad->rxd_val[RXD_INFO_SIZE-1] = 0; 542 #endif 543 } 544 545 /* 546 * Only allow a single packet to take up most 1/nth of the tx ring 547 */ 548 #define MAX_SINGLE_PACKET_FRACTION 12 549 #define IF_BAD_DMA (bus_addr_t)-1 550 551 #define CTX_ACTIVE(ctx) ((if_getdrvflags((ctx)->ifc_ifp) & IFF_DRV_RUNNING)) 552 553 #define CTX_LOCK_INIT(_sc) sx_init(&(_sc)->ifc_ctx_sx, "iflib ctx lock") 554 #define CTX_LOCK(ctx) sx_xlock(&(ctx)->ifc_ctx_sx) 555 #define CTX_UNLOCK(ctx) sx_xunlock(&(ctx)->ifc_ctx_sx) 556 #define CTX_LOCK_DESTROY(ctx) sx_destroy(&(ctx)->ifc_ctx_sx) 557 558 559 #define STATE_LOCK_INIT(_sc, _name) mtx_init(&(_sc)->ifc_state_mtx, _name, "iflib state lock", MTX_DEF) 560 #define STATE_LOCK(ctx) mtx_lock(&(ctx)->ifc_state_mtx) 561 #define STATE_UNLOCK(ctx) mtx_unlock(&(ctx)->ifc_state_mtx) 562 #define STATE_LOCK_DESTROY(ctx) mtx_destroy(&(ctx)->ifc_state_mtx) 563 564 565 566 #define CALLOUT_LOCK(txq) mtx_lock(&txq->ift_mtx) 567 #define CALLOUT_UNLOCK(txq) mtx_unlock(&txq->ift_mtx) 568 569 void 570 iflib_set_detach(if_ctx_t ctx) 571 { 572 STATE_LOCK(ctx); 573 ctx->ifc_flags |= IFC_IN_DETACH; 574 STATE_UNLOCK(ctx); 575 } 576 577 /* Our boot-time initialization hook */ 578 static int iflib_module_event_handler(module_t, int, void *); 579 580 static moduledata_t iflib_moduledata = { 581 "iflib", 582 iflib_module_event_handler, 583 NULL 584 }; 585 586 DECLARE_MODULE(iflib, iflib_moduledata, SI_SUB_INIT_IF, SI_ORDER_ANY); 587 MODULE_VERSION(iflib, 1); 588 589 MODULE_DEPEND(iflib, pci, 1, 1, 1); 590 MODULE_DEPEND(iflib, ether, 1, 1, 1); 591 592 TASKQGROUP_DEFINE(if_io_tqg, mp_ncpus, 1); 593 TASKQGROUP_DEFINE(if_config_tqg, 1, 1); 594 595 #ifndef IFLIB_DEBUG_COUNTERS 596 #ifdef INVARIANTS 597 #define IFLIB_DEBUG_COUNTERS 1 598 #else 599 #define IFLIB_DEBUG_COUNTERS 0 600 #endif /* !INVARIANTS */ 601 #endif 602 603 static SYSCTL_NODE(_net, OID_AUTO, iflib, CTLFLAG_RD, 0, 604 "iflib driver parameters"); 605 606 /* 607 * XXX need to ensure that this can't accidentally cause the head to be moved backwards 608 */ 609 static int iflib_min_tx_latency = 0; 610 SYSCTL_INT(_net_iflib, OID_AUTO, min_tx_latency, CTLFLAG_RW, 611 &iflib_min_tx_latency, 0, "minimize transmit latency at the possible expense of throughput"); 612 static int iflib_no_tx_batch = 0; 613 SYSCTL_INT(_net_iflib, OID_AUTO, no_tx_batch, CTLFLAG_RW, 614 &iflib_no_tx_batch, 0, "minimize transmit latency at the possible expense of throughput"); 615 616 617 #if IFLIB_DEBUG_COUNTERS 618 619 static int iflib_tx_seen; 620 static int iflib_tx_sent; 621 static int iflib_tx_encap; 622 static int iflib_rx_allocs; 623 static int iflib_fl_refills; 624 static int iflib_fl_refills_large; 625 static int iflib_tx_frees; 626 627 SYSCTL_INT(_net_iflib, OID_AUTO, tx_seen, CTLFLAG_RD, 628 &iflib_tx_seen, 0, "# tx mbufs seen"); 629 SYSCTL_INT(_net_iflib, OID_AUTO, tx_sent, CTLFLAG_RD, 630 &iflib_tx_sent, 0, "# tx mbufs sent"); 631 SYSCTL_INT(_net_iflib, OID_AUTO, tx_encap, CTLFLAG_RD, 632 &iflib_tx_encap, 0, "# tx mbufs encapped"); 633 SYSCTL_INT(_net_iflib, OID_AUTO, tx_frees, CTLFLAG_RD, 634 &iflib_tx_frees, 0, "# tx frees"); 635 SYSCTL_INT(_net_iflib, OID_AUTO, rx_allocs, CTLFLAG_RD, 636 &iflib_rx_allocs, 0, "# rx allocations"); 637 SYSCTL_INT(_net_iflib, OID_AUTO, fl_refills, CTLFLAG_RD, 638 &iflib_fl_refills, 0, "# refills"); 639 SYSCTL_INT(_net_iflib, OID_AUTO, fl_refills_large, CTLFLAG_RD, 640 &iflib_fl_refills_large, 0, "# large refills"); 641 642 643 static int iflib_txq_drain_flushing; 644 static int iflib_txq_drain_oactive; 645 static int iflib_txq_drain_notready; 646 647 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_flushing, CTLFLAG_RD, 648 &iflib_txq_drain_flushing, 0, "# drain flushes"); 649 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_oactive, CTLFLAG_RD, 650 &iflib_txq_drain_oactive, 0, "# drain oactives"); 651 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_notready, CTLFLAG_RD, 652 &iflib_txq_drain_notready, 0, "# drain notready"); 653 654 655 static int iflib_encap_load_mbuf_fail; 656 static int iflib_encap_pad_mbuf_fail; 657 static int iflib_encap_txq_avail_fail; 658 static int iflib_encap_txd_encap_fail; 659 660 SYSCTL_INT(_net_iflib, OID_AUTO, encap_load_mbuf_fail, CTLFLAG_RD, 661 &iflib_encap_load_mbuf_fail, 0, "# busdma load failures"); 662 SYSCTL_INT(_net_iflib, OID_AUTO, encap_pad_mbuf_fail, CTLFLAG_RD, 663 &iflib_encap_pad_mbuf_fail, 0, "# runt frame pad failures"); 664 SYSCTL_INT(_net_iflib, OID_AUTO, encap_txq_avail_fail, CTLFLAG_RD, 665 &iflib_encap_txq_avail_fail, 0, "# txq avail failures"); 666 SYSCTL_INT(_net_iflib, OID_AUTO, encap_txd_encap_fail, CTLFLAG_RD, 667 &iflib_encap_txd_encap_fail, 0, "# driver encap failures"); 668 669 static int iflib_task_fn_rxs; 670 static int iflib_rx_intr_enables; 671 static int iflib_fast_intrs; 672 static int iflib_rx_unavail; 673 static int iflib_rx_ctx_inactive; 674 static int iflib_rx_if_input; 675 static int iflib_rx_mbuf_null; 676 static int iflib_rxd_flush; 677 678 static int iflib_verbose_debug; 679 680 SYSCTL_INT(_net_iflib, OID_AUTO, task_fn_rx, CTLFLAG_RD, 681 &iflib_task_fn_rxs, 0, "# task_fn_rx calls"); 682 SYSCTL_INT(_net_iflib, OID_AUTO, rx_intr_enables, CTLFLAG_RD, 683 &iflib_rx_intr_enables, 0, "# rx intr enables"); 684 SYSCTL_INT(_net_iflib, OID_AUTO, fast_intrs, CTLFLAG_RD, 685 &iflib_fast_intrs, 0, "# fast_intr calls"); 686 SYSCTL_INT(_net_iflib, OID_AUTO, rx_unavail, CTLFLAG_RD, 687 &iflib_rx_unavail, 0, "# times rxeof called with no available data"); 688 SYSCTL_INT(_net_iflib, OID_AUTO, rx_ctx_inactive, CTLFLAG_RD, 689 &iflib_rx_ctx_inactive, 0, "# times rxeof called with inactive context"); 690 SYSCTL_INT(_net_iflib, OID_AUTO, rx_if_input, CTLFLAG_RD, 691 &iflib_rx_if_input, 0, "# times rxeof called if_input"); 692 SYSCTL_INT(_net_iflib, OID_AUTO, rx_mbuf_null, CTLFLAG_RD, 693 &iflib_rx_mbuf_null, 0, "# times rxeof got null mbuf"); 694 SYSCTL_INT(_net_iflib, OID_AUTO, rxd_flush, CTLFLAG_RD, 695 &iflib_rxd_flush, 0, "# times rxd_flush called"); 696 SYSCTL_INT(_net_iflib, OID_AUTO, verbose_debug, CTLFLAG_RW, 697 &iflib_verbose_debug, 0, "enable verbose debugging"); 698 699 #define DBG_COUNTER_INC(name) atomic_add_int(&(iflib_ ## name), 1) 700 static void 701 iflib_debug_reset(void) 702 { 703 iflib_tx_seen = iflib_tx_sent = iflib_tx_encap = iflib_rx_allocs = 704 iflib_fl_refills = iflib_fl_refills_large = iflib_tx_frees = 705 iflib_txq_drain_flushing = iflib_txq_drain_oactive = 706 iflib_txq_drain_notready = 707 iflib_encap_load_mbuf_fail = iflib_encap_pad_mbuf_fail = 708 iflib_encap_txq_avail_fail = iflib_encap_txd_encap_fail = 709 iflib_task_fn_rxs = iflib_rx_intr_enables = iflib_fast_intrs = 710 iflib_rx_unavail = 711 iflib_rx_ctx_inactive = iflib_rx_if_input = 712 iflib_rx_mbuf_null = iflib_rxd_flush = 0; 713 } 714 715 #else 716 #define DBG_COUNTER_INC(name) 717 static void iflib_debug_reset(void) {} 718 #endif 719 720 #define IFLIB_DEBUG 0 721 722 static void iflib_tx_structures_free(if_ctx_t ctx); 723 static void iflib_rx_structures_free(if_ctx_t ctx); 724 static int iflib_queues_alloc(if_ctx_t ctx); 725 static int iflib_tx_credits_update(if_ctx_t ctx, iflib_txq_t txq); 726 static int iflib_rxd_avail(if_ctx_t ctx, iflib_rxq_t rxq, qidx_t cidx, qidx_t budget); 727 static int iflib_qset_structures_setup(if_ctx_t ctx); 728 static int iflib_msix_init(if_ctx_t ctx); 729 static int iflib_legacy_setup(if_ctx_t ctx, driver_filter_t filter, void *filterarg, int *rid, const char *str); 730 static void iflib_txq_check_drain(iflib_txq_t txq, int budget); 731 static uint32_t iflib_txq_can_drain(struct ifmp_ring *); 732 #ifdef ALTQ 733 static void iflib_altq_if_start(if_t ifp); 734 static int iflib_altq_if_transmit(if_t ifp, struct mbuf *m); 735 #endif 736 static int iflib_register(if_ctx_t); 737 static void iflib_init_locked(if_ctx_t ctx); 738 static void iflib_add_device_sysctl_pre(if_ctx_t ctx); 739 static void iflib_add_device_sysctl_post(if_ctx_t ctx); 740 static void iflib_ifmp_purge(iflib_txq_t txq); 741 static void _iflib_pre_assert(if_softc_ctx_t scctx); 742 static void iflib_if_init_locked(if_ctx_t ctx); 743 static void iflib_free_intr_mem(if_ctx_t ctx); 744 #ifndef __NO_STRICT_ALIGNMENT 745 static struct mbuf * iflib_fixup_rx(struct mbuf *m); 746 #endif 747 748 NETDUMP_DEFINE(iflib); 749 750 #ifdef DEV_NETMAP 751 #include <sys/selinfo.h> 752 #include <net/netmap.h> 753 #include <dev/netmap/netmap_kern.h> 754 755 MODULE_DEPEND(iflib, netmap, 1, 1, 1); 756 757 static int netmap_fl_refill(iflib_rxq_t rxq, struct netmap_kring *kring, uint32_t nm_i, bool init); 758 759 /* 760 * device-specific sysctl variables: 761 * 762 * iflib_crcstrip: 0: keep CRC in rx frames (default), 1: strip it. 763 * During regular operations the CRC is stripped, but on some 764 * hardware reception of frames not multiple of 64 is slower, 765 * so using crcstrip=0 helps in benchmarks. 766 * 767 * iflib_rx_miss, iflib_rx_miss_bufs: 768 * count packets that might be missed due to lost interrupts. 769 */ 770 SYSCTL_DECL(_dev_netmap); 771 /* 772 * The xl driver by default strips CRCs and we do not override it. 773 */ 774 775 int iflib_crcstrip = 1; 776 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_crcstrip, 777 CTLFLAG_RW, &iflib_crcstrip, 1, "strip CRC on rx frames"); 778 779 int iflib_rx_miss, iflib_rx_miss_bufs; 780 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_rx_miss, 781 CTLFLAG_RW, &iflib_rx_miss, 0, "potentially missed rx intr"); 782 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_rx_miss_bufs, 783 CTLFLAG_RW, &iflib_rx_miss_bufs, 0, "potentially missed rx intr bufs"); 784 785 /* 786 * Register/unregister. We are already under netmap lock. 787 * Only called on the first register or the last unregister. 788 */ 789 static int 790 iflib_netmap_register(struct netmap_adapter *na, int onoff) 791 { 792 struct ifnet *ifp = na->ifp; 793 if_ctx_t ctx = ifp->if_softc; 794 int status; 795 796 CTX_LOCK(ctx); 797 IFDI_INTR_DISABLE(ctx); 798 799 /* Tell the stack that the interface is no longer active */ 800 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 801 802 if (!CTX_IS_VF(ctx)) 803 IFDI_CRCSTRIP_SET(ctx, onoff, iflib_crcstrip); 804 805 /* enable or disable flags and callbacks in na and ifp */ 806 if (onoff) { 807 nm_set_native_flags(na); 808 } else { 809 nm_clear_native_flags(na); 810 } 811 iflib_stop(ctx); 812 iflib_init_locked(ctx); 813 IFDI_CRCSTRIP_SET(ctx, onoff, iflib_crcstrip); // XXX why twice ? 814 status = ifp->if_drv_flags & IFF_DRV_RUNNING ? 0 : 1; 815 if (status) 816 nm_clear_native_flags(na); 817 CTX_UNLOCK(ctx); 818 return (status); 819 } 820 821 static int 822 netmap_fl_refill(iflib_rxq_t rxq, struct netmap_kring *kring, uint32_t nm_i, bool init) 823 { 824 struct netmap_adapter *na = kring->na; 825 u_int const lim = kring->nkr_num_slots - 1; 826 u_int head = kring->rhead; 827 struct netmap_ring *ring = kring->ring; 828 bus_dmamap_t *map; 829 struct if_rxd_update iru; 830 if_ctx_t ctx = rxq->ifr_ctx; 831 iflib_fl_t fl = &rxq->ifr_fl[0]; 832 uint32_t refill_pidx, nic_i; 833 #if IFLIB_DEBUG_COUNTERS 834 int rf_count = 0; 835 #endif 836 837 if (nm_i == head && __predict_true(!init)) 838 return 0; 839 iru_init(&iru, rxq, 0 /* flid */); 840 map = fl->ifl_sds.ifsd_map; 841 refill_pidx = netmap_idx_k2n(kring, nm_i); 842 /* 843 * IMPORTANT: we must leave one free slot in the ring, 844 * so move head back by one unit 845 */ 846 head = nm_prev(head, lim); 847 nic_i = UINT_MAX; 848 DBG_COUNTER_INC(fl_refills); 849 while (nm_i != head) { 850 #if IFLIB_DEBUG_COUNTERS 851 if (++rf_count == 9) 852 DBG_COUNTER_INC(fl_refills_large); 853 #endif 854 for (int tmp_pidx = 0; tmp_pidx < IFLIB_MAX_RX_REFRESH && nm_i != head; tmp_pidx++) { 855 struct netmap_slot *slot = &ring->slot[nm_i]; 856 void *addr = PNMB(na, slot, &fl->ifl_bus_addrs[tmp_pidx]); 857 uint32_t nic_i_dma = refill_pidx; 858 nic_i = netmap_idx_k2n(kring, nm_i); 859 860 MPASS(tmp_pidx < IFLIB_MAX_RX_REFRESH); 861 862 if (addr == NETMAP_BUF_BASE(na)) /* bad buf */ 863 return netmap_ring_reinit(kring); 864 865 fl->ifl_vm_addrs[tmp_pidx] = addr; 866 if (__predict_false(init) && map) { 867 netmap_load_map(na, fl->ifl_ifdi->idi_tag, map[nic_i], addr); 868 } else if (map && (slot->flags & NS_BUF_CHANGED)) { 869 /* buffer has changed, reload map */ 870 netmap_reload_map(na, fl->ifl_ifdi->idi_tag, map[nic_i], addr); 871 } 872 slot->flags &= ~NS_BUF_CHANGED; 873 874 nm_i = nm_next(nm_i, lim); 875 fl->ifl_rxd_idxs[tmp_pidx] = nic_i = nm_next(nic_i, lim); 876 if (nm_i != head && tmp_pidx < IFLIB_MAX_RX_REFRESH-1) 877 continue; 878 879 iru.iru_pidx = refill_pidx; 880 iru.iru_count = tmp_pidx+1; 881 ctx->isc_rxd_refill(ctx->ifc_softc, &iru); 882 883 refill_pidx = nic_i; 884 if (map == NULL) 885 continue; 886 887 for (int n = 0; n < iru.iru_count; n++) { 888 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, map[nic_i_dma], 889 BUS_DMASYNC_PREREAD); 890 /* XXX - change this to not use the netmap func*/ 891 nic_i_dma = nm_next(nic_i_dma, lim); 892 } 893 } 894 } 895 kring->nr_hwcur = head; 896 897 if (map) 898 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 899 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 900 if (__predict_true(nic_i != UINT_MAX)) { 901 ctx->isc_rxd_flush(ctx->ifc_softc, rxq->ifr_id, fl->ifl_id, nic_i); 902 DBG_COUNTER_INC(rxd_flush); 903 } 904 return (0); 905 } 906 907 /* 908 * Reconcile kernel and user view of the transmit ring. 909 * 910 * All information is in the kring. 911 * Userspace wants to send packets up to the one before kring->rhead, 912 * kernel knows kring->nr_hwcur is the first unsent packet. 913 * 914 * Here we push packets out (as many as possible), and possibly 915 * reclaim buffers from previously completed transmission. 916 * 917 * The caller (netmap) guarantees that there is only one instance 918 * running at any time. Any interference with other driver 919 * methods should be handled by the individual drivers. 920 */ 921 static int 922 iflib_netmap_txsync(struct netmap_kring *kring, int flags) 923 { 924 struct netmap_adapter *na = kring->na; 925 struct ifnet *ifp = na->ifp; 926 struct netmap_ring *ring = kring->ring; 927 u_int nm_i; /* index into the netmap kring */ 928 u_int nic_i; /* index into the NIC ring */ 929 u_int n; 930 u_int const lim = kring->nkr_num_slots - 1; 931 u_int const head = kring->rhead; 932 struct if_pkt_info pi; 933 934 /* 935 * interrupts on every tx packet are expensive so request 936 * them every half ring, or where NS_REPORT is set 937 */ 938 u_int report_frequency = kring->nkr_num_slots >> 1; 939 /* device-specific */ 940 if_ctx_t ctx = ifp->if_softc; 941 iflib_txq_t txq = &ctx->ifc_txqs[kring->ring_id]; 942 943 if (txq->ift_sds.ifsd_map) 944 bus_dmamap_sync(txq->ift_desc_tag, txq->ift_ifdi->idi_map, 945 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 946 947 948 /* 949 * First part: process new packets to send. 950 * nm_i is the current index in the netmap kring, 951 * nic_i is the corresponding index in the NIC ring. 952 * 953 * If we have packets to send (nm_i != head) 954 * iterate over the netmap ring, fetch length and update 955 * the corresponding slot in the NIC ring. Some drivers also 956 * need to update the buffer's physical address in the NIC slot 957 * even NS_BUF_CHANGED is not set (PNMB computes the addresses). 958 * 959 * The netmap_reload_map() calls is especially expensive, 960 * even when (as in this case) the tag is 0, so do only 961 * when the buffer has actually changed. 962 * 963 * If possible do not set the report/intr bit on all slots, 964 * but only a few times per ring or when NS_REPORT is set. 965 * 966 * Finally, on 10G and faster drivers, it might be useful 967 * to prefetch the next slot and txr entry. 968 */ 969 970 nm_i = kring->nr_hwcur; 971 if (nm_i != head) { /* we have new packets to send */ 972 pkt_info_zero(&pi); 973 pi.ipi_segs = txq->ift_segs; 974 pi.ipi_qsidx = kring->ring_id; 975 nic_i = netmap_idx_k2n(kring, nm_i); 976 977 __builtin_prefetch(&ring->slot[nm_i]); 978 __builtin_prefetch(&txq->ift_sds.ifsd_m[nic_i]); 979 if (txq->ift_sds.ifsd_map) 980 __builtin_prefetch(&txq->ift_sds.ifsd_map[nic_i]); 981 982 for (n = 0; nm_i != head; n++) { 983 struct netmap_slot *slot = &ring->slot[nm_i]; 984 u_int len = slot->len; 985 uint64_t paddr; 986 void *addr = PNMB(na, slot, &paddr); 987 int flags = (slot->flags & NS_REPORT || 988 nic_i == 0 || nic_i == report_frequency) ? 989 IPI_TX_INTR : 0; 990 991 /* device-specific */ 992 pi.ipi_len = len; 993 pi.ipi_segs[0].ds_addr = paddr; 994 pi.ipi_segs[0].ds_len = len; 995 pi.ipi_nsegs = 1; 996 pi.ipi_ndescs = 0; 997 pi.ipi_pidx = nic_i; 998 pi.ipi_flags = flags; 999 1000 /* Fill the slot in the NIC ring. */ 1001 ctx->isc_txd_encap(ctx->ifc_softc, &pi); 1002 DBG_COUNTER_INC(tx_encap); 1003 1004 /* prefetch for next round */ 1005 __builtin_prefetch(&ring->slot[nm_i + 1]); 1006 __builtin_prefetch(&txq->ift_sds.ifsd_m[nic_i + 1]); 1007 if (txq->ift_sds.ifsd_map) { 1008 __builtin_prefetch(&txq->ift_sds.ifsd_map[nic_i + 1]); 1009 1010 NM_CHECK_ADDR_LEN(na, addr, len); 1011 1012 if (slot->flags & NS_BUF_CHANGED) { 1013 /* buffer has changed, reload map */ 1014 netmap_reload_map(na, txq->ift_desc_tag, txq->ift_sds.ifsd_map[nic_i], addr); 1015 } 1016 /* make sure changes to the buffer are synced */ 1017 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_sds.ifsd_map[nic_i], 1018 BUS_DMASYNC_PREWRITE); 1019 } 1020 slot->flags &= ~(NS_REPORT | NS_BUF_CHANGED); 1021 nm_i = nm_next(nm_i, lim); 1022 nic_i = nm_next(nic_i, lim); 1023 } 1024 kring->nr_hwcur = nm_i; 1025 1026 /* synchronize the NIC ring */ 1027 if (txq->ift_sds.ifsd_map) 1028 bus_dmamap_sync(txq->ift_desc_tag, txq->ift_ifdi->idi_map, 1029 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1030 1031 /* (re)start the tx unit up to slot nic_i (excluded) */ 1032 ctx->isc_txd_flush(ctx->ifc_softc, txq->ift_id, nic_i); 1033 } 1034 1035 /* 1036 * Second part: reclaim buffers for completed transmissions. 1037 * 1038 * If there are unclaimed buffers, attempt to reclaim them. 1039 * If none are reclaimed, and TX IRQs are not in use, do an initial 1040 * minimal delay, then trigger the tx handler which will spin in the 1041 * group task queue. 1042 */ 1043 if (kring->nr_hwtail != nm_prev(kring->nr_hwcur, lim)) { 1044 if (iflib_tx_credits_update(ctx, txq)) { 1045 /* some tx completed, increment avail */ 1046 nic_i = txq->ift_cidx_processed; 1047 kring->nr_hwtail = nm_prev(netmap_idx_n2k(kring, nic_i), lim); 1048 } 1049 } 1050 if (!(ctx->ifc_flags & IFC_NETMAP_TX_IRQ)) 1051 if (kring->nr_hwtail != nm_prev(kring->nr_hwcur, lim)) { 1052 callout_reset_on(&txq->ift_timer, hz < 2000 ? 1 : hz / 1000, 1053 iflib_timer, txq, txq->ift_timer.c_cpu); 1054 } 1055 return (0); 1056 } 1057 1058 /* 1059 * Reconcile kernel and user view of the receive ring. 1060 * Same as for the txsync, this routine must be efficient. 1061 * The caller guarantees a single invocations, but races against 1062 * the rest of the driver should be handled here. 1063 * 1064 * On call, kring->rhead is the first packet that userspace wants 1065 * to keep, and kring->rcur is the wakeup point. 1066 * The kernel has previously reported packets up to kring->rtail. 1067 * 1068 * If (flags & NAF_FORCE_READ) also check for incoming packets irrespective 1069 * of whether or not we received an interrupt. 1070 */ 1071 static int 1072 iflib_netmap_rxsync(struct netmap_kring *kring, int flags) 1073 { 1074 struct netmap_adapter *na = kring->na; 1075 struct netmap_ring *ring = kring->ring; 1076 uint32_t nm_i; /* index into the netmap ring */ 1077 uint32_t nic_i; /* index into the NIC ring */ 1078 u_int i, n; 1079 u_int const lim = kring->nkr_num_slots - 1; 1080 u_int const head = kring->rhead; 1081 int force_update = (flags & NAF_FORCE_READ) || kring->nr_kflags & NKR_PENDINTR; 1082 struct if_rxd_info ri; 1083 1084 struct ifnet *ifp = na->ifp; 1085 if_ctx_t ctx = ifp->if_softc; 1086 iflib_rxq_t rxq = &ctx->ifc_rxqs[kring->ring_id]; 1087 iflib_fl_t fl = rxq->ifr_fl; 1088 if (head > lim) 1089 return netmap_ring_reinit(kring); 1090 1091 /* XXX check sync modes */ 1092 for (i = 0, fl = rxq->ifr_fl; i < rxq->ifr_nfl; i++, fl++) { 1093 if (fl->ifl_sds.ifsd_map == NULL) 1094 continue; 1095 bus_dmamap_sync(rxq->ifr_fl[i].ifl_desc_tag, fl->ifl_ifdi->idi_map, 1096 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1097 } 1098 /* 1099 * First part: import newly received packets. 1100 * 1101 * nm_i is the index of the next free slot in the netmap ring, 1102 * nic_i is the index of the next received packet in the NIC ring, 1103 * and they may differ in case if_init() has been called while 1104 * in netmap mode. For the receive ring we have 1105 * 1106 * nic_i = rxr->next_check; 1107 * nm_i = kring->nr_hwtail (previous) 1108 * and 1109 * nm_i == (nic_i + kring->nkr_hwofs) % ring_size 1110 * 1111 * rxr->next_check is set to 0 on a ring reinit 1112 */ 1113 if (netmap_no_pendintr || force_update) { 1114 int crclen = iflib_crcstrip ? 0 : 4; 1115 int error, avail; 1116 1117 for (i = 0; i < rxq->ifr_nfl; i++) { 1118 fl = &rxq->ifr_fl[i]; 1119 nic_i = fl->ifl_cidx; 1120 nm_i = netmap_idx_n2k(kring, nic_i); 1121 avail = iflib_rxd_avail(ctx, rxq, nic_i, USHRT_MAX); 1122 for (n = 0; avail > 0; n++, avail--) { 1123 rxd_info_zero(&ri); 1124 ri.iri_frags = rxq->ifr_frags; 1125 ri.iri_qsidx = kring->ring_id; 1126 ri.iri_ifp = ctx->ifc_ifp; 1127 ri.iri_cidx = nic_i; 1128 1129 error = ctx->isc_rxd_pkt_get(ctx->ifc_softc, &ri); 1130 ring->slot[nm_i].len = error ? 0 : ri.iri_len - crclen; 1131 ring->slot[nm_i].flags = 0; 1132 if (fl->ifl_sds.ifsd_map) 1133 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, 1134 fl->ifl_sds.ifsd_map[nic_i], BUS_DMASYNC_POSTREAD); 1135 nm_i = nm_next(nm_i, lim); 1136 nic_i = nm_next(nic_i, lim); 1137 } 1138 if (n) { /* update the state variables */ 1139 if (netmap_no_pendintr && !force_update) { 1140 /* diagnostics */ 1141 iflib_rx_miss ++; 1142 iflib_rx_miss_bufs += n; 1143 } 1144 fl->ifl_cidx = nic_i; 1145 kring->nr_hwtail = nm_i; 1146 } 1147 kring->nr_kflags &= ~NKR_PENDINTR; 1148 } 1149 } 1150 /* 1151 * Second part: skip past packets that userspace has released. 1152 * (kring->nr_hwcur to head excluded), 1153 * and make the buffers available for reception. 1154 * As usual nm_i is the index in the netmap ring, 1155 * nic_i is the index in the NIC ring, and 1156 * nm_i == (nic_i + kring->nkr_hwofs) % ring_size 1157 */ 1158 /* XXX not sure how this will work with multiple free lists */ 1159 nm_i = kring->nr_hwcur; 1160 1161 return (netmap_fl_refill(rxq, kring, nm_i, false)); 1162 } 1163 1164 static void 1165 iflib_netmap_intr(struct netmap_adapter *na, int onoff) 1166 { 1167 struct ifnet *ifp = na->ifp; 1168 if_ctx_t ctx = ifp->if_softc; 1169 1170 CTX_LOCK(ctx); 1171 if (onoff) { 1172 IFDI_INTR_ENABLE(ctx); 1173 } else { 1174 IFDI_INTR_DISABLE(ctx); 1175 } 1176 CTX_UNLOCK(ctx); 1177 } 1178 1179 1180 static int 1181 iflib_netmap_attach(if_ctx_t ctx) 1182 { 1183 struct netmap_adapter na; 1184 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1185 1186 bzero(&na, sizeof(na)); 1187 1188 na.ifp = ctx->ifc_ifp; 1189 na.na_flags = NAF_BDG_MAYSLEEP; 1190 MPASS(ctx->ifc_softc_ctx.isc_ntxqsets); 1191 MPASS(ctx->ifc_softc_ctx.isc_nrxqsets); 1192 1193 na.num_tx_desc = scctx->isc_ntxd[0]; 1194 na.num_rx_desc = scctx->isc_nrxd[0]; 1195 na.nm_txsync = iflib_netmap_txsync; 1196 na.nm_rxsync = iflib_netmap_rxsync; 1197 na.nm_register = iflib_netmap_register; 1198 na.nm_intr = iflib_netmap_intr; 1199 na.num_tx_rings = ctx->ifc_softc_ctx.isc_ntxqsets; 1200 na.num_rx_rings = ctx->ifc_softc_ctx.isc_nrxqsets; 1201 return (netmap_attach(&na)); 1202 } 1203 1204 static void 1205 iflib_netmap_txq_init(if_ctx_t ctx, iflib_txq_t txq) 1206 { 1207 struct netmap_adapter *na = NA(ctx->ifc_ifp); 1208 struct netmap_slot *slot; 1209 1210 slot = netmap_reset(na, NR_TX, txq->ift_id, 0); 1211 if (slot == NULL) 1212 return; 1213 if (txq->ift_sds.ifsd_map == NULL) 1214 return; 1215 1216 for (int i = 0; i < ctx->ifc_softc_ctx.isc_ntxd[0]; i++) { 1217 1218 /* 1219 * In netmap mode, set the map for the packet buffer. 1220 * NOTE: Some drivers (not this one) also need to set 1221 * the physical buffer address in the NIC ring. 1222 * netmap_idx_n2k() maps a nic index, i, into the corresponding 1223 * netmap slot index, si 1224 */ 1225 int si = netmap_idx_n2k(na->tx_rings[txq->ift_id], i); 1226 netmap_load_map(na, txq->ift_desc_tag, txq->ift_sds.ifsd_map[i], NMB(na, slot + si)); 1227 } 1228 } 1229 1230 static void 1231 iflib_netmap_rxq_init(if_ctx_t ctx, iflib_rxq_t rxq) 1232 { 1233 struct netmap_adapter *na = NA(ctx->ifc_ifp); 1234 struct netmap_kring *kring = na->rx_rings[rxq->ifr_id]; 1235 struct netmap_slot *slot; 1236 uint32_t nm_i; 1237 1238 slot = netmap_reset(na, NR_RX, rxq->ifr_id, 0); 1239 if (slot == NULL) 1240 return; 1241 nm_i = netmap_idx_n2k(kring, 0); 1242 netmap_fl_refill(rxq, kring, nm_i, true); 1243 } 1244 1245 static void 1246 iflib_netmap_timer_adjust(if_ctx_t ctx, uint16_t txqid, uint32_t *reset_on) 1247 { 1248 struct netmap_kring *kring; 1249 1250 kring = NA(ctx->ifc_ifp)->tx_rings[txqid]; 1251 1252 if (kring->nr_hwcur != nm_next(kring->nr_hwtail, kring->nkr_num_slots - 1)) { 1253 if (ctx->isc_txd_credits_update(ctx->ifc_softc, txqid, false)) 1254 netmap_tx_irq(ctx->ifc_ifp, txqid); 1255 if (!(ctx->ifc_flags & IFC_NETMAP_TX_IRQ)) { 1256 if (hz < 2000) 1257 *reset_on = 1; 1258 else 1259 *reset_on = hz / 1000; 1260 } 1261 } 1262 } 1263 1264 #define iflib_netmap_detach(ifp) netmap_detach(ifp) 1265 1266 #else 1267 #define iflib_netmap_txq_init(ctx, txq) 1268 #define iflib_netmap_rxq_init(ctx, rxq) 1269 #define iflib_netmap_detach(ifp) 1270 1271 #define iflib_netmap_attach(ctx) (0) 1272 #define netmap_rx_irq(ifp, qid, budget) (0) 1273 #define netmap_tx_irq(ifp, qid) do {} while (0) 1274 #define iflib_netmap_timer_adjust(ctx, txqid, reset_on) 1275 1276 #endif 1277 1278 #if defined(__i386__) || defined(__amd64__) 1279 static __inline void 1280 prefetch(void *x) 1281 { 1282 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x)); 1283 } 1284 static __inline void 1285 prefetch2cachelines(void *x) 1286 { 1287 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x)); 1288 #if (CACHE_LINE_SIZE < 128) 1289 __asm volatile("prefetcht0 %0" :: "m" (*(((unsigned long *)x)+CACHE_LINE_SIZE/(sizeof(unsigned long))))); 1290 #endif 1291 } 1292 #else 1293 #define prefetch(x) 1294 #define prefetch2cachelines(x) 1295 #endif 1296 1297 static void 1298 iflib_gen_mac(if_ctx_t ctx) 1299 { 1300 struct thread *td; 1301 MD5_CTX mdctx; 1302 char uuid[HOSTUUIDLEN+1]; 1303 char buf[HOSTUUIDLEN+16]; 1304 uint8_t *mac; 1305 unsigned char digest[16]; 1306 1307 td = curthread; 1308 mac = ctx->ifc_mac; 1309 uuid[HOSTUUIDLEN] = 0; 1310 bcopy(td->td_ucred->cr_prison->pr_hostuuid, uuid, HOSTUUIDLEN); 1311 snprintf(buf, HOSTUUIDLEN+16, "%s-%s", uuid, device_get_nameunit(ctx->ifc_dev)); 1312 /* 1313 * Generate a pseudo-random, deterministic MAC 1314 * address based on the UUID and unit number. 1315 * The FreeBSD Foundation OUI of 58-9C-FC is used. 1316 */ 1317 MD5Init(&mdctx); 1318 MD5Update(&mdctx, buf, strlen(buf)); 1319 MD5Final(digest, &mdctx); 1320 1321 mac[0] = 0x58; 1322 mac[1] = 0x9C; 1323 mac[2] = 0xFC; 1324 mac[3] = digest[0]; 1325 mac[4] = digest[1]; 1326 mac[5] = digest[2]; 1327 } 1328 1329 static void 1330 iru_init(if_rxd_update_t iru, iflib_rxq_t rxq, uint8_t flid) 1331 { 1332 iflib_fl_t fl; 1333 1334 fl = &rxq->ifr_fl[flid]; 1335 iru->iru_paddrs = fl->ifl_bus_addrs; 1336 iru->iru_vaddrs = &fl->ifl_vm_addrs[0]; 1337 iru->iru_idxs = fl->ifl_rxd_idxs; 1338 iru->iru_qsidx = rxq->ifr_id; 1339 iru->iru_buf_size = fl->ifl_buf_size; 1340 iru->iru_flidx = fl->ifl_id; 1341 } 1342 1343 static void 1344 _iflib_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int err) 1345 { 1346 if (err) 1347 return; 1348 *(bus_addr_t *) arg = segs[0].ds_addr; 1349 } 1350 1351 int 1352 iflib_dma_alloc(if_ctx_t ctx, int size, iflib_dma_info_t dma, int mapflags) 1353 { 1354 int err; 1355 if_shared_ctx_t sctx = ctx->ifc_sctx; 1356 device_t dev = ctx->ifc_dev; 1357 1358 KASSERT(sctx->isc_q_align != 0, ("alignment value not initialized")); 1359 1360 err = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */ 1361 sctx->isc_q_align, 0, /* alignment, bounds */ 1362 BUS_SPACE_MAXADDR, /* lowaddr */ 1363 BUS_SPACE_MAXADDR, /* highaddr */ 1364 NULL, NULL, /* filter, filterarg */ 1365 size, /* maxsize */ 1366 1, /* nsegments */ 1367 size, /* maxsegsize */ 1368 BUS_DMA_ALLOCNOW, /* flags */ 1369 NULL, /* lockfunc */ 1370 NULL, /* lockarg */ 1371 &dma->idi_tag); 1372 if (err) { 1373 device_printf(dev, 1374 "%s: bus_dma_tag_create failed: %d\n", 1375 __func__, err); 1376 goto fail_0; 1377 } 1378 1379 err = bus_dmamem_alloc(dma->idi_tag, (void**) &dma->idi_vaddr, 1380 BUS_DMA_NOWAIT | BUS_DMA_COHERENT | BUS_DMA_ZERO, &dma->idi_map); 1381 if (err) { 1382 device_printf(dev, 1383 "%s: bus_dmamem_alloc(%ju) failed: %d\n", 1384 __func__, (uintmax_t)size, err); 1385 goto fail_1; 1386 } 1387 1388 dma->idi_paddr = IF_BAD_DMA; 1389 err = bus_dmamap_load(dma->idi_tag, dma->idi_map, dma->idi_vaddr, 1390 size, _iflib_dmamap_cb, &dma->idi_paddr, mapflags | BUS_DMA_NOWAIT); 1391 if (err || dma->idi_paddr == IF_BAD_DMA) { 1392 device_printf(dev, 1393 "%s: bus_dmamap_load failed: %d\n", 1394 __func__, err); 1395 goto fail_2; 1396 } 1397 1398 dma->idi_size = size; 1399 return (0); 1400 1401 fail_2: 1402 bus_dmamem_free(dma->idi_tag, dma->idi_vaddr, dma->idi_map); 1403 fail_1: 1404 bus_dma_tag_destroy(dma->idi_tag); 1405 fail_0: 1406 dma->idi_tag = NULL; 1407 1408 return (err); 1409 } 1410 1411 int 1412 iflib_dma_alloc_multi(if_ctx_t ctx, int *sizes, iflib_dma_info_t *dmalist, int mapflags, int count) 1413 { 1414 int i, err; 1415 iflib_dma_info_t *dmaiter; 1416 1417 dmaiter = dmalist; 1418 for (i = 0; i < count; i++, dmaiter++) { 1419 if ((err = iflib_dma_alloc(ctx, sizes[i], *dmaiter, mapflags)) != 0) 1420 break; 1421 } 1422 if (err) 1423 iflib_dma_free_multi(dmalist, i); 1424 return (err); 1425 } 1426 1427 void 1428 iflib_dma_free(iflib_dma_info_t dma) 1429 { 1430 if (dma->idi_tag == NULL) 1431 return; 1432 if (dma->idi_paddr != IF_BAD_DMA) { 1433 bus_dmamap_sync(dma->idi_tag, dma->idi_map, 1434 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1435 bus_dmamap_unload(dma->idi_tag, dma->idi_map); 1436 dma->idi_paddr = IF_BAD_DMA; 1437 } 1438 if (dma->idi_vaddr != NULL) { 1439 bus_dmamem_free(dma->idi_tag, dma->idi_vaddr, dma->idi_map); 1440 dma->idi_vaddr = NULL; 1441 } 1442 bus_dma_tag_destroy(dma->idi_tag); 1443 dma->idi_tag = NULL; 1444 } 1445 1446 void 1447 iflib_dma_free_multi(iflib_dma_info_t *dmalist, int count) 1448 { 1449 int i; 1450 iflib_dma_info_t *dmaiter = dmalist; 1451 1452 for (i = 0; i < count; i++, dmaiter++) 1453 iflib_dma_free(*dmaiter); 1454 } 1455 1456 #ifdef EARLY_AP_STARTUP 1457 static const int iflib_started = 1; 1458 #else 1459 /* 1460 * We used to abuse the smp_started flag to decide if the queues have been 1461 * fully initialized (by late taskqgroup_adjust() calls in a SYSINIT()). 1462 * That gave bad races, since the SYSINIT() runs strictly after smp_started 1463 * is set. Run a SYSINIT() strictly after that to just set a usable 1464 * completion flag. 1465 */ 1466 1467 static int iflib_started; 1468 1469 static void 1470 iflib_record_started(void *arg) 1471 { 1472 iflib_started = 1; 1473 } 1474 1475 SYSINIT(iflib_record_started, SI_SUB_SMP + 1, SI_ORDER_FIRST, 1476 iflib_record_started, NULL); 1477 #endif 1478 1479 static int 1480 iflib_fast_intr(void *arg) 1481 { 1482 iflib_filter_info_t info = arg; 1483 struct grouptask *gtask = info->ifi_task; 1484 if (!iflib_started) 1485 return (FILTER_HANDLED); 1486 1487 DBG_COUNTER_INC(fast_intrs); 1488 if (info->ifi_filter != NULL && info->ifi_filter(info->ifi_filter_arg) == FILTER_HANDLED) 1489 return (FILTER_HANDLED); 1490 1491 GROUPTASK_ENQUEUE(gtask); 1492 return (FILTER_HANDLED); 1493 } 1494 1495 static int 1496 iflib_fast_intr_rxtx(void *arg) 1497 { 1498 iflib_filter_info_t info = arg; 1499 struct grouptask *gtask = info->ifi_task; 1500 iflib_rxq_t rxq = (iflib_rxq_t)info->ifi_ctx; 1501 if_ctx_t ctx = NULL;; 1502 int i, cidx; 1503 1504 if (!iflib_started) 1505 return (FILTER_HANDLED); 1506 1507 DBG_COUNTER_INC(fast_intrs); 1508 if (info->ifi_filter != NULL && info->ifi_filter(info->ifi_filter_arg) == FILTER_HANDLED) 1509 return (FILTER_HANDLED); 1510 1511 MPASS(rxq->ifr_ntxqirq); 1512 for (i = 0; i < rxq->ifr_ntxqirq; i++) { 1513 qidx_t txqid = rxq->ifr_txqid[i]; 1514 1515 ctx = rxq->ifr_ctx; 1516 1517 if (!ctx->isc_txd_credits_update(ctx->ifc_softc, txqid, false)) { 1518 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txqid); 1519 continue; 1520 } 1521 GROUPTASK_ENQUEUE(&ctx->ifc_txqs[txqid].ift_task); 1522 } 1523 if (ctx->ifc_sctx->isc_flags & IFLIB_HAS_RXCQ) 1524 cidx = rxq->ifr_cq_cidx; 1525 else 1526 cidx = rxq->ifr_fl[0].ifl_cidx; 1527 if (iflib_rxd_avail(ctx, rxq, cidx, 1)) 1528 GROUPTASK_ENQUEUE(gtask); 1529 else { 1530 IFDI_RX_QUEUE_INTR_ENABLE(ctx, rxq->ifr_id); 1531 DBG_COUNTER_INC(rx_intr_enables); 1532 } 1533 return (FILTER_HANDLED); 1534 } 1535 1536 1537 static int 1538 iflib_fast_intr_ctx(void *arg) 1539 { 1540 iflib_filter_info_t info = arg; 1541 struct grouptask *gtask = info->ifi_task; 1542 1543 if (!iflib_started) 1544 return (FILTER_HANDLED); 1545 1546 DBG_COUNTER_INC(fast_intrs); 1547 if (info->ifi_filter != NULL && info->ifi_filter(info->ifi_filter_arg) == FILTER_HANDLED) 1548 return (FILTER_HANDLED); 1549 1550 GROUPTASK_ENQUEUE(gtask); 1551 return (FILTER_HANDLED); 1552 } 1553 1554 static int 1555 _iflib_irq_alloc(if_ctx_t ctx, if_irq_t irq, int rid, 1556 driver_filter_t filter, driver_intr_t handler, void *arg, 1557 const char *name) 1558 { 1559 int rc, flags; 1560 struct resource *res; 1561 void *tag = NULL; 1562 device_t dev = ctx->ifc_dev; 1563 1564 flags = RF_ACTIVE; 1565 if (ctx->ifc_flags & IFC_LEGACY) 1566 flags |= RF_SHAREABLE; 1567 MPASS(rid < 512); 1568 irq->ii_rid = rid; 1569 res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &irq->ii_rid, flags); 1570 if (res == NULL) { 1571 device_printf(dev, 1572 "failed to allocate IRQ for rid %d, name %s.\n", rid, name); 1573 return (ENOMEM); 1574 } 1575 irq->ii_res = res; 1576 KASSERT(filter == NULL || handler == NULL, ("filter and handler can't both be non-NULL")); 1577 rc = bus_setup_intr(dev, res, INTR_MPSAFE | INTR_TYPE_NET, 1578 filter, handler, arg, &tag); 1579 if (rc != 0) { 1580 device_printf(dev, 1581 "failed to setup interrupt for rid %d, name %s: %d\n", 1582 rid, name ? name : "unknown", rc); 1583 return (rc); 1584 } else if (name) 1585 bus_describe_intr(dev, res, tag, "%s", name); 1586 1587 irq->ii_tag = tag; 1588 return (0); 1589 } 1590 1591 1592 /********************************************************************* 1593 * 1594 * Allocate memory for tx_buffer structures. The tx_buffer stores all 1595 * the information needed to transmit a packet on the wire. This is 1596 * called only once at attach, setup is done every reset. 1597 * 1598 **********************************************************************/ 1599 1600 static int 1601 iflib_txsd_alloc(iflib_txq_t txq) 1602 { 1603 if_ctx_t ctx = txq->ift_ctx; 1604 if_shared_ctx_t sctx = ctx->ifc_sctx; 1605 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1606 device_t dev = ctx->ifc_dev; 1607 bus_size_t tsomaxsize; 1608 int err, nsegments, ntsosegments; 1609 1610 nsegments = scctx->isc_tx_nsegments; 1611 ntsosegments = scctx->isc_tx_tso_segments_max; 1612 tsomaxsize = scctx->isc_tx_tso_size_max; 1613 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_VLAN_MTU) 1614 tsomaxsize += sizeof(struct ether_vlan_header); 1615 MPASS(scctx->isc_ntxd[0] > 0); 1616 MPASS(scctx->isc_ntxd[txq->ift_br_offset] > 0); 1617 MPASS(nsegments > 0); 1618 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_TSO) { 1619 MPASS(ntsosegments > 0); 1620 MPASS(sctx->isc_tso_maxsize >= tsomaxsize); 1621 } 1622 1623 /* 1624 * Setup DMA descriptor areas. 1625 */ 1626 if ((err = bus_dma_tag_create(bus_get_dma_tag(dev), 1627 1, 0, /* alignment, bounds */ 1628 BUS_SPACE_MAXADDR, /* lowaddr */ 1629 BUS_SPACE_MAXADDR, /* highaddr */ 1630 NULL, NULL, /* filter, filterarg */ 1631 sctx->isc_tx_maxsize, /* maxsize */ 1632 nsegments, /* nsegments */ 1633 sctx->isc_tx_maxsegsize, /* maxsegsize */ 1634 0, /* flags */ 1635 NULL, /* lockfunc */ 1636 NULL, /* lockfuncarg */ 1637 &txq->ift_desc_tag))) { 1638 device_printf(dev,"Unable to allocate TX DMA tag: %d\n", err); 1639 device_printf(dev,"maxsize: %ju nsegments: %d maxsegsize: %ju\n", 1640 (uintmax_t)sctx->isc_tx_maxsize, nsegments, (uintmax_t)sctx->isc_tx_maxsegsize); 1641 goto fail; 1642 } 1643 if ((if_getcapabilities(ctx->ifc_ifp) & IFCAP_TSO) & 1644 (err = bus_dma_tag_create(bus_get_dma_tag(dev), 1645 1, 0, /* alignment, bounds */ 1646 BUS_SPACE_MAXADDR, /* lowaddr */ 1647 BUS_SPACE_MAXADDR, /* highaddr */ 1648 NULL, NULL, /* filter, filterarg */ 1649 tsomaxsize, /* maxsize */ 1650 ntsosegments, /* nsegments */ 1651 sctx->isc_tso_maxsegsize,/* maxsegsize */ 1652 0, /* flags */ 1653 NULL, /* lockfunc */ 1654 NULL, /* lockfuncarg */ 1655 &txq->ift_tso_desc_tag))) { 1656 device_printf(dev,"Unable to allocate TX TSO DMA tag: %d\n", err); 1657 1658 goto fail; 1659 } 1660 if (!(txq->ift_sds.ifsd_flags = 1661 (uint8_t *) malloc(sizeof(uint8_t) * 1662 scctx->isc_ntxd[txq->ift_br_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1663 device_printf(dev, "Unable to allocate tx_buffer memory\n"); 1664 err = ENOMEM; 1665 goto fail; 1666 } 1667 if (!(txq->ift_sds.ifsd_m = 1668 (struct mbuf **) malloc(sizeof(struct mbuf *) * 1669 scctx->isc_ntxd[txq->ift_br_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1670 device_printf(dev, "Unable to allocate tx_buffer memory\n"); 1671 err = ENOMEM; 1672 goto fail; 1673 } 1674 1675 /* Create the descriptor buffer dma maps */ 1676 #if defined(ACPI_DMAR) || (! (defined(__i386__) || defined(__amd64__))) 1677 if ((ctx->ifc_flags & IFC_DMAR) == 0) 1678 return (0); 1679 1680 if (!(txq->ift_sds.ifsd_map = 1681 (bus_dmamap_t *) malloc(sizeof(bus_dmamap_t) * scctx->isc_ntxd[txq->ift_br_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1682 device_printf(dev, "Unable to allocate tx_buffer map memory\n"); 1683 err = ENOMEM; 1684 goto fail; 1685 } 1686 1687 for (int i = 0; i < scctx->isc_ntxd[txq->ift_br_offset]; i++) { 1688 err = bus_dmamap_create(txq->ift_desc_tag, 0, &txq->ift_sds.ifsd_map[i]); 1689 if (err != 0) { 1690 device_printf(dev, "Unable to create TX DMA map\n"); 1691 goto fail; 1692 } 1693 } 1694 #endif 1695 return (0); 1696 fail: 1697 /* We free all, it handles case where we are in the middle */ 1698 iflib_tx_structures_free(ctx); 1699 return (err); 1700 } 1701 1702 static void 1703 iflib_txsd_destroy(if_ctx_t ctx, iflib_txq_t txq, int i) 1704 { 1705 bus_dmamap_t map; 1706 1707 map = NULL; 1708 if (txq->ift_sds.ifsd_map != NULL) 1709 map = txq->ift_sds.ifsd_map[i]; 1710 if (map != NULL) { 1711 bus_dmamap_unload(txq->ift_desc_tag, map); 1712 bus_dmamap_destroy(txq->ift_desc_tag, map); 1713 txq->ift_sds.ifsd_map[i] = NULL; 1714 } 1715 } 1716 1717 static void 1718 iflib_txq_destroy(iflib_txq_t txq) 1719 { 1720 if_ctx_t ctx = txq->ift_ctx; 1721 1722 for (int i = 0; i < txq->ift_size; i++) 1723 iflib_txsd_destroy(ctx, txq, i); 1724 if (txq->ift_sds.ifsd_map != NULL) { 1725 free(txq->ift_sds.ifsd_map, M_IFLIB); 1726 txq->ift_sds.ifsd_map = NULL; 1727 } 1728 if (txq->ift_sds.ifsd_m != NULL) { 1729 free(txq->ift_sds.ifsd_m, M_IFLIB); 1730 txq->ift_sds.ifsd_m = NULL; 1731 } 1732 if (txq->ift_sds.ifsd_flags != NULL) { 1733 free(txq->ift_sds.ifsd_flags, M_IFLIB); 1734 txq->ift_sds.ifsd_flags = NULL; 1735 } 1736 if (txq->ift_desc_tag != NULL) { 1737 bus_dma_tag_destroy(txq->ift_desc_tag); 1738 txq->ift_desc_tag = NULL; 1739 } 1740 if (txq->ift_tso_desc_tag != NULL) { 1741 bus_dma_tag_destroy(txq->ift_tso_desc_tag); 1742 txq->ift_tso_desc_tag = NULL; 1743 } 1744 } 1745 1746 static void 1747 iflib_txsd_free(if_ctx_t ctx, iflib_txq_t txq, int i) 1748 { 1749 struct mbuf **mp; 1750 1751 mp = &txq->ift_sds.ifsd_m[i]; 1752 if (*mp == NULL) 1753 return; 1754 1755 if (txq->ift_sds.ifsd_map != NULL) { 1756 bus_dmamap_sync(txq->ift_desc_tag, 1757 txq->ift_sds.ifsd_map[i], 1758 BUS_DMASYNC_POSTWRITE); 1759 bus_dmamap_unload(txq->ift_desc_tag, 1760 txq->ift_sds.ifsd_map[i]); 1761 } 1762 m_free(*mp); 1763 DBG_COUNTER_INC(tx_frees); 1764 *mp = NULL; 1765 } 1766 1767 static int 1768 iflib_txq_setup(iflib_txq_t txq) 1769 { 1770 if_ctx_t ctx = txq->ift_ctx; 1771 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1772 if_shared_ctx_t sctx = ctx->ifc_sctx; 1773 iflib_dma_info_t di; 1774 int i; 1775 1776 /* Set number of descriptors available */ 1777 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 1778 /* XXX make configurable */ 1779 txq->ift_update_freq = IFLIB_DEFAULT_TX_UPDATE_FREQ; 1780 1781 /* Reset indices */ 1782 txq->ift_cidx_processed = 0; 1783 txq->ift_pidx = txq->ift_cidx = txq->ift_npending = 0; 1784 txq->ift_size = scctx->isc_ntxd[txq->ift_br_offset]; 1785 1786 for (i = 0, di = txq->ift_ifdi; i < sctx->isc_ntxqs; i++, di++) 1787 bzero((void *)di->idi_vaddr, di->idi_size); 1788 1789 IFDI_TXQ_SETUP(ctx, txq->ift_id); 1790 for (i = 0, di = txq->ift_ifdi; i < sctx->isc_ntxqs; i++, di++) 1791 bus_dmamap_sync(di->idi_tag, di->idi_map, 1792 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1793 return (0); 1794 } 1795 1796 /********************************************************************* 1797 * 1798 * Allocate memory for rx_buffer structures. Since we use one 1799 * rx_buffer per received packet, the maximum number of rx_buffer's 1800 * that we'll need is equal to the number of receive descriptors 1801 * that we've allocated. 1802 * 1803 **********************************************************************/ 1804 static int 1805 iflib_rxsd_alloc(iflib_rxq_t rxq) 1806 { 1807 if_ctx_t ctx = rxq->ifr_ctx; 1808 if_shared_ctx_t sctx = ctx->ifc_sctx; 1809 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1810 device_t dev = ctx->ifc_dev; 1811 iflib_fl_t fl; 1812 int err; 1813 1814 MPASS(scctx->isc_nrxd[0] > 0); 1815 MPASS(scctx->isc_nrxd[rxq->ifr_fl_offset] > 0); 1816 1817 fl = rxq->ifr_fl; 1818 for (int i = 0; i < rxq->ifr_nfl; i++, fl++) { 1819 fl->ifl_size = scctx->isc_nrxd[rxq->ifr_fl_offset]; /* this isn't necessarily the same */ 1820 err = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */ 1821 1, 0, /* alignment, bounds */ 1822 BUS_SPACE_MAXADDR, /* lowaddr */ 1823 BUS_SPACE_MAXADDR, /* highaddr */ 1824 NULL, NULL, /* filter, filterarg */ 1825 sctx->isc_rx_maxsize, /* maxsize */ 1826 sctx->isc_rx_nsegments, /* nsegments */ 1827 sctx->isc_rx_maxsegsize, /* maxsegsize */ 1828 0, /* flags */ 1829 NULL, /* lockfunc */ 1830 NULL, /* lockarg */ 1831 &fl->ifl_desc_tag); 1832 if (err) { 1833 device_printf(dev, "%s: bus_dma_tag_create failed %d\n", 1834 __func__, err); 1835 goto fail; 1836 } 1837 if (!(fl->ifl_sds.ifsd_flags = 1838 (uint8_t *) malloc(sizeof(uint8_t) * 1839 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1840 device_printf(dev, "Unable to allocate tx_buffer memory\n"); 1841 err = ENOMEM; 1842 goto fail; 1843 } 1844 if (!(fl->ifl_sds.ifsd_m = 1845 (struct mbuf **) malloc(sizeof(struct mbuf *) * 1846 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1847 device_printf(dev, "Unable to allocate tx_buffer memory\n"); 1848 err = ENOMEM; 1849 goto fail; 1850 } 1851 if (!(fl->ifl_sds.ifsd_cl = 1852 (caddr_t *) malloc(sizeof(caddr_t) * 1853 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1854 device_printf(dev, "Unable to allocate tx_buffer memory\n"); 1855 err = ENOMEM; 1856 goto fail; 1857 } 1858 1859 /* Create the descriptor buffer dma maps */ 1860 #if defined(ACPI_DMAR) || (! (defined(__i386__) || defined(__amd64__))) 1861 if ((ctx->ifc_flags & IFC_DMAR) == 0) 1862 continue; 1863 1864 if (!(fl->ifl_sds.ifsd_map = 1865 (bus_dmamap_t *) malloc(sizeof(bus_dmamap_t) * scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1866 device_printf(dev, "Unable to allocate tx_buffer map memory\n"); 1867 err = ENOMEM; 1868 goto fail; 1869 } 1870 1871 for (int i = 0; i < scctx->isc_nrxd[rxq->ifr_fl_offset]; i++) { 1872 err = bus_dmamap_create(fl->ifl_desc_tag, 0, &fl->ifl_sds.ifsd_map[i]); 1873 if (err != 0) { 1874 device_printf(dev, "Unable to create RX buffer DMA map\n"); 1875 goto fail; 1876 } 1877 } 1878 #endif 1879 } 1880 return (0); 1881 1882 fail: 1883 iflib_rx_structures_free(ctx); 1884 return (err); 1885 } 1886 1887 1888 /* 1889 * Internal service routines 1890 */ 1891 1892 struct rxq_refill_cb_arg { 1893 int error; 1894 bus_dma_segment_t seg; 1895 int nseg; 1896 }; 1897 1898 static void 1899 _rxq_refill_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 1900 { 1901 struct rxq_refill_cb_arg *cb_arg = arg; 1902 1903 cb_arg->error = error; 1904 cb_arg->seg = segs[0]; 1905 cb_arg->nseg = nseg; 1906 } 1907 1908 1909 #ifdef ACPI_DMAR 1910 #define IS_DMAR(ctx) (ctx->ifc_flags & IFC_DMAR) 1911 #else 1912 #define IS_DMAR(ctx) (0) 1913 #endif 1914 1915 /** 1916 * rxq_refill - refill an rxq free-buffer list 1917 * @ctx: the iflib context 1918 * @rxq: the free-list to refill 1919 * @n: the number of new buffers to allocate 1920 * 1921 * (Re)populate an rxq free-buffer list with up to @n new packet buffers. 1922 * The caller must assure that @n does not exceed the queue's capacity. 1923 */ 1924 static void 1925 _iflib_fl_refill(if_ctx_t ctx, iflib_fl_t fl, int count) 1926 { 1927 struct mbuf *m; 1928 int idx, frag_idx = fl->ifl_fragidx; 1929 int pidx = fl->ifl_pidx; 1930 caddr_t cl, *sd_cl; 1931 struct mbuf **sd_m; 1932 uint8_t *sd_flags; 1933 struct if_rxd_update iru; 1934 bus_dmamap_t *sd_map; 1935 int n, i = 0; 1936 uint64_t bus_addr; 1937 int err; 1938 qidx_t credits; 1939 1940 sd_m = fl->ifl_sds.ifsd_m; 1941 sd_map = fl->ifl_sds.ifsd_map; 1942 sd_cl = fl->ifl_sds.ifsd_cl; 1943 sd_flags = fl->ifl_sds.ifsd_flags; 1944 idx = pidx; 1945 credits = fl->ifl_credits; 1946 1947 n = count; 1948 MPASS(n > 0); 1949 MPASS(credits + n <= fl->ifl_size); 1950 1951 if (pidx < fl->ifl_cidx) 1952 MPASS(pidx + n <= fl->ifl_cidx); 1953 if (pidx == fl->ifl_cidx && (credits < fl->ifl_size)) 1954 MPASS(fl->ifl_gen == 0); 1955 if (pidx > fl->ifl_cidx) 1956 MPASS(n <= fl->ifl_size - pidx + fl->ifl_cidx); 1957 1958 DBG_COUNTER_INC(fl_refills); 1959 if (n > 8) 1960 DBG_COUNTER_INC(fl_refills_large); 1961 iru_init(&iru, fl->ifl_rxq, fl->ifl_id); 1962 while (n--) { 1963 /* 1964 * We allocate an uninitialized mbuf + cluster, mbuf is 1965 * initialized after rx. 1966 * 1967 * If the cluster is still set then we know a minimum sized packet was received 1968 */ 1969 bit_ffc_at(fl->ifl_rx_bitmap, frag_idx, fl->ifl_size, &frag_idx); 1970 if ((frag_idx < 0) || (frag_idx >= fl->ifl_size)) 1971 bit_ffc(fl->ifl_rx_bitmap, fl->ifl_size, &frag_idx); 1972 if ((cl = sd_cl[frag_idx]) == NULL) { 1973 if ((cl = sd_cl[frag_idx] = m_cljget(NULL, M_NOWAIT, fl->ifl_buf_size)) == NULL) 1974 break; 1975 #if MEMORY_LOGGING 1976 fl->ifl_cl_enqueued++; 1977 #endif 1978 } 1979 if ((m = m_gethdr(M_NOWAIT, MT_NOINIT)) == NULL) { 1980 break; 1981 } 1982 #if MEMORY_LOGGING 1983 fl->ifl_m_enqueued++; 1984 #endif 1985 1986 DBG_COUNTER_INC(rx_allocs); 1987 #if defined(__i386__) || defined(__amd64__) 1988 if (!IS_DMAR(ctx)) { 1989 bus_addr = pmap_kextract((vm_offset_t)cl); 1990 } else 1991 #endif 1992 { 1993 struct rxq_refill_cb_arg cb_arg; 1994 1995 cb_arg.error = 0; 1996 MPASS(sd_map != NULL); 1997 MPASS(sd_map[frag_idx] != NULL); 1998 err = bus_dmamap_load(fl->ifl_desc_tag, sd_map[frag_idx], 1999 cl, fl->ifl_buf_size, _rxq_refill_cb, &cb_arg, 0); 2000 bus_dmamap_sync(fl->ifl_desc_tag, sd_map[frag_idx], 2001 BUS_DMASYNC_PREREAD); 2002 2003 if (err != 0 || cb_arg.error) { 2004 /* 2005 * !zone_pack ? 2006 */ 2007 if (fl->ifl_zone == zone_pack) 2008 uma_zfree(fl->ifl_zone, cl); 2009 m_free(m); 2010 n = 0; 2011 goto done; 2012 } 2013 bus_addr = cb_arg.seg.ds_addr; 2014 } 2015 bit_set(fl->ifl_rx_bitmap, frag_idx); 2016 sd_flags[frag_idx] |= RX_SW_DESC_INUSE; 2017 2018 MPASS(sd_m[frag_idx] == NULL); 2019 sd_cl[frag_idx] = cl; 2020 sd_m[frag_idx] = m; 2021 fl->ifl_rxd_idxs[i] = frag_idx; 2022 fl->ifl_bus_addrs[i] = bus_addr; 2023 fl->ifl_vm_addrs[i] = cl; 2024 credits++; 2025 i++; 2026 MPASS(credits <= fl->ifl_size); 2027 if (++idx == fl->ifl_size) { 2028 fl->ifl_gen = 1; 2029 idx = 0; 2030 } 2031 if (n == 0 || i == IFLIB_MAX_RX_REFRESH) { 2032 iru.iru_pidx = pidx; 2033 iru.iru_count = i; 2034 ctx->isc_rxd_refill(ctx->ifc_softc, &iru); 2035 i = 0; 2036 pidx = idx; 2037 fl->ifl_pidx = idx; 2038 fl->ifl_credits = credits; 2039 } 2040 2041 } 2042 done: 2043 if (i) { 2044 iru.iru_pidx = pidx; 2045 iru.iru_count = i; 2046 ctx->isc_rxd_refill(ctx->ifc_softc, &iru); 2047 fl->ifl_pidx = idx; 2048 fl->ifl_credits = credits; 2049 } 2050 DBG_COUNTER_INC(rxd_flush); 2051 if (fl->ifl_pidx == 0) 2052 pidx = fl->ifl_size - 1; 2053 else 2054 pidx = fl->ifl_pidx - 1; 2055 2056 if (sd_map) 2057 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 2058 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2059 ctx->isc_rxd_flush(ctx->ifc_softc, fl->ifl_rxq->ifr_id, fl->ifl_id, pidx); 2060 fl->ifl_fragidx = frag_idx; 2061 } 2062 2063 static __inline void 2064 __iflib_fl_refill_lt(if_ctx_t ctx, iflib_fl_t fl, int max) 2065 { 2066 /* we avoid allowing pidx to catch up with cidx as it confuses ixl */ 2067 int32_t reclaimable = fl->ifl_size - fl->ifl_credits - 1; 2068 #ifdef INVARIANTS 2069 int32_t delta = fl->ifl_size - get_inuse(fl->ifl_size, fl->ifl_cidx, fl->ifl_pidx, fl->ifl_gen) - 1; 2070 #endif 2071 2072 MPASS(fl->ifl_credits <= fl->ifl_size); 2073 MPASS(reclaimable == delta); 2074 2075 if (reclaimable > 0) 2076 _iflib_fl_refill(ctx, fl, min(max, reclaimable)); 2077 } 2078 2079 uint8_t 2080 iflib_in_detach(if_ctx_t ctx) 2081 { 2082 bool in_detach; 2083 STATE_LOCK(ctx); 2084 in_detach = !!(ctx->ifc_flags & IFC_IN_DETACH); 2085 STATE_UNLOCK(ctx); 2086 return (in_detach); 2087 } 2088 2089 static void 2090 iflib_fl_bufs_free(iflib_fl_t fl) 2091 { 2092 iflib_dma_info_t idi = fl->ifl_ifdi; 2093 uint32_t i; 2094 2095 for (i = 0; i < fl->ifl_size; i++) { 2096 struct mbuf **sd_m = &fl->ifl_sds.ifsd_m[i]; 2097 uint8_t *sd_flags = &fl->ifl_sds.ifsd_flags[i]; 2098 caddr_t *sd_cl = &fl->ifl_sds.ifsd_cl[i]; 2099 2100 if (*sd_flags & RX_SW_DESC_INUSE) { 2101 if (fl->ifl_sds.ifsd_map != NULL) { 2102 bus_dmamap_t sd_map = fl->ifl_sds.ifsd_map[i]; 2103 bus_dmamap_unload(fl->ifl_desc_tag, sd_map); 2104 // XXX: Should this get moved out? 2105 if (iflib_in_detach(fl->ifl_rxq->ifr_ctx)) 2106 bus_dmamap_destroy(fl->ifl_desc_tag, sd_map); 2107 } 2108 if (*sd_m != NULL) { 2109 m_init(*sd_m, M_NOWAIT, MT_DATA, 0); 2110 uma_zfree(zone_mbuf, *sd_m); 2111 } 2112 if (*sd_cl != NULL) 2113 uma_zfree(fl->ifl_zone, *sd_cl); 2114 *sd_flags = 0; 2115 } else { 2116 MPASS(*sd_cl == NULL); 2117 MPASS(*sd_m == NULL); 2118 } 2119 #if MEMORY_LOGGING 2120 fl->ifl_m_dequeued++; 2121 fl->ifl_cl_dequeued++; 2122 #endif 2123 *sd_cl = NULL; 2124 *sd_m = NULL; 2125 } 2126 #ifdef INVARIANTS 2127 for (i = 0; i < fl->ifl_size; i++) { 2128 MPASS(fl->ifl_sds.ifsd_flags[i] == 0); 2129 MPASS(fl->ifl_sds.ifsd_cl[i] == NULL); 2130 MPASS(fl->ifl_sds.ifsd_m[i] == NULL); 2131 } 2132 #endif 2133 /* 2134 * Reset free list values 2135 */ 2136 fl->ifl_credits = fl->ifl_cidx = fl->ifl_pidx = fl->ifl_gen = fl->ifl_fragidx = 0; 2137 bzero(idi->idi_vaddr, idi->idi_size); 2138 } 2139 2140 /********************************************************************* 2141 * 2142 * Initialize a receive ring and its buffers. 2143 * 2144 **********************************************************************/ 2145 static int 2146 iflib_fl_setup(iflib_fl_t fl) 2147 { 2148 iflib_rxq_t rxq = fl->ifl_rxq; 2149 if_ctx_t ctx = rxq->ifr_ctx; 2150 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 2151 2152 bit_nclear(fl->ifl_rx_bitmap, 0, fl->ifl_size - 1); 2153 /* 2154 ** Free current RX buffer structs and their mbufs 2155 */ 2156 iflib_fl_bufs_free(fl); 2157 /* Now replenish the mbufs */ 2158 MPASS(fl->ifl_credits == 0); 2159 /* 2160 * XXX don't set the max_frame_size to larger 2161 * than the hardware can handle 2162 */ 2163 if (sctx->isc_max_frame_size <= 2048) 2164 fl->ifl_buf_size = MCLBYTES; 2165 #ifndef CONTIGMALLOC_WORKS 2166 else 2167 fl->ifl_buf_size = MJUMPAGESIZE; 2168 #else 2169 else if (sctx->isc_max_frame_size <= 4096) 2170 fl->ifl_buf_size = MJUMPAGESIZE; 2171 else if (sctx->isc_max_frame_size <= 9216) 2172 fl->ifl_buf_size = MJUM9BYTES; 2173 else 2174 fl->ifl_buf_size = MJUM16BYTES; 2175 #endif 2176 if (fl->ifl_buf_size > ctx->ifc_max_fl_buf_size) 2177 ctx->ifc_max_fl_buf_size = fl->ifl_buf_size; 2178 fl->ifl_cltype = m_gettype(fl->ifl_buf_size); 2179 fl->ifl_zone = m_getzone(fl->ifl_buf_size); 2180 2181 2182 /* avoid pre-allocating zillions of clusters to an idle card 2183 * potentially speeding up attach 2184 */ 2185 _iflib_fl_refill(ctx, fl, min(128, fl->ifl_size)); 2186 MPASS(min(128, fl->ifl_size) == fl->ifl_credits); 2187 if (min(128, fl->ifl_size) != fl->ifl_credits) 2188 return (ENOBUFS); 2189 /* 2190 * handle failure 2191 */ 2192 MPASS(rxq != NULL); 2193 MPASS(fl->ifl_ifdi != NULL); 2194 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 2195 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2196 return (0); 2197 } 2198 2199 /********************************************************************* 2200 * 2201 * Free receive ring data structures 2202 * 2203 **********************************************************************/ 2204 static void 2205 iflib_rx_sds_free(iflib_rxq_t rxq) 2206 { 2207 iflib_fl_t fl; 2208 int i; 2209 2210 if (rxq->ifr_fl != NULL) { 2211 for (i = 0; i < rxq->ifr_nfl; i++) { 2212 fl = &rxq->ifr_fl[i]; 2213 if (fl->ifl_desc_tag != NULL) { 2214 bus_dma_tag_destroy(fl->ifl_desc_tag); 2215 fl->ifl_desc_tag = NULL; 2216 } 2217 free(fl->ifl_sds.ifsd_m, M_IFLIB); 2218 free(fl->ifl_sds.ifsd_cl, M_IFLIB); 2219 /* XXX destroy maps first */ 2220 free(fl->ifl_sds.ifsd_map, M_IFLIB); 2221 fl->ifl_sds.ifsd_m = NULL; 2222 fl->ifl_sds.ifsd_cl = NULL; 2223 fl->ifl_sds.ifsd_map = NULL; 2224 } 2225 free(rxq->ifr_fl, M_IFLIB); 2226 rxq->ifr_fl = NULL; 2227 rxq->ifr_cq_gen = rxq->ifr_cq_cidx = rxq->ifr_cq_pidx = 0; 2228 } 2229 } 2230 2231 /* 2232 * MI independent logic 2233 * 2234 */ 2235 static void 2236 iflib_timer(void *arg) 2237 { 2238 iflib_txq_t txq = arg; 2239 if_ctx_t ctx = txq->ift_ctx; 2240 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 2241 uint64_t this_tick = ticks; 2242 uint32_t reset_on = hz / 2; 2243 2244 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)) 2245 return; 2246 /* 2247 ** Check on the state of the TX queue(s), this 2248 ** can be done without the lock because its RO 2249 ** and the HUNG state will be static if set. 2250 */ 2251 if (this_tick - txq->ift_last_timer_tick >= hz / 2) { 2252 txq->ift_last_timer_tick = this_tick; 2253 IFDI_TIMER(ctx, txq->ift_id); 2254 if ((txq->ift_qstatus == IFLIB_QUEUE_HUNG) && 2255 ((txq->ift_cleaned_prev == txq->ift_cleaned) || 2256 (sctx->isc_pause_frames == 0))) 2257 goto hung; 2258 2259 if (ifmp_ring_is_stalled(txq->ift_br)) 2260 txq->ift_qstatus = IFLIB_QUEUE_HUNG; 2261 txq->ift_cleaned_prev = txq->ift_cleaned; 2262 } 2263 #ifdef DEV_NETMAP 2264 if (if_getcapenable(ctx->ifc_ifp) & IFCAP_NETMAP) 2265 iflib_netmap_timer_adjust(ctx, txq->ift_id, &reset_on); 2266 #endif 2267 /* handle any laggards */ 2268 if (txq->ift_db_pending) 2269 GROUPTASK_ENQUEUE(&txq->ift_task); 2270 2271 sctx->isc_pause_frames = 0; 2272 if (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING) 2273 callout_reset_on(&txq->ift_timer, reset_on, iflib_timer, txq, txq->ift_timer.c_cpu); 2274 return; 2275 hung: 2276 device_printf(ctx->ifc_dev, "TX(%d) desc avail = %d, pidx = %d\n", 2277 txq->ift_id, TXQ_AVAIL(txq), txq->ift_pidx); 2278 STATE_LOCK(ctx); 2279 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING); 2280 ctx->ifc_flags |= (IFC_DO_WATCHDOG|IFC_DO_RESET); 2281 iflib_admin_intr_deferred(ctx); 2282 STATE_UNLOCK(ctx); 2283 } 2284 2285 static void 2286 iflib_init_locked(if_ctx_t ctx) 2287 { 2288 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 2289 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 2290 if_t ifp = ctx->ifc_ifp; 2291 iflib_fl_t fl; 2292 iflib_txq_t txq; 2293 iflib_rxq_t rxq; 2294 int i, j, tx_ip_csum_flags, tx_ip6_csum_flags; 2295 2296 2297 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING); 2298 IFDI_INTR_DISABLE(ctx); 2299 2300 tx_ip_csum_flags = scctx->isc_tx_csum_flags & (CSUM_IP | CSUM_TCP | CSUM_UDP | CSUM_SCTP); 2301 tx_ip6_csum_flags = scctx->isc_tx_csum_flags & (CSUM_IP6_TCP | CSUM_IP6_UDP | CSUM_IP6_SCTP); 2302 /* Set hardware offload abilities */ 2303 if_clearhwassist(ifp); 2304 if (if_getcapenable(ifp) & IFCAP_TXCSUM) 2305 if_sethwassistbits(ifp, tx_ip_csum_flags, 0); 2306 if (if_getcapenable(ifp) & IFCAP_TXCSUM_IPV6) 2307 if_sethwassistbits(ifp, tx_ip6_csum_flags, 0); 2308 if (if_getcapenable(ifp) & IFCAP_TSO4) 2309 if_sethwassistbits(ifp, CSUM_IP_TSO, 0); 2310 if (if_getcapenable(ifp) & IFCAP_TSO6) 2311 if_sethwassistbits(ifp, CSUM_IP6_TSO, 0); 2312 2313 for (i = 0, txq = ctx->ifc_txqs; i < sctx->isc_ntxqsets; i++, txq++) { 2314 CALLOUT_LOCK(txq); 2315 callout_stop(&txq->ift_timer); 2316 CALLOUT_UNLOCK(txq); 2317 iflib_netmap_txq_init(ctx, txq); 2318 } 2319 #ifdef INVARIANTS 2320 i = if_getdrvflags(ifp); 2321 #endif 2322 IFDI_INIT(ctx); 2323 MPASS(if_getdrvflags(ifp) == i); 2324 for (i = 0, rxq = ctx->ifc_rxqs; i < sctx->isc_nrxqsets; i++, rxq++) { 2325 /* XXX this should really be done on a per-queue basis */ 2326 if (if_getcapenable(ifp) & IFCAP_NETMAP) { 2327 MPASS(rxq->ifr_id == i); 2328 iflib_netmap_rxq_init(ctx, rxq); 2329 continue; 2330 } 2331 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) { 2332 if (iflib_fl_setup(fl)) { 2333 device_printf(ctx->ifc_dev, "freelist setup failed - check cluster settings\n"); 2334 goto done; 2335 } 2336 } 2337 } 2338 done: 2339 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_RUNNING, IFF_DRV_OACTIVE); 2340 IFDI_INTR_ENABLE(ctx); 2341 txq = ctx->ifc_txqs; 2342 for (i = 0; i < sctx->isc_ntxqsets; i++, txq++) 2343 callout_reset_on(&txq->ift_timer, hz/2, iflib_timer, txq, 2344 txq->ift_timer.c_cpu); 2345 } 2346 2347 static int 2348 iflib_media_change(if_t ifp) 2349 { 2350 if_ctx_t ctx = if_getsoftc(ifp); 2351 int err; 2352 2353 CTX_LOCK(ctx); 2354 if ((err = IFDI_MEDIA_CHANGE(ctx)) == 0) 2355 iflib_init_locked(ctx); 2356 CTX_UNLOCK(ctx); 2357 return (err); 2358 } 2359 2360 static void 2361 iflib_media_status(if_t ifp, struct ifmediareq *ifmr) 2362 { 2363 if_ctx_t ctx = if_getsoftc(ifp); 2364 2365 CTX_LOCK(ctx); 2366 IFDI_UPDATE_ADMIN_STATUS(ctx); 2367 IFDI_MEDIA_STATUS(ctx, ifmr); 2368 CTX_UNLOCK(ctx); 2369 } 2370 2371 void 2372 iflib_stop(if_ctx_t ctx) 2373 { 2374 iflib_txq_t txq = ctx->ifc_txqs; 2375 iflib_rxq_t rxq = ctx->ifc_rxqs; 2376 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 2377 if_shared_ctx_t sctx = ctx->ifc_sctx; 2378 iflib_dma_info_t di; 2379 iflib_fl_t fl; 2380 int i, j; 2381 2382 /* Tell the stack that the interface is no longer active */ 2383 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING); 2384 2385 IFDI_INTR_DISABLE(ctx); 2386 DELAY(1000); 2387 IFDI_STOP(ctx); 2388 DELAY(1000); 2389 2390 iflib_debug_reset(); 2391 /* Wait for current tx queue users to exit to disarm watchdog timer. */ 2392 for (i = 0; i < scctx->isc_ntxqsets; i++, txq++) { 2393 /* make sure all transmitters have completed before proceeding XXX */ 2394 2395 CALLOUT_LOCK(txq); 2396 callout_stop(&txq->ift_timer); 2397 CALLOUT_UNLOCK(txq); 2398 2399 /* clean any enqueued buffers */ 2400 iflib_ifmp_purge(txq); 2401 /* Free any existing tx buffers. */ 2402 for (j = 0; j < txq->ift_size; j++) { 2403 iflib_txsd_free(ctx, txq, j); 2404 } 2405 txq->ift_processed = txq->ift_cleaned = txq->ift_cidx_processed = 0; 2406 txq->ift_in_use = txq->ift_gen = txq->ift_cidx = txq->ift_pidx = txq->ift_no_desc_avail = 0; 2407 txq->ift_closed = txq->ift_mbuf_defrag = txq->ift_mbuf_defrag_failed = 0; 2408 txq->ift_no_tx_dma_setup = txq->ift_txd_encap_efbig = txq->ift_map_failed = 0; 2409 txq->ift_pullups = 0; 2410 ifmp_ring_reset_stats(txq->ift_br); 2411 for (j = 0, di = txq->ift_ifdi; j < sctx->isc_ntxqs; j++, di++) 2412 bzero((void *)di->idi_vaddr, di->idi_size); 2413 } 2414 for (i = 0; i < scctx->isc_nrxqsets; i++, rxq++) { 2415 /* make sure all transmitters have completed before proceeding XXX */ 2416 2417 rxq->ifr_cq_gen = rxq->ifr_cq_cidx = rxq->ifr_cq_pidx = 0; 2418 for (j = 0, di = rxq->ifr_ifdi; j < sctx->isc_nrxqs; j++, di++) 2419 bzero((void *)di->idi_vaddr, di->idi_size); 2420 /* also resets the free lists pidx/cidx */ 2421 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) 2422 iflib_fl_bufs_free(fl); 2423 } 2424 } 2425 2426 static inline caddr_t 2427 calc_next_rxd(iflib_fl_t fl, int cidx) 2428 { 2429 qidx_t size; 2430 int nrxd; 2431 caddr_t start, end, cur, next; 2432 2433 nrxd = fl->ifl_size; 2434 size = fl->ifl_rxd_size; 2435 start = fl->ifl_ifdi->idi_vaddr; 2436 2437 if (__predict_false(size == 0)) 2438 return (start); 2439 cur = start + size*cidx; 2440 end = start + size*nrxd; 2441 next = CACHE_PTR_NEXT(cur); 2442 return (next < end ? next : start); 2443 } 2444 2445 static inline void 2446 prefetch_pkts(iflib_fl_t fl, int cidx) 2447 { 2448 int nextptr; 2449 int nrxd = fl->ifl_size; 2450 caddr_t next_rxd; 2451 2452 2453 nextptr = (cidx + CACHE_PTR_INCREMENT) & (nrxd-1); 2454 prefetch(&fl->ifl_sds.ifsd_m[nextptr]); 2455 prefetch(&fl->ifl_sds.ifsd_cl[nextptr]); 2456 next_rxd = calc_next_rxd(fl, cidx); 2457 prefetch(next_rxd); 2458 prefetch(fl->ifl_sds.ifsd_m[(cidx + 1) & (nrxd-1)]); 2459 prefetch(fl->ifl_sds.ifsd_m[(cidx + 2) & (nrxd-1)]); 2460 prefetch(fl->ifl_sds.ifsd_m[(cidx + 3) & (nrxd-1)]); 2461 prefetch(fl->ifl_sds.ifsd_m[(cidx + 4) & (nrxd-1)]); 2462 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 1) & (nrxd-1)]); 2463 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 2) & (nrxd-1)]); 2464 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 3) & (nrxd-1)]); 2465 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 4) & (nrxd-1)]); 2466 } 2467 2468 static void 2469 rxd_frag_to_sd(iflib_rxq_t rxq, if_rxd_frag_t irf, int unload, if_rxsd_t sd) 2470 { 2471 int flid, cidx; 2472 bus_dmamap_t map; 2473 iflib_fl_t fl; 2474 iflib_dma_info_t di; 2475 int next; 2476 2477 map = NULL; 2478 flid = irf->irf_flid; 2479 cidx = irf->irf_idx; 2480 fl = &rxq->ifr_fl[flid]; 2481 sd->ifsd_fl = fl; 2482 sd->ifsd_cidx = cidx; 2483 sd->ifsd_m = &fl->ifl_sds.ifsd_m[cidx]; 2484 sd->ifsd_cl = &fl->ifl_sds.ifsd_cl[cidx]; 2485 fl->ifl_credits--; 2486 #if MEMORY_LOGGING 2487 fl->ifl_m_dequeued++; 2488 #endif 2489 if (rxq->ifr_ctx->ifc_flags & IFC_PREFETCH) 2490 prefetch_pkts(fl, cidx); 2491 if (fl->ifl_sds.ifsd_map != NULL) { 2492 next = (cidx + CACHE_PTR_INCREMENT) & (fl->ifl_size-1); 2493 prefetch(&fl->ifl_sds.ifsd_map[next]); 2494 map = fl->ifl_sds.ifsd_map[cidx]; 2495 di = fl->ifl_ifdi; 2496 next = (cidx + CACHE_LINE_SIZE) & (fl->ifl_size-1); 2497 prefetch(&fl->ifl_sds.ifsd_flags[next]); 2498 bus_dmamap_sync(di->idi_tag, di->idi_map, 2499 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2500 2501 /* not valid assert if bxe really does SGE from non-contiguous elements */ 2502 MPASS(fl->ifl_cidx == cidx); 2503 if (unload) 2504 bus_dmamap_unload(fl->ifl_desc_tag, map); 2505 } 2506 fl->ifl_cidx = (fl->ifl_cidx + 1) & (fl->ifl_size-1); 2507 if (__predict_false(fl->ifl_cidx == 0)) 2508 fl->ifl_gen = 0; 2509 if (map != NULL) 2510 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 2511 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2512 bit_clear(fl->ifl_rx_bitmap, cidx); 2513 } 2514 2515 static struct mbuf * 2516 assemble_segments(iflib_rxq_t rxq, if_rxd_info_t ri, if_rxsd_t sd) 2517 { 2518 int i, padlen , flags; 2519 struct mbuf *m, *mh, *mt; 2520 caddr_t cl; 2521 2522 i = 0; 2523 mh = NULL; 2524 do { 2525 rxd_frag_to_sd(rxq, &ri->iri_frags[i], TRUE, sd); 2526 2527 MPASS(*sd->ifsd_cl != NULL); 2528 MPASS(*sd->ifsd_m != NULL); 2529 2530 /* Don't include zero-length frags */ 2531 if (ri->iri_frags[i].irf_len == 0) { 2532 /* XXX we can save the cluster here, but not the mbuf */ 2533 m_init(*sd->ifsd_m, M_NOWAIT, MT_DATA, 0); 2534 m_free(*sd->ifsd_m); 2535 *sd->ifsd_m = NULL; 2536 continue; 2537 } 2538 m = *sd->ifsd_m; 2539 *sd->ifsd_m = NULL; 2540 if (mh == NULL) { 2541 flags = M_PKTHDR|M_EXT; 2542 mh = mt = m; 2543 padlen = ri->iri_pad; 2544 } else { 2545 flags = M_EXT; 2546 mt->m_next = m; 2547 mt = m; 2548 /* assuming padding is only on the first fragment */ 2549 padlen = 0; 2550 } 2551 cl = *sd->ifsd_cl; 2552 *sd->ifsd_cl = NULL; 2553 2554 /* Can these two be made one ? */ 2555 m_init(m, M_NOWAIT, MT_DATA, flags); 2556 m_cljset(m, cl, sd->ifsd_fl->ifl_cltype); 2557 /* 2558 * These must follow m_init and m_cljset 2559 */ 2560 m->m_data += padlen; 2561 ri->iri_len -= padlen; 2562 m->m_len = ri->iri_frags[i].irf_len; 2563 } while (++i < ri->iri_nfrags); 2564 2565 return (mh); 2566 } 2567 2568 /* 2569 * Process one software descriptor 2570 */ 2571 static struct mbuf * 2572 iflib_rxd_pkt_get(iflib_rxq_t rxq, if_rxd_info_t ri) 2573 { 2574 struct if_rxsd sd; 2575 struct mbuf *m; 2576 2577 /* should I merge this back in now that the two paths are basically duplicated? */ 2578 if (ri->iri_nfrags == 1 && 2579 ri->iri_frags[0].irf_len <= MIN(IFLIB_RX_COPY_THRESH, MHLEN)) { 2580 rxd_frag_to_sd(rxq, &ri->iri_frags[0], FALSE, &sd); 2581 m = *sd.ifsd_m; 2582 *sd.ifsd_m = NULL; 2583 m_init(m, M_NOWAIT, MT_DATA, M_PKTHDR); 2584 #ifndef __NO_STRICT_ALIGNMENT 2585 if (!IP_ALIGNED(m)) 2586 m->m_data += 2; 2587 #endif 2588 memcpy(m->m_data, *sd.ifsd_cl, ri->iri_len); 2589 m->m_len = ri->iri_frags[0].irf_len; 2590 } else { 2591 m = assemble_segments(rxq, ri, &sd); 2592 } 2593 m->m_pkthdr.len = ri->iri_len; 2594 m->m_pkthdr.rcvif = ri->iri_ifp; 2595 m->m_flags |= ri->iri_flags; 2596 m->m_pkthdr.ether_vtag = ri->iri_vtag; 2597 m->m_pkthdr.flowid = ri->iri_flowid; 2598 M_HASHTYPE_SET(m, ri->iri_rsstype); 2599 m->m_pkthdr.csum_flags = ri->iri_csum_flags; 2600 m->m_pkthdr.csum_data = ri->iri_csum_data; 2601 return (m); 2602 } 2603 2604 #if defined(INET6) || defined(INET) 2605 static void 2606 iflib_get_ip_forwarding(struct lro_ctrl *lc, bool *v4, bool *v6) 2607 { 2608 CURVNET_SET(lc->ifp->if_vnet); 2609 #if defined(INET6) 2610 *v6 = VNET(ip6_forwarding); 2611 #endif 2612 #if defined(INET) 2613 *v4 = VNET(ipforwarding); 2614 #endif 2615 CURVNET_RESTORE(); 2616 } 2617 2618 /* 2619 * Returns true if it's possible this packet could be LROed. 2620 * if it returns false, it is guaranteed that tcp_lro_rx() 2621 * would not return zero. 2622 */ 2623 static bool 2624 iflib_check_lro_possible(struct mbuf *m, bool v4_forwarding, bool v6_forwarding) 2625 { 2626 struct ether_header *eh; 2627 uint16_t eh_type; 2628 2629 eh = mtod(m, struct ether_header *); 2630 eh_type = ntohs(eh->ether_type); 2631 switch (eh_type) { 2632 #if defined(INET6) 2633 case ETHERTYPE_IPV6: 2634 return !v6_forwarding; 2635 #endif 2636 #if defined (INET) 2637 case ETHERTYPE_IP: 2638 return !v4_forwarding; 2639 #endif 2640 } 2641 2642 return false; 2643 } 2644 #else 2645 static void 2646 iflib_get_ip_forwarding(struct lro_ctrl *lc __unused, bool *v4 __unused, bool *v6 __unused) 2647 { 2648 } 2649 #endif 2650 2651 static bool 2652 iflib_rxeof(iflib_rxq_t rxq, qidx_t budget) 2653 { 2654 if_ctx_t ctx = rxq->ifr_ctx; 2655 if_shared_ctx_t sctx = ctx->ifc_sctx; 2656 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 2657 int avail, i; 2658 qidx_t *cidxp; 2659 struct if_rxd_info ri; 2660 int err, budget_left, rx_bytes, rx_pkts; 2661 iflib_fl_t fl; 2662 struct ifnet *ifp; 2663 int lro_enabled; 2664 bool v4_forwarding, v6_forwarding, lro_possible; 2665 2666 /* 2667 * XXX early demux data packets so that if_input processing only handles 2668 * acks in interrupt context 2669 */ 2670 struct mbuf *m, *mh, *mt, *mf; 2671 2672 lro_possible = v4_forwarding = v6_forwarding = false; 2673 ifp = ctx->ifc_ifp; 2674 mh = mt = NULL; 2675 MPASS(budget > 0); 2676 rx_pkts = rx_bytes = 0; 2677 if (sctx->isc_flags & IFLIB_HAS_RXCQ) 2678 cidxp = &rxq->ifr_cq_cidx; 2679 else 2680 cidxp = &rxq->ifr_fl[0].ifl_cidx; 2681 if ((avail = iflib_rxd_avail(ctx, rxq, *cidxp, budget)) == 0) { 2682 for (i = 0, fl = &rxq->ifr_fl[0]; i < sctx->isc_nfl; i++, fl++) 2683 __iflib_fl_refill_lt(ctx, fl, budget + 8); 2684 DBG_COUNTER_INC(rx_unavail); 2685 return (false); 2686 } 2687 2688 for (budget_left = budget; budget_left > 0 && avail > 0;) { 2689 if (__predict_false(!CTX_ACTIVE(ctx))) { 2690 DBG_COUNTER_INC(rx_ctx_inactive); 2691 break; 2692 } 2693 /* 2694 * Reset client set fields to their default values 2695 */ 2696 rxd_info_zero(&ri); 2697 ri.iri_qsidx = rxq->ifr_id; 2698 ri.iri_cidx = *cidxp; 2699 ri.iri_ifp = ifp; 2700 ri.iri_frags = rxq->ifr_frags; 2701 err = ctx->isc_rxd_pkt_get(ctx->ifc_softc, &ri); 2702 2703 if (err) 2704 goto err; 2705 if (sctx->isc_flags & IFLIB_HAS_RXCQ) { 2706 *cidxp = ri.iri_cidx; 2707 /* Update our consumer index */ 2708 /* XXX NB: shurd - check if this is still safe */ 2709 while (rxq->ifr_cq_cidx >= scctx->isc_nrxd[0]) { 2710 rxq->ifr_cq_cidx -= scctx->isc_nrxd[0]; 2711 rxq->ifr_cq_gen = 0; 2712 } 2713 /* was this only a completion queue message? */ 2714 if (__predict_false(ri.iri_nfrags == 0)) 2715 continue; 2716 } 2717 MPASS(ri.iri_nfrags != 0); 2718 MPASS(ri.iri_len != 0); 2719 2720 /* will advance the cidx on the corresponding free lists */ 2721 m = iflib_rxd_pkt_get(rxq, &ri); 2722 avail--; 2723 budget_left--; 2724 if (avail == 0 && budget_left) 2725 avail = iflib_rxd_avail(ctx, rxq, *cidxp, budget_left); 2726 2727 if (__predict_false(m == NULL)) { 2728 DBG_COUNTER_INC(rx_mbuf_null); 2729 continue; 2730 } 2731 /* imm_pkt: -- cxgb */ 2732 if (mh == NULL) 2733 mh = mt = m; 2734 else { 2735 mt->m_nextpkt = m; 2736 mt = m; 2737 } 2738 } 2739 /* make sure that we can refill faster than drain */ 2740 for (i = 0, fl = &rxq->ifr_fl[0]; i < sctx->isc_nfl; i++, fl++) 2741 __iflib_fl_refill_lt(ctx, fl, budget + 8); 2742 2743 lro_enabled = (if_getcapenable(ifp) & IFCAP_LRO); 2744 if (lro_enabled) 2745 iflib_get_ip_forwarding(&rxq->ifr_lc, &v4_forwarding, &v6_forwarding); 2746 mt = mf = NULL; 2747 while (mh != NULL) { 2748 m = mh; 2749 mh = mh->m_nextpkt; 2750 m->m_nextpkt = NULL; 2751 #ifndef __NO_STRICT_ALIGNMENT 2752 if (!IP_ALIGNED(m) && (m = iflib_fixup_rx(m)) == NULL) 2753 continue; 2754 #endif 2755 rx_bytes += m->m_pkthdr.len; 2756 rx_pkts++; 2757 #if defined(INET6) || defined(INET) 2758 if (lro_enabled) { 2759 if (!lro_possible) { 2760 lro_possible = iflib_check_lro_possible(m, v4_forwarding, v6_forwarding); 2761 if (lro_possible && mf != NULL) { 2762 ifp->if_input(ifp, mf); 2763 DBG_COUNTER_INC(rx_if_input); 2764 mt = mf = NULL; 2765 } 2766 } 2767 if ((m->m_pkthdr.csum_flags & (CSUM_L4_CALC|CSUM_L4_VALID)) == 2768 (CSUM_L4_CALC|CSUM_L4_VALID)) { 2769 if (lro_possible && tcp_lro_rx(&rxq->ifr_lc, m, 0) == 0) 2770 continue; 2771 } 2772 } 2773 #endif 2774 if (lro_possible) { 2775 ifp->if_input(ifp, m); 2776 DBG_COUNTER_INC(rx_if_input); 2777 continue; 2778 } 2779 2780 if (mf == NULL) 2781 mf = m; 2782 if (mt != NULL) 2783 mt->m_nextpkt = m; 2784 mt = m; 2785 } 2786 if (mf != NULL) { 2787 ifp->if_input(ifp, mf); 2788 DBG_COUNTER_INC(rx_if_input); 2789 } 2790 2791 if_inc_counter(ifp, IFCOUNTER_IBYTES, rx_bytes); 2792 if_inc_counter(ifp, IFCOUNTER_IPACKETS, rx_pkts); 2793 2794 /* 2795 * Flush any outstanding LRO work 2796 */ 2797 #if defined(INET6) || defined(INET) 2798 tcp_lro_flush_all(&rxq->ifr_lc); 2799 #endif 2800 if (avail) 2801 return true; 2802 return (iflib_rxd_avail(ctx, rxq, *cidxp, 1)); 2803 err: 2804 STATE_LOCK(ctx); 2805 ctx->ifc_flags |= IFC_DO_RESET; 2806 iflib_admin_intr_deferred(ctx); 2807 STATE_UNLOCK(ctx); 2808 return (false); 2809 } 2810 2811 #define TXD_NOTIFY_COUNT(txq) (((txq)->ift_size / (txq)->ift_update_freq)-1) 2812 static inline qidx_t 2813 txq_max_db_deferred(iflib_txq_t txq, qidx_t in_use) 2814 { 2815 qidx_t notify_count = TXD_NOTIFY_COUNT(txq); 2816 qidx_t minthresh = txq->ift_size / 8; 2817 if (in_use > 4*minthresh) 2818 return (notify_count); 2819 if (in_use > 2*minthresh) 2820 return (notify_count >> 1); 2821 if (in_use > minthresh) 2822 return (notify_count >> 3); 2823 return (0); 2824 } 2825 2826 static inline qidx_t 2827 txq_max_rs_deferred(iflib_txq_t txq) 2828 { 2829 qidx_t notify_count = TXD_NOTIFY_COUNT(txq); 2830 qidx_t minthresh = txq->ift_size / 8; 2831 if (txq->ift_in_use > 4*minthresh) 2832 return (notify_count); 2833 if (txq->ift_in_use > 2*minthresh) 2834 return (notify_count >> 1); 2835 if (txq->ift_in_use > minthresh) 2836 return (notify_count >> 2); 2837 return (2); 2838 } 2839 2840 #define M_CSUM_FLAGS(m) ((m)->m_pkthdr.csum_flags) 2841 #define M_HAS_VLANTAG(m) (m->m_flags & M_VLANTAG) 2842 2843 #define TXQ_MAX_DB_DEFERRED(txq, in_use) txq_max_db_deferred((txq), (in_use)) 2844 #define TXQ_MAX_RS_DEFERRED(txq) txq_max_rs_deferred(txq) 2845 #define TXQ_MAX_DB_CONSUMED(size) (size >> 4) 2846 2847 /* forward compatibility for cxgb */ 2848 #define FIRST_QSET(ctx) 0 2849 #define NTXQSETS(ctx) ((ctx)->ifc_softc_ctx.isc_ntxqsets) 2850 #define NRXQSETS(ctx) ((ctx)->ifc_softc_ctx.isc_nrxqsets) 2851 #define QIDX(ctx, m) ((((m)->m_pkthdr.flowid & ctx->ifc_softc_ctx.isc_rss_table_mask) % NTXQSETS(ctx)) + FIRST_QSET(ctx)) 2852 #define DESC_RECLAIMABLE(q) ((int)((q)->ift_processed - (q)->ift_cleaned - (q)->ift_ctx->ifc_softc_ctx.isc_tx_nsegments)) 2853 2854 /* XXX we should be setting this to something other than zero */ 2855 #define RECLAIM_THRESH(ctx) ((ctx)->ifc_sctx->isc_tx_reclaim_thresh) 2856 #define MAX_TX_DESC(ctx) max((ctx)->ifc_softc_ctx.isc_tx_tso_segments_max, \ 2857 (ctx)->ifc_softc_ctx.isc_tx_nsegments) 2858 2859 static inline bool 2860 iflib_txd_db_check(if_ctx_t ctx, iflib_txq_t txq, int ring, qidx_t in_use) 2861 { 2862 qidx_t dbval, max; 2863 bool rang; 2864 2865 rang = false; 2866 max = TXQ_MAX_DB_DEFERRED(txq, in_use); 2867 if (ring || txq->ift_db_pending >= max) { 2868 dbval = txq->ift_npending ? txq->ift_npending : txq->ift_pidx; 2869 ctx->isc_txd_flush(ctx->ifc_softc, txq->ift_id, dbval); 2870 txq->ift_db_pending = txq->ift_npending = 0; 2871 rang = true; 2872 } 2873 return (rang); 2874 } 2875 2876 #ifdef PKT_DEBUG 2877 static void 2878 print_pkt(if_pkt_info_t pi) 2879 { 2880 printf("pi len: %d qsidx: %d nsegs: %d ndescs: %d flags: %x pidx: %d\n", 2881 pi->ipi_len, pi->ipi_qsidx, pi->ipi_nsegs, pi->ipi_ndescs, pi->ipi_flags, pi->ipi_pidx); 2882 printf("pi new_pidx: %d csum_flags: %lx tso_segsz: %d mflags: %x vtag: %d\n", 2883 pi->ipi_new_pidx, pi->ipi_csum_flags, pi->ipi_tso_segsz, pi->ipi_mflags, pi->ipi_vtag); 2884 printf("pi etype: %d ehdrlen: %d ip_hlen: %d ipproto: %d\n", 2885 pi->ipi_etype, pi->ipi_ehdrlen, pi->ipi_ip_hlen, pi->ipi_ipproto); 2886 } 2887 #endif 2888 2889 #define IS_TSO4(pi) ((pi)->ipi_csum_flags & CSUM_IP_TSO) 2890 #define IS_TX_OFFLOAD4(pi) ((pi)->ipi_csum_flags & (CSUM_IP_TCP | CSUM_IP_TSO)) 2891 #define IS_TSO6(pi) ((pi)->ipi_csum_flags & CSUM_IP6_TSO) 2892 #define IS_TX_OFFLOAD6(pi) ((pi)->ipi_csum_flags & (CSUM_IP6_TCP | CSUM_IP6_TSO)) 2893 2894 static int 2895 iflib_parse_header(iflib_txq_t txq, if_pkt_info_t pi, struct mbuf **mp) 2896 { 2897 if_shared_ctx_t sctx = txq->ift_ctx->ifc_sctx; 2898 struct ether_vlan_header *eh; 2899 struct mbuf *m; 2900 2901 m = *mp; 2902 if ((sctx->isc_flags & IFLIB_NEED_SCRATCH) && 2903 M_WRITABLE(m) == 0) { 2904 if ((m = m_dup(m, M_NOWAIT)) == NULL) { 2905 return (ENOMEM); 2906 } else { 2907 m_freem(*mp); 2908 DBG_COUNTER_INC(tx_frees); 2909 *mp = m; 2910 } 2911 } 2912 2913 /* 2914 * Determine where frame payload starts. 2915 * Jump over vlan headers if already present, 2916 * helpful for QinQ too. 2917 */ 2918 if (__predict_false(m->m_len < sizeof(*eh))) { 2919 txq->ift_pullups++; 2920 if (__predict_false((m = m_pullup(m, sizeof(*eh))) == NULL)) 2921 return (ENOMEM); 2922 } 2923 eh = mtod(m, struct ether_vlan_header *); 2924 if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) { 2925 pi->ipi_etype = ntohs(eh->evl_proto); 2926 pi->ipi_ehdrlen = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 2927 } else { 2928 pi->ipi_etype = ntohs(eh->evl_encap_proto); 2929 pi->ipi_ehdrlen = ETHER_HDR_LEN; 2930 } 2931 2932 switch (pi->ipi_etype) { 2933 #ifdef INET 2934 case ETHERTYPE_IP: 2935 { 2936 struct mbuf *n; 2937 struct ip *ip = NULL; 2938 struct tcphdr *th = NULL; 2939 int minthlen; 2940 2941 minthlen = min(m->m_pkthdr.len, pi->ipi_ehdrlen + sizeof(*ip) + sizeof(*th)); 2942 if (__predict_false(m->m_len < minthlen)) { 2943 /* 2944 * if this code bloat is causing too much of a hit 2945 * move it to a separate function and mark it noinline 2946 */ 2947 if (m->m_len == pi->ipi_ehdrlen) { 2948 n = m->m_next; 2949 MPASS(n); 2950 if (n->m_len >= sizeof(*ip)) { 2951 ip = (struct ip *)n->m_data; 2952 if (n->m_len >= (ip->ip_hl << 2) + sizeof(*th)) 2953 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2)); 2954 } else { 2955 txq->ift_pullups++; 2956 if (__predict_false((m = m_pullup(m, minthlen)) == NULL)) 2957 return (ENOMEM); 2958 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen); 2959 } 2960 } else { 2961 txq->ift_pullups++; 2962 if (__predict_false((m = m_pullup(m, minthlen)) == NULL)) 2963 return (ENOMEM); 2964 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen); 2965 if (m->m_len >= (ip->ip_hl << 2) + sizeof(*th)) 2966 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2)); 2967 } 2968 } else { 2969 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen); 2970 if (m->m_len >= (ip->ip_hl << 2) + sizeof(*th)) 2971 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2)); 2972 } 2973 pi->ipi_ip_hlen = ip->ip_hl << 2; 2974 pi->ipi_ipproto = ip->ip_p; 2975 pi->ipi_flags |= IPI_TX_IPV4; 2976 2977 /* TCP checksum offload may require TCP header length */ 2978 if (IS_TX_OFFLOAD4(pi)) { 2979 if (__predict_true(pi->ipi_ipproto == IPPROTO_TCP)) { 2980 if (__predict_false(th == NULL)) { 2981 txq->ift_pullups++; 2982 if (__predict_false((m = m_pullup(m, (ip->ip_hl << 2) + sizeof(*th))) == NULL)) 2983 return (ENOMEM); 2984 th = (struct tcphdr *)((caddr_t)ip + pi->ipi_ip_hlen); 2985 } 2986 pi->ipi_tcp_hflags = th->th_flags; 2987 pi->ipi_tcp_hlen = th->th_off << 2; 2988 pi->ipi_tcp_seq = th->th_seq; 2989 } 2990 if (IS_TSO4(pi)) { 2991 if (__predict_false(ip->ip_p != IPPROTO_TCP)) 2992 return (ENXIO); 2993 /* 2994 * TSO always requires hardware checksum offload. 2995 */ 2996 pi->ipi_csum_flags |= (CSUM_IP_TCP | CSUM_IP); 2997 th->th_sum = in_pseudo(ip->ip_src.s_addr, 2998 ip->ip_dst.s_addr, htons(IPPROTO_TCP)); 2999 pi->ipi_tso_segsz = m->m_pkthdr.tso_segsz; 3000 if (sctx->isc_flags & IFLIB_TSO_INIT_IP) { 3001 ip->ip_sum = 0; 3002 ip->ip_len = htons(pi->ipi_ip_hlen + pi->ipi_tcp_hlen + pi->ipi_tso_segsz); 3003 } 3004 } 3005 } 3006 if ((sctx->isc_flags & IFLIB_NEED_ZERO_CSUM) && (pi->ipi_csum_flags & CSUM_IP)) 3007 ip->ip_sum = 0; 3008 3009 break; 3010 } 3011 #endif 3012 #ifdef INET6 3013 case ETHERTYPE_IPV6: 3014 { 3015 struct ip6_hdr *ip6 = (struct ip6_hdr *)(m->m_data + pi->ipi_ehdrlen); 3016 struct tcphdr *th; 3017 pi->ipi_ip_hlen = sizeof(struct ip6_hdr); 3018 3019 if (__predict_false(m->m_len < pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) { 3020 txq->ift_pullups++; 3021 if (__predict_false((m = m_pullup(m, pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) == NULL)) 3022 return (ENOMEM); 3023 } 3024 th = (struct tcphdr *)((caddr_t)ip6 + pi->ipi_ip_hlen); 3025 3026 /* XXX-BZ this will go badly in case of ext hdrs. */ 3027 pi->ipi_ipproto = ip6->ip6_nxt; 3028 pi->ipi_flags |= IPI_TX_IPV6; 3029 3030 /* TCP checksum offload may require TCP header length */ 3031 if (IS_TX_OFFLOAD6(pi)) { 3032 if (pi->ipi_ipproto == IPPROTO_TCP) { 3033 if (__predict_false(m->m_len < pi->ipi_ehdrlen + sizeof(struct ip6_hdr) + sizeof(struct tcphdr))) { 3034 txq->ift_pullups++; 3035 if (__predict_false((m = m_pullup(m, pi->ipi_ehdrlen + sizeof(struct ip6_hdr) + sizeof(struct tcphdr))) == NULL)) 3036 return (ENOMEM); 3037 } 3038 pi->ipi_tcp_hflags = th->th_flags; 3039 pi->ipi_tcp_hlen = th->th_off << 2; 3040 pi->ipi_tcp_seq = th->th_seq; 3041 } 3042 if (IS_TSO6(pi)) { 3043 if (__predict_false(ip6->ip6_nxt != IPPROTO_TCP)) 3044 return (ENXIO); 3045 /* 3046 * TSO always requires hardware checksum offload. 3047 */ 3048 pi->ipi_csum_flags |= CSUM_IP6_TCP; 3049 th->th_sum = in6_cksum_pseudo(ip6, 0, IPPROTO_TCP, 0); 3050 pi->ipi_tso_segsz = m->m_pkthdr.tso_segsz; 3051 } 3052 } 3053 break; 3054 } 3055 #endif 3056 default: 3057 pi->ipi_csum_flags &= ~CSUM_OFFLOAD; 3058 pi->ipi_ip_hlen = 0; 3059 break; 3060 } 3061 *mp = m; 3062 3063 return (0); 3064 } 3065 3066 /* 3067 * If dodgy hardware rejects the scatter gather chain we've handed it 3068 * we'll need to remove the mbuf chain from ifsg_m[] before we can add the 3069 * m_defrag'd mbufs 3070 */ 3071 static __noinline struct mbuf * 3072 iflib_remove_mbuf(iflib_txq_t txq) 3073 { 3074 int ntxd, i, pidx; 3075 struct mbuf *m, *mh, **ifsd_m; 3076 3077 pidx = txq->ift_pidx; 3078 ifsd_m = txq->ift_sds.ifsd_m; 3079 ntxd = txq->ift_size; 3080 mh = m = ifsd_m[pidx]; 3081 ifsd_m[pidx] = NULL; 3082 #if MEMORY_LOGGING 3083 txq->ift_dequeued++; 3084 #endif 3085 i = 1; 3086 3087 while (m) { 3088 ifsd_m[(pidx + i) & (ntxd -1)] = NULL; 3089 #if MEMORY_LOGGING 3090 txq->ift_dequeued++; 3091 #endif 3092 m = m->m_next; 3093 i++; 3094 } 3095 return (mh); 3096 } 3097 3098 static int 3099 iflib_busdma_load_mbuf_sg(iflib_txq_t txq, bus_dma_tag_t tag, bus_dmamap_t map, 3100 struct mbuf **m0, bus_dma_segment_t *segs, int *nsegs, 3101 int max_segs, int flags) 3102 { 3103 if_ctx_t ctx; 3104 if_shared_ctx_t sctx; 3105 if_softc_ctx_t scctx; 3106 int i, next, pidx, err, ntxd, count; 3107 struct mbuf *m, *tmp, **ifsd_m; 3108 3109 m = *m0; 3110 3111 /* 3112 * Please don't ever do this 3113 */ 3114 MPASS(__predict_true(m->m_len > 0)); 3115 3116 ctx = txq->ift_ctx; 3117 sctx = ctx->ifc_sctx; 3118 scctx = &ctx->ifc_softc_ctx; 3119 ifsd_m = txq->ift_sds.ifsd_m; 3120 ntxd = txq->ift_size; 3121 pidx = txq->ift_pidx; 3122 if (map != NULL) { 3123 uint8_t *ifsd_flags = txq->ift_sds.ifsd_flags; 3124 3125 err = bus_dmamap_load_mbuf_sg(tag, map, 3126 *m0, segs, nsegs, BUS_DMA_NOWAIT); 3127 if (err) 3128 return (err); 3129 ifsd_flags[pidx] |= TX_SW_DESC_MAPPED; 3130 count = 0; 3131 m = *m0; 3132 do { 3133 if (__predict_false(m->m_len <= 0)) { 3134 tmp = m; 3135 m = m->m_next; 3136 tmp->m_next = NULL; 3137 m_free(tmp); 3138 continue; 3139 } 3140 m = m->m_next; 3141 count++; 3142 } while (m != NULL); 3143 if (count > *nsegs) { 3144 ifsd_m[pidx] = *m0; 3145 ifsd_m[pidx]->m_flags |= M_TOOBIG; 3146 return (0); 3147 } 3148 m = *m0; 3149 count = 0; 3150 do { 3151 next = (pidx + count) & (ntxd-1); 3152 MPASS(ifsd_m[next] == NULL); 3153 ifsd_m[next] = m; 3154 count++; 3155 tmp = m; 3156 m = m->m_next; 3157 } while (m != NULL); 3158 } else { 3159 int buflen, sgsize, maxsegsz, max_sgsize; 3160 vm_offset_t vaddr; 3161 vm_paddr_t curaddr; 3162 3163 count = i = 0; 3164 m = *m0; 3165 if (m->m_pkthdr.csum_flags & CSUM_TSO) 3166 maxsegsz = scctx->isc_tx_tso_segsize_max; 3167 else 3168 maxsegsz = sctx->isc_tx_maxsegsize; 3169 3170 do { 3171 if (__predict_false(m->m_len <= 0)) { 3172 tmp = m; 3173 m = m->m_next; 3174 tmp->m_next = NULL; 3175 m_free(tmp); 3176 continue; 3177 } 3178 buflen = m->m_len; 3179 vaddr = (vm_offset_t)m->m_data; 3180 /* 3181 * see if we can't be smarter about physically 3182 * contiguous mappings 3183 */ 3184 next = (pidx + count) & (ntxd-1); 3185 MPASS(ifsd_m[next] == NULL); 3186 #if MEMORY_LOGGING 3187 txq->ift_enqueued++; 3188 #endif 3189 ifsd_m[next] = m; 3190 while (buflen > 0) { 3191 if (i >= max_segs) 3192 goto err; 3193 max_sgsize = MIN(buflen, maxsegsz); 3194 curaddr = pmap_kextract(vaddr); 3195 sgsize = PAGE_SIZE - (curaddr & PAGE_MASK); 3196 sgsize = MIN(sgsize, max_sgsize); 3197 segs[i].ds_addr = curaddr; 3198 segs[i].ds_len = sgsize; 3199 vaddr += sgsize; 3200 buflen -= sgsize; 3201 i++; 3202 } 3203 count++; 3204 tmp = m; 3205 m = m->m_next; 3206 } while (m != NULL); 3207 *nsegs = i; 3208 } 3209 return (0); 3210 err: 3211 *m0 = iflib_remove_mbuf(txq); 3212 return (EFBIG); 3213 } 3214 3215 static inline caddr_t 3216 calc_next_txd(iflib_txq_t txq, int cidx, uint8_t qid) 3217 { 3218 qidx_t size; 3219 int ntxd; 3220 caddr_t start, end, cur, next; 3221 3222 ntxd = txq->ift_size; 3223 size = txq->ift_txd_size[qid]; 3224 start = txq->ift_ifdi[qid].idi_vaddr; 3225 3226 if (__predict_false(size == 0)) 3227 return (start); 3228 cur = start + size*cidx; 3229 end = start + size*ntxd; 3230 next = CACHE_PTR_NEXT(cur); 3231 return (next < end ? next : start); 3232 } 3233 3234 /* 3235 * Pad an mbuf to ensure a minimum ethernet frame size. 3236 * min_frame_size is the frame size (less CRC) to pad the mbuf to 3237 */ 3238 static __noinline int 3239 iflib_ether_pad(device_t dev, struct mbuf **m_head, uint16_t min_frame_size) 3240 { 3241 /* 3242 * 18 is enough bytes to pad an ARP packet to 46 bytes, and 3243 * and ARP message is the smallest common payload I can think of 3244 */ 3245 static char pad[18]; /* just zeros */ 3246 int n; 3247 struct mbuf *new_head; 3248 3249 if (!M_WRITABLE(*m_head)) { 3250 new_head = m_dup(*m_head, M_NOWAIT); 3251 if (new_head == NULL) { 3252 m_freem(*m_head); 3253 device_printf(dev, "cannot pad short frame, m_dup() failed"); 3254 DBG_COUNTER_INC(encap_pad_mbuf_fail); 3255 DBG_COUNTER_INC(tx_frees); 3256 return ENOMEM; 3257 } 3258 m_freem(*m_head); 3259 *m_head = new_head; 3260 } 3261 3262 for (n = min_frame_size - (*m_head)->m_pkthdr.len; 3263 n > 0; n -= sizeof(pad)) 3264 if (!m_append(*m_head, min(n, sizeof(pad)), pad)) 3265 break; 3266 3267 if (n > 0) { 3268 m_freem(*m_head); 3269 device_printf(dev, "cannot pad short frame\n"); 3270 DBG_COUNTER_INC(encap_pad_mbuf_fail); 3271 DBG_COUNTER_INC(tx_frees); 3272 return (ENOBUFS); 3273 } 3274 3275 return 0; 3276 } 3277 3278 static int 3279 iflib_encap(iflib_txq_t txq, struct mbuf **m_headp) 3280 { 3281 if_ctx_t ctx; 3282 if_shared_ctx_t sctx; 3283 if_softc_ctx_t scctx; 3284 bus_dma_segment_t *segs; 3285 struct mbuf *m_head; 3286 void *next_txd; 3287 bus_dmamap_t map; 3288 struct if_pkt_info pi; 3289 int remap = 0; 3290 int err, nsegs, ndesc, max_segs, pidx, cidx, next, ntxd; 3291 bus_dma_tag_t desc_tag; 3292 3293 ctx = txq->ift_ctx; 3294 sctx = ctx->ifc_sctx; 3295 scctx = &ctx->ifc_softc_ctx; 3296 segs = txq->ift_segs; 3297 ntxd = txq->ift_size; 3298 m_head = *m_headp; 3299 map = NULL; 3300 3301 /* 3302 * If we're doing TSO the next descriptor to clean may be quite far ahead 3303 */ 3304 cidx = txq->ift_cidx; 3305 pidx = txq->ift_pidx; 3306 if (ctx->ifc_flags & IFC_PREFETCH) { 3307 next = (cidx + CACHE_PTR_INCREMENT) & (ntxd-1); 3308 if (!(ctx->ifc_flags & IFLIB_HAS_TXCQ)) { 3309 next_txd = calc_next_txd(txq, cidx, 0); 3310 prefetch(next_txd); 3311 } 3312 3313 /* prefetch the next cache line of mbuf pointers and flags */ 3314 prefetch(&txq->ift_sds.ifsd_m[next]); 3315 if (txq->ift_sds.ifsd_map != NULL) { 3316 prefetch(&txq->ift_sds.ifsd_map[next]); 3317 next = (cidx + CACHE_LINE_SIZE) & (ntxd-1); 3318 prefetch(&txq->ift_sds.ifsd_flags[next]); 3319 } 3320 } else if (txq->ift_sds.ifsd_map != NULL) 3321 map = txq->ift_sds.ifsd_map[pidx]; 3322 3323 if (m_head->m_pkthdr.csum_flags & CSUM_TSO) { 3324 desc_tag = txq->ift_tso_desc_tag; 3325 max_segs = scctx->isc_tx_tso_segments_max; 3326 MPASS(desc_tag != NULL); 3327 MPASS(max_segs > 0); 3328 } else { 3329 desc_tag = txq->ift_desc_tag; 3330 max_segs = scctx->isc_tx_nsegments; 3331 } 3332 if ((sctx->isc_flags & IFLIB_NEED_ETHER_PAD) && 3333 __predict_false(m_head->m_pkthdr.len < scctx->isc_min_frame_size)) { 3334 err = iflib_ether_pad(ctx->ifc_dev, m_headp, scctx->isc_min_frame_size); 3335 if (err) { 3336 DBG_COUNTER_INC(encap_txd_encap_fail); 3337 return err; 3338 } 3339 } 3340 m_head = *m_headp; 3341 3342 pkt_info_zero(&pi); 3343 pi.ipi_mflags = (m_head->m_flags & (M_VLANTAG|M_BCAST|M_MCAST)); 3344 pi.ipi_pidx = pidx; 3345 pi.ipi_qsidx = txq->ift_id; 3346 pi.ipi_len = m_head->m_pkthdr.len; 3347 pi.ipi_csum_flags = m_head->m_pkthdr.csum_flags; 3348 pi.ipi_vtag = (m_head->m_flags & M_VLANTAG) ? m_head->m_pkthdr.ether_vtag : 0; 3349 3350 /* deliberate bitwise OR to make one condition */ 3351 if (__predict_true((pi.ipi_csum_flags | pi.ipi_vtag))) { 3352 if (__predict_false((err = iflib_parse_header(txq, &pi, m_headp)) != 0)) { 3353 DBG_COUNTER_INC(encap_txd_encap_fail); 3354 return (err); 3355 } 3356 m_head = *m_headp; 3357 } 3358 3359 retry: 3360 err = iflib_busdma_load_mbuf_sg(txq, desc_tag, map, m_headp, segs, &nsegs, max_segs, BUS_DMA_NOWAIT); 3361 defrag: 3362 if (__predict_false(err)) { 3363 switch (err) { 3364 case EFBIG: 3365 /* try collapse once and defrag once */ 3366 if (remap == 0) { 3367 m_head = m_collapse(*m_headp, M_NOWAIT, max_segs); 3368 /* try defrag if collapsing fails */ 3369 if (m_head == NULL) 3370 remap++; 3371 } 3372 if (remap == 1) { 3373 txq->ift_mbuf_defrag++; 3374 m_head = m_defrag(*m_headp, M_NOWAIT); 3375 } 3376 remap++; 3377 if (__predict_false(m_head == NULL)) 3378 goto defrag_failed; 3379 *m_headp = m_head; 3380 goto retry; 3381 break; 3382 case ENOMEM: 3383 txq->ift_no_tx_dma_setup++; 3384 break; 3385 default: 3386 txq->ift_no_tx_dma_setup++; 3387 m_freem(*m_headp); 3388 DBG_COUNTER_INC(tx_frees); 3389 *m_headp = NULL; 3390 break; 3391 } 3392 txq->ift_map_failed++; 3393 DBG_COUNTER_INC(encap_load_mbuf_fail); 3394 DBG_COUNTER_INC(encap_txd_encap_fail); 3395 return (err); 3396 } 3397 3398 /* 3399 * XXX assumes a 1 to 1 relationship between segments and 3400 * descriptors - this does not hold true on all drivers, e.g. 3401 * cxgb 3402 */ 3403 if (__predict_false(nsegs + 2 > TXQ_AVAIL(txq))) { 3404 txq->ift_no_desc_avail++; 3405 if (map != NULL) 3406 bus_dmamap_unload(desc_tag, map); 3407 DBG_COUNTER_INC(encap_txq_avail_fail); 3408 DBG_COUNTER_INC(encap_txd_encap_fail); 3409 if ((txq->ift_task.gt_task.ta_flags & TASK_ENQUEUED) == 0) 3410 GROUPTASK_ENQUEUE(&txq->ift_task); 3411 return (ENOBUFS); 3412 } 3413 /* 3414 * On Intel cards we can greatly reduce the number of TX interrupts 3415 * we see by only setting report status on every Nth descriptor. 3416 * However, this also means that the driver will need to keep track 3417 * of the descriptors that RS was set on to check them for the DD bit. 3418 */ 3419 txq->ift_rs_pending += nsegs + 1; 3420 if (txq->ift_rs_pending > TXQ_MAX_RS_DEFERRED(txq) || 3421 iflib_no_tx_batch || (TXQ_AVAIL(txq) - nsegs) <= MAX_TX_DESC(ctx) + 2) { 3422 pi.ipi_flags |= IPI_TX_INTR; 3423 txq->ift_rs_pending = 0; 3424 } 3425 3426 pi.ipi_segs = segs; 3427 pi.ipi_nsegs = nsegs; 3428 3429 MPASS(pidx >= 0 && pidx < txq->ift_size); 3430 #ifdef PKT_DEBUG 3431 print_pkt(&pi); 3432 #endif 3433 if (map != NULL) 3434 bus_dmamap_sync(desc_tag, map, BUS_DMASYNC_PREWRITE); 3435 if ((err = ctx->isc_txd_encap(ctx->ifc_softc, &pi)) == 0) { 3436 if (map != NULL) 3437 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 3438 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3439 DBG_COUNTER_INC(tx_encap); 3440 MPASS(pi.ipi_new_pidx < txq->ift_size); 3441 3442 ndesc = pi.ipi_new_pidx - pi.ipi_pidx; 3443 if (pi.ipi_new_pidx < pi.ipi_pidx) { 3444 ndesc += txq->ift_size; 3445 txq->ift_gen = 1; 3446 } 3447 /* 3448 * drivers can need as many as 3449 * two sentinels 3450 */ 3451 MPASS(ndesc <= pi.ipi_nsegs + 2); 3452 MPASS(pi.ipi_new_pidx != pidx); 3453 MPASS(ndesc > 0); 3454 txq->ift_in_use += ndesc; 3455 3456 /* 3457 * We update the last software descriptor again here because there may 3458 * be a sentinel and/or there may be more mbufs than segments 3459 */ 3460 txq->ift_pidx = pi.ipi_new_pidx; 3461 txq->ift_npending += pi.ipi_ndescs; 3462 } else { 3463 *m_headp = m_head = iflib_remove_mbuf(txq); 3464 if (err == EFBIG) { 3465 txq->ift_txd_encap_efbig++; 3466 if (remap < 2) { 3467 remap = 1; 3468 goto defrag; 3469 } 3470 } 3471 goto defrag_failed; 3472 } 3473 /* 3474 * err can't possibly be non-zero here, so we don't neet to test it 3475 * to see if we need to DBG_COUNTER_INC(encap_txd_encap_fail). 3476 */ 3477 return (err); 3478 3479 defrag_failed: 3480 txq->ift_mbuf_defrag_failed++; 3481 txq->ift_map_failed++; 3482 m_freem(*m_headp); 3483 DBG_COUNTER_INC(tx_frees); 3484 *m_headp = NULL; 3485 DBG_COUNTER_INC(encap_txd_encap_fail); 3486 return (ENOMEM); 3487 } 3488 3489 static void 3490 iflib_tx_desc_free(iflib_txq_t txq, int n) 3491 { 3492 int hasmap; 3493 uint32_t qsize, cidx, mask, gen; 3494 struct mbuf *m, **ifsd_m; 3495 uint8_t *ifsd_flags; 3496 bus_dmamap_t *ifsd_map; 3497 bool do_prefetch; 3498 3499 cidx = txq->ift_cidx; 3500 gen = txq->ift_gen; 3501 qsize = txq->ift_size; 3502 mask = qsize-1; 3503 hasmap = txq->ift_sds.ifsd_map != NULL; 3504 ifsd_flags = txq->ift_sds.ifsd_flags; 3505 ifsd_m = txq->ift_sds.ifsd_m; 3506 ifsd_map = txq->ift_sds.ifsd_map; 3507 do_prefetch = (txq->ift_ctx->ifc_flags & IFC_PREFETCH); 3508 3509 while (n-- > 0) { 3510 if (do_prefetch) { 3511 prefetch(ifsd_m[(cidx + 3) & mask]); 3512 prefetch(ifsd_m[(cidx + 4) & mask]); 3513 } 3514 if (ifsd_m[cidx] != NULL) { 3515 prefetch(&ifsd_m[(cidx + CACHE_PTR_INCREMENT) & mask]); 3516 prefetch(&ifsd_flags[(cidx + CACHE_PTR_INCREMENT) & mask]); 3517 if (hasmap && (ifsd_flags[cidx] & TX_SW_DESC_MAPPED)) { 3518 /* 3519 * does it matter if it's not the TSO tag? If so we'll 3520 * have to add the type to flags 3521 */ 3522 bus_dmamap_unload(txq->ift_desc_tag, ifsd_map[cidx]); 3523 ifsd_flags[cidx] &= ~TX_SW_DESC_MAPPED; 3524 } 3525 if ((m = ifsd_m[cidx]) != NULL) { 3526 /* XXX we don't support any drivers that batch packets yet */ 3527 MPASS(m->m_nextpkt == NULL); 3528 /* if the number of clusters exceeds the number of segments 3529 * there won't be space on the ring to save a pointer to each 3530 * cluster so we simply free the list here 3531 */ 3532 if (m->m_flags & M_TOOBIG) { 3533 m_freem(m); 3534 } else { 3535 m_free(m); 3536 } 3537 ifsd_m[cidx] = NULL; 3538 #if MEMORY_LOGGING 3539 txq->ift_dequeued++; 3540 #endif 3541 DBG_COUNTER_INC(tx_frees); 3542 } 3543 } 3544 if (__predict_false(++cidx == qsize)) { 3545 cidx = 0; 3546 gen = 0; 3547 } 3548 } 3549 txq->ift_cidx = cidx; 3550 txq->ift_gen = gen; 3551 } 3552 3553 static __inline int 3554 iflib_completed_tx_reclaim(iflib_txq_t txq, int thresh) 3555 { 3556 int reclaim; 3557 if_ctx_t ctx = txq->ift_ctx; 3558 3559 KASSERT(thresh >= 0, ("invalid threshold to reclaim")); 3560 MPASS(thresh /*+ MAX_TX_DESC(txq->ift_ctx) */ < txq->ift_size); 3561 3562 /* 3563 * Need a rate-limiting check so that this isn't called every time 3564 */ 3565 iflib_tx_credits_update(ctx, txq); 3566 reclaim = DESC_RECLAIMABLE(txq); 3567 3568 if (reclaim <= thresh /* + MAX_TX_DESC(txq->ift_ctx) */) { 3569 #ifdef INVARIANTS 3570 if (iflib_verbose_debug) { 3571 printf("%s processed=%ju cleaned=%ju tx_nsegments=%d reclaim=%d thresh=%d\n", __FUNCTION__, 3572 txq->ift_processed, txq->ift_cleaned, txq->ift_ctx->ifc_softc_ctx.isc_tx_nsegments, 3573 reclaim, thresh); 3574 3575 } 3576 #endif 3577 return (0); 3578 } 3579 iflib_tx_desc_free(txq, reclaim); 3580 txq->ift_cleaned += reclaim; 3581 txq->ift_in_use -= reclaim; 3582 3583 return (reclaim); 3584 } 3585 3586 static struct mbuf ** 3587 _ring_peek_one(struct ifmp_ring *r, int cidx, int offset, int remaining) 3588 { 3589 int next, size; 3590 struct mbuf **items; 3591 3592 size = r->size; 3593 next = (cidx + CACHE_PTR_INCREMENT) & (size-1); 3594 items = __DEVOLATILE(struct mbuf **, &r->items[0]); 3595 3596 prefetch(items[(cidx + offset) & (size-1)]); 3597 if (remaining > 1) { 3598 prefetch2cachelines(&items[next]); 3599 prefetch2cachelines(items[(cidx + offset + 1) & (size-1)]); 3600 prefetch2cachelines(items[(cidx + offset + 2) & (size-1)]); 3601 prefetch2cachelines(items[(cidx + offset + 3) & (size-1)]); 3602 } 3603 return (__DEVOLATILE(struct mbuf **, &r->items[(cidx + offset) & (size-1)])); 3604 } 3605 3606 static void 3607 iflib_txq_check_drain(iflib_txq_t txq, int budget) 3608 { 3609 3610 ifmp_ring_check_drainage(txq->ift_br, budget); 3611 } 3612 3613 static uint32_t 3614 iflib_txq_can_drain(struct ifmp_ring *r) 3615 { 3616 iflib_txq_t txq = r->cookie; 3617 if_ctx_t ctx = txq->ift_ctx; 3618 3619 return ((TXQ_AVAIL(txq) > MAX_TX_DESC(ctx) + 2) || 3620 ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, false)); 3621 } 3622 3623 static uint32_t 3624 iflib_txq_drain(struct ifmp_ring *r, uint32_t cidx, uint32_t pidx) 3625 { 3626 iflib_txq_t txq = r->cookie; 3627 if_ctx_t ctx = txq->ift_ctx; 3628 struct ifnet *ifp = ctx->ifc_ifp; 3629 struct mbuf **mp, *m; 3630 int i, count, consumed, pkt_sent, bytes_sent, mcast_sent, avail; 3631 int reclaimed, err, in_use_prev, desc_used; 3632 bool do_prefetch, ring, rang; 3633 3634 if (__predict_false(!(if_getdrvflags(ifp) & IFF_DRV_RUNNING) || 3635 !LINK_ACTIVE(ctx))) { 3636 DBG_COUNTER_INC(txq_drain_notready); 3637 return (0); 3638 } 3639 reclaimed = iflib_completed_tx_reclaim(txq, RECLAIM_THRESH(ctx)); 3640 rang = iflib_txd_db_check(ctx, txq, reclaimed, txq->ift_in_use); 3641 avail = IDXDIFF(pidx, cidx, r->size); 3642 if (__predict_false(ctx->ifc_flags & IFC_QFLUSH)) { 3643 DBG_COUNTER_INC(txq_drain_flushing); 3644 for (i = 0; i < avail; i++) { 3645 if (__predict_true(r->items[(cidx + i) & (r->size-1)] != (void *)txq)) 3646 m_free(r->items[(cidx + i) & (r->size-1)]); 3647 r->items[(cidx + i) & (r->size-1)] = NULL; 3648 } 3649 return (avail); 3650 } 3651 3652 if (__predict_false(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_OACTIVE)) { 3653 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 3654 CALLOUT_LOCK(txq); 3655 callout_stop(&txq->ift_timer); 3656 CALLOUT_UNLOCK(txq); 3657 DBG_COUNTER_INC(txq_drain_oactive); 3658 return (0); 3659 } 3660 if (reclaimed) 3661 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 3662 consumed = mcast_sent = bytes_sent = pkt_sent = 0; 3663 count = MIN(avail, TX_BATCH_SIZE); 3664 #ifdef INVARIANTS 3665 if (iflib_verbose_debug) 3666 printf("%s avail=%d ifc_flags=%x txq_avail=%d ", __FUNCTION__, 3667 avail, ctx->ifc_flags, TXQ_AVAIL(txq)); 3668 #endif 3669 do_prefetch = (ctx->ifc_flags & IFC_PREFETCH); 3670 avail = TXQ_AVAIL(txq); 3671 err = 0; 3672 for (desc_used = i = 0; i < count && avail > MAX_TX_DESC(ctx) + 2; i++) { 3673 int rem = do_prefetch ? count - i : 0; 3674 3675 mp = _ring_peek_one(r, cidx, i, rem); 3676 MPASS(mp != NULL && *mp != NULL); 3677 if (__predict_false(*mp == (struct mbuf *)txq)) { 3678 consumed++; 3679 reclaimed++; 3680 continue; 3681 } 3682 in_use_prev = txq->ift_in_use; 3683 err = iflib_encap(txq, mp); 3684 if (__predict_false(err)) { 3685 /* no room - bail out */ 3686 if (err == ENOBUFS) 3687 break; 3688 consumed++; 3689 /* we can't send this packet - skip it */ 3690 continue; 3691 } 3692 consumed++; 3693 pkt_sent++; 3694 m = *mp; 3695 DBG_COUNTER_INC(tx_sent); 3696 bytes_sent += m->m_pkthdr.len; 3697 mcast_sent += !!(m->m_flags & M_MCAST); 3698 avail = TXQ_AVAIL(txq); 3699 3700 txq->ift_db_pending += (txq->ift_in_use - in_use_prev); 3701 desc_used += (txq->ift_in_use - in_use_prev); 3702 ETHER_BPF_MTAP(ifp, m); 3703 if (__predict_false(!(ifp->if_drv_flags & IFF_DRV_RUNNING))) 3704 break; 3705 rang = iflib_txd_db_check(ctx, txq, false, in_use_prev); 3706 } 3707 3708 /* deliberate use of bitwise or to avoid gratuitous short-circuit */ 3709 ring = rang ? false : (iflib_min_tx_latency | err) || (TXQ_AVAIL(txq) < MAX_TX_DESC(ctx)); 3710 iflib_txd_db_check(ctx, txq, ring, txq->ift_in_use); 3711 if_inc_counter(ifp, IFCOUNTER_OBYTES, bytes_sent); 3712 if_inc_counter(ifp, IFCOUNTER_OPACKETS, pkt_sent); 3713 if (mcast_sent) 3714 if_inc_counter(ifp, IFCOUNTER_OMCASTS, mcast_sent); 3715 #ifdef INVARIANTS 3716 if (iflib_verbose_debug) 3717 printf("consumed=%d\n", consumed); 3718 #endif 3719 return (consumed); 3720 } 3721 3722 static uint32_t 3723 iflib_txq_drain_always(struct ifmp_ring *r) 3724 { 3725 return (1); 3726 } 3727 3728 static uint32_t 3729 iflib_txq_drain_free(struct ifmp_ring *r, uint32_t cidx, uint32_t pidx) 3730 { 3731 int i, avail; 3732 struct mbuf **mp; 3733 iflib_txq_t txq; 3734 3735 txq = r->cookie; 3736 3737 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 3738 CALLOUT_LOCK(txq); 3739 callout_stop(&txq->ift_timer); 3740 CALLOUT_UNLOCK(txq); 3741 3742 avail = IDXDIFF(pidx, cidx, r->size); 3743 for (i = 0; i < avail; i++) { 3744 mp = _ring_peek_one(r, cidx, i, avail - i); 3745 if (__predict_false(*mp == (struct mbuf *)txq)) 3746 continue; 3747 m_freem(*mp); 3748 DBG_COUNTER_INC(tx_frees); 3749 } 3750 MPASS(ifmp_ring_is_stalled(r) == 0); 3751 return (avail); 3752 } 3753 3754 static void 3755 iflib_ifmp_purge(iflib_txq_t txq) 3756 { 3757 struct ifmp_ring *r; 3758 3759 r = txq->ift_br; 3760 r->drain = iflib_txq_drain_free; 3761 r->can_drain = iflib_txq_drain_always; 3762 3763 ifmp_ring_check_drainage(r, r->size); 3764 3765 r->drain = iflib_txq_drain; 3766 r->can_drain = iflib_txq_can_drain; 3767 } 3768 3769 static void 3770 _task_fn_tx(void *context) 3771 { 3772 iflib_txq_t txq = context; 3773 if_ctx_t ctx = txq->ift_ctx; 3774 struct ifnet *ifp = ctx->ifc_ifp; 3775 int abdicate = ctx->ifc_sysctl_tx_abdicate; 3776 3777 #ifdef IFLIB_DIAGNOSTICS 3778 txq->ift_cpu_exec_count[curcpu]++; 3779 #endif 3780 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)) 3781 return; 3782 if (if_getcapenable(ifp) & IFCAP_NETMAP) { 3783 if (ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, false)) 3784 netmap_tx_irq(ifp, txq->ift_id); 3785 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txq->ift_id); 3786 return; 3787 } 3788 #ifdef ALTQ 3789 if (ALTQ_IS_ENABLED(&ifp->if_snd)) 3790 iflib_altq_if_start(ifp); 3791 #endif 3792 if (txq->ift_db_pending) 3793 ifmp_ring_enqueue(txq->ift_br, (void **)&txq, 1, TX_BATCH_SIZE, abdicate); 3794 else if (!abdicate) 3795 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE); 3796 /* 3797 * When abdicating, we always need to check drainage, not just when we don't enqueue 3798 */ 3799 if (abdicate) 3800 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE); 3801 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE); 3802 if (ctx->ifc_flags & IFC_LEGACY) 3803 IFDI_INTR_ENABLE(ctx); 3804 else { 3805 #ifdef INVARIANTS 3806 int rc = 3807 #endif 3808 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txq->ift_id); 3809 KASSERT(rc != ENOTSUP, ("MSI-X support requires queue_intr_enable, but not implemented in driver")); 3810 } 3811 } 3812 3813 static void 3814 _task_fn_rx(void *context) 3815 { 3816 iflib_rxq_t rxq = context; 3817 if_ctx_t ctx = rxq->ifr_ctx; 3818 bool more; 3819 uint16_t budget; 3820 3821 #ifdef IFLIB_DIAGNOSTICS 3822 rxq->ifr_cpu_exec_count[curcpu]++; 3823 #endif 3824 DBG_COUNTER_INC(task_fn_rxs); 3825 if (__predict_false(!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING))) 3826 return; 3827 more = true; 3828 #ifdef DEV_NETMAP 3829 if (if_getcapenable(ctx->ifc_ifp) & IFCAP_NETMAP) { 3830 u_int work = 0; 3831 if (netmap_rx_irq(ctx->ifc_ifp, rxq->ifr_id, &work)) { 3832 more = false; 3833 } 3834 } 3835 #endif 3836 budget = ctx->ifc_sysctl_rx_budget; 3837 if (budget == 0) 3838 budget = 16; /* XXX */ 3839 if (more == false || (more = iflib_rxeof(rxq, budget)) == false) { 3840 if (ctx->ifc_flags & IFC_LEGACY) 3841 IFDI_INTR_ENABLE(ctx); 3842 else { 3843 #ifdef INVARIANTS 3844 int rc = 3845 #endif 3846 IFDI_RX_QUEUE_INTR_ENABLE(ctx, rxq->ifr_id); 3847 KASSERT(rc != ENOTSUP, ("MSI-X support requires queue_intr_enable, but not implemented in driver")); 3848 DBG_COUNTER_INC(rx_intr_enables); 3849 } 3850 } 3851 if (__predict_false(!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING))) 3852 return; 3853 if (more) 3854 GROUPTASK_ENQUEUE(&rxq->ifr_task); 3855 } 3856 3857 static void 3858 _task_fn_admin(void *context) 3859 { 3860 if_ctx_t ctx = context; 3861 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 3862 iflib_txq_t txq; 3863 int i; 3864 bool oactive, running, do_reset, do_watchdog, in_detach; 3865 uint32_t reset_on = hz / 2; 3866 3867 STATE_LOCK(ctx); 3868 running = (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING); 3869 oactive = (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_OACTIVE); 3870 do_reset = (ctx->ifc_flags & IFC_DO_RESET); 3871 do_watchdog = (ctx->ifc_flags & IFC_DO_WATCHDOG); 3872 in_detach = (ctx->ifc_flags & IFC_IN_DETACH); 3873 ctx->ifc_flags &= ~(IFC_DO_RESET|IFC_DO_WATCHDOG); 3874 STATE_UNLOCK(ctx); 3875 3876 if ((!running && !oactive) && !(ctx->ifc_sctx->isc_flags & IFLIB_ADMIN_ALWAYS_RUN)) 3877 return; 3878 if (in_detach) 3879 return; 3880 3881 CTX_LOCK(ctx); 3882 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) { 3883 CALLOUT_LOCK(txq); 3884 callout_stop(&txq->ift_timer); 3885 CALLOUT_UNLOCK(txq); 3886 } 3887 if (do_watchdog) { 3888 ctx->ifc_watchdog_events++; 3889 IFDI_WATCHDOG_RESET(ctx); 3890 } 3891 IFDI_UPDATE_ADMIN_STATUS(ctx); 3892 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) { 3893 #ifdef DEV_NETMAP 3894 reset_on = hz / 2; 3895 if (if_getcapenable(ctx->ifc_ifp) & IFCAP_NETMAP) 3896 iflib_netmap_timer_adjust(ctx, txq->ift_id, &reset_on); 3897 #endif 3898 callout_reset_on(&txq->ift_timer, reset_on, iflib_timer, txq, txq->ift_timer.c_cpu); 3899 } 3900 IFDI_LINK_INTR_ENABLE(ctx); 3901 if (do_reset) 3902 iflib_if_init_locked(ctx); 3903 CTX_UNLOCK(ctx); 3904 3905 if (LINK_ACTIVE(ctx) == 0) 3906 return; 3907 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) 3908 iflib_txq_check_drain(txq, IFLIB_RESTART_BUDGET); 3909 } 3910 3911 3912 static void 3913 _task_fn_iov(void *context) 3914 { 3915 if_ctx_t ctx = context; 3916 3917 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING) && 3918 !(ctx->ifc_sctx->isc_flags & IFLIB_ADMIN_ALWAYS_RUN)) 3919 return; 3920 3921 CTX_LOCK(ctx); 3922 IFDI_VFLR_HANDLE(ctx); 3923 CTX_UNLOCK(ctx); 3924 } 3925 3926 static int 3927 iflib_sysctl_int_delay(SYSCTL_HANDLER_ARGS) 3928 { 3929 int err; 3930 if_int_delay_info_t info; 3931 if_ctx_t ctx; 3932 3933 info = (if_int_delay_info_t)arg1; 3934 ctx = info->iidi_ctx; 3935 info->iidi_req = req; 3936 info->iidi_oidp = oidp; 3937 CTX_LOCK(ctx); 3938 err = IFDI_SYSCTL_INT_DELAY(ctx, info); 3939 CTX_UNLOCK(ctx); 3940 return (err); 3941 } 3942 3943 /********************************************************************* 3944 * 3945 * IFNET FUNCTIONS 3946 * 3947 **********************************************************************/ 3948 3949 static void 3950 iflib_if_init_locked(if_ctx_t ctx) 3951 { 3952 iflib_stop(ctx); 3953 iflib_init_locked(ctx); 3954 } 3955 3956 3957 static void 3958 iflib_if_init(void *arg) 3959 { 3960 if_ctx_t ctx = arg; 3961 3962 CTX_LOCK(ctx); 3963 iflib_if_init_locked(ctx); 3964 CTX_UNLOCK(ctx); 3965 } 3966 3967 static int 3968 iflib_if_transmit(if_t ifp, struct mbuf *m) 3969 { 3970 if_ctx_t ctx = if_getsoftc(ifp); 3971 3972 iflib_txq_t txq; 3973 int err, qidx; 3974 int abdicate = ctx->ifc_sysctl_tx_abdicate; 3975 3976 if (__predict_false((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0 || !LINK_ACTIVE(ctx))) { 3977 DBG_COUNTER_INC(tx_frees); 3978 m_freem(m); 3979 return (ENOBUFS); 3980 } 3981 3982 MPASS(m->m_nextpkt == NULL); 3983 /* ALTQ-enabled interfaces always use queue 0. */ 3984 qidx = 0; 3985 if ((NTXQSETS(ctx) > 1) && M_HASHTYPE_GET(m) && !ALTQ_IS_ENABLED(&ifp->if_snd)) 3986 qidx = QIDX(ctx, m); 3987 /* 3988 * XXX calculate buf_ring based on flowid (divvy up bits?) 3989 */ 3990 txq = &ctx->ifc_txqs[qidx]; 3991 3992 #ifdef DRIVER_BACKPRESSURE 3993 if (txq->ift_closed) { 3994 while (m != NULL) { 3995 next = m->m_nextpkt; 3996 m->m_nextpkt = NULL; 3997 m_freem(m); 3998 DBG_COUNTER_INC(tx_frees); 3999 m = next; 4000 } 4001 return (ENOBUFS); 4002 } 4003 #endif 4004 #ifdef notyet 4005 qidx = count = 0; 4006 mp = marr; 4007 next = m; 4008 do { 4009 count++; 4010 next = next->m_nextpkt; 4011 } while (next != NULL); 4012 4013 if (count > nitems(marr)) 4014 if ((mp = malloc(count*sizeof(struct mbuf *), M_IFLIB, M_NOWAIT)) == NULL) { 4015 /* XXX check nextpkt */ 4016 m_freem(m); 4017 /* XXX simplify for now */ 4018 DBG_COUNTER_INC(tx_frees); 4019 return (ENOBUFS); 4020 } 4021 for (next = m, i = 0; next != NULL; i++) { 4022 mp[i] = next; 4023 next = next->m_nextpkt; 4024 mp[i]->m_nextpkt = NULL; 4025 } 4026 #endif 4027 DBG_COUNTER_INC(tx_seen); 4028 err = ifmp_ring_enqueue(txq->ift_br, (void **)&m, 1, TX_BATCH_SIZE, abdicate); 4029 4030 if (abdicate) 4031 GROUPTASK_ENQUEUE(&txq->ift_task); 4032 if (err) { 4033 if (!abdicate) 4034 GROUPTASK_ENQUEUE(&txq->ift_task); 4035 /* support forthcoming later */ 4036 #ifdef DRIVER_BACKPRESSURE 4037 txq->ift_closed = TRUE; 4038 #endif 4039 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE); 4040 m_freem(m); 4041 DBG_COUNTER_INC(tx_frees); 4042 } 4043 4044 return (err); 4045 } 4046 4047 #ifdef ALTQ 4048 /* 4049 * The overall approach to integrating iflib with ALTQ is to continue to use 4050 * the iflib mp_ring machinery between the ALTQ queue(s) and the hardware 4051 * ring. Technically, when using ALTQ, queueing to an intermediate mp_ring 4052 * is redundant/unnecessary, but doing so minimizes the amount of 4053 * ALTQ-specific code required in iflib. It is assumed that the overhead of 4054 * redundantly queueing to an intermediate mp_ring is swamped by the 4055 * performance limitations inherent in using ALTQ. 4056 * 4057 * When ALTQ support is compiled in, all iflib drivers will use a transmit 4058 * routine, iflib_altq_if_transmit(), that checks if ALTQ is enabled for the 4059 * given interface. If ALTQ is enabled for an interface, then all 4060 * transmitted packets for that interface will be submitted to the ALTQ 4061 * subsystem via IFQ_ENQUEUE(). We don't use the legacy if_transmit() 4062 * implementation because it uses IFQ_HANDOFF(), which will duplicatively 4063 * update stats that the iflib machinery handles, and which is sensitve to 4064 * the disused IFF_DRV_OACTIVE flag. Additionally, iflib_altq_if_start() 4065 * will be installed as the start routine for use by ALTQ facilities that 4066 * need to trigger queue drains on a scheduled basis. 4067 * 4068 */ 4069 static void 4070 iflib_altq_if_start(if_t ifp) 4071 { 4072 struct ifaltq *ifq = &ifp->if_snd; 4073 struct mbuf *m; 4074 4075 IFQ_LOCK(ifq); 4076 IFQ_DEQUEUE_NOLOCK(ifq, m); 4077 while (m != NULL) { 4078 iflib_if_transmit(ifp, m); 4079 IFQ_DEQUEUE_NOLOCK(ifq, m); 4080 } 4081 IFQ_UNLOCK(ifq); 4082 } 4083 4084 static int 4085 iflib_altq_if_transmit(if_t ifp, struct mbuf *m) 4086 { 4087 int err; 4088 4089 if (ALTQ_IS_ENABLED(&ifp->if_snd)) { 4090 IFQ_ENQUEUE(&ifp->if_snd, m, err); 4091 if (err == 0) 4092 iflib_altq_if_start(ifp); 4093 } else 4094 err = iflib_if_transmit(ifp, m); 4095 4096 return (err); 4097 } 4098 #endif /* ALTQ */ 4099 4100 static void 4101 iflib_if_qflush(if_t ifp) 4102 { 4103 if_ctx_t ctx = if_getsoftc(ifp); 4104 iflib_txq_t txq = ctx->ifc_txqs; 4105 int i; 4106 4107 STATE_LOCK(ctx); 4108 ctx->ifc_flags |= IFC_QFLUSH; 4109 STATE_UNLOCK(ctx); 4110 for (i = 0; i < NTXQSETS(ctx); i++, txq++) 4111 while (!(ifmp_ring_is_idle(txq->ift_br) || ifmp_ring_is_stalled(txq->ift_br))) 4112 iflib_txq_check_drain(txq, 0); 4113 STATE_LOCK(ctx); 4114 ctx->ifc_flags &= ~IFC_QFLUSH; 4115 STATE_UNLOCK(ctx); 4116 4117 /* 4118 * When ALTQ is enabled, this will also take care of purging the 4119 * ALTQ queue(s). 4120 */ 4121 if_qflush(ifp); 4122 } 4123 4124 4125 #define IFCAP_FLAGS (IFCAP_HWCSUM_IPV6 | IFCAP_HWCSUM | IFCAP_LRO | \ 4126 IFCAP_TSO | IFCAP_VLAN_HWTAGGING | IFCAP_HWSTATS | \ 4127 IFCAP_VLAN_MTU | IFCAP_VLAN_HWFILTER | \ 4128 IFCAP_VLAN_HWTSO | IFCAP_VLAN_HWCSUM) 4129 4130 static int 4131 iflib_if_ioctl(if_t ifp, u_long command, caddr_t data) 4132 { 4133 if_ctx_t ctx = if_getsoftc(ifp); 4134 struct ifreq *ifr = (struct ifreq *)data; 4135 #if defined(INET) || defined(INET6) 4136 struct ifaddr *ifa = (struct ifaddr *)data; 4137 #endif 4138 bool avoid_reset = FALSE; 4139 int err = 0, reinit = 0, bits; 4140 4141 switch (command) { 4142 case SIOCSIFADDR: 4143 #ifdef INET 4144 if (ifa->ifa_addr->sa_family == AF_INET) 4145 avoid_reset = TRUE; 4146 #endif 4147 #ifdef INET6 4148 if (ifa->ifa_addr->sa_family == AF_INET6) 4149 avoid_reset = TRUE; 4150 #endif 4151 /* 4152 ** Calling init results in link renegotiation, 4153 ** so we avoid doing it when possible. 4154 */ 4155 if (avoid_reset) { 4156 if_setflagbits(ifp, IFF_UP,0); 4157 if (!(if_getdrvflags(ifp) & IFF_DRV_RUNNING)) 4158 reinit = 1; 4159 #ifdef INET 4160 if (!(if_getflags(ifp) & IFF_NOARP)) 4161 arp_ifinit(ifp, ifa); 4162 #endif 4163 } else 4164 err = ether_ioctl(ifp, command, data); 4165 break; 4166 case SIOCSIFMTU: 4167 CTX_LOCK(ctx); 4168 if (ifr->ifr_mtu == if_getmtu(ifp)) { 4169 CTX_UNLOCK(ctx); 4170 break; 4171 } 4172 bits = if_getdrvflags(ifp); 4173 /* stop the driver and free any clusters before proceeding */ 4174 iflib_stop(ctx); 4175 4176 if ((err = IFDI_MTU_SET(ctx, ifr->ifr_mtu)) == 0) { 4177 STATE_LOCK(ctx); 4178 if (ifr->ifr_mtu > ctx->ifc_max_fl_buf_size) 4179 ctx->ifc_flags |= IFC_MULTISEG; 4180 else 4181 ctx->ifc_flags &= ~IFC_MULTISEG; 4182 STATE_UNLOCK(ctx); 4183 err = if_setmtu(ifp, ifr->ifr_mtu); 4184 } 4185 iflib_init_locked(ctx); 4186 STATE_LOCK(ctx); 4187 if_setdrvflags(ifp, bits); 4188 STATE_UNLOCK(ctx); 4189 CTX_UNLOCK(ctx); 4190 break; 4191 case SIOCSIFFLAGS: 4192 CTX_LOCK(ctx); 4193 if (if_getflags(ifp) & IFF_UP) { 4194 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 4195 if ((if_getflags(ifp) ^ ctx->ifc_if_flags) & 4196 (IFF_PROMISC | IFF_ALLMULTI)) { 4197 err = IFDI_PROMISC_SET(ctx, if_getflags(ifp)); 4198 } 4199 } else 4200 reinit = 1; 4201 } else if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 4202 iflib_stop(ctx); 4203 } 4204 ctx->ifc_if_flags = if_getflags(ifp); 4205 CTX_UNLOCK(ctx); 4206 break; 4207 case SIOCADDMULTI: 4208 case SIOCDELMULTI: 4209 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 4210 CTX_LOCK(ctx); 4211 IFDI_INTR_DISABLE(ctx); 4212 IFDI_MULTI_SET(ctx); 4213 IFDI_INTR_ENABLE(ctx); 4214 CTX_UNLOCK(ctx); 4215 } 4216 break; 4217 case SIOCSIFMEDIA: 4218 CTX_LOCK(ctx); 4219 IFDI_MEDIA_SET(ctx); 4220 CTX_UNLOCK(ctx); 4221 /* falls thru */ 4222 case SIOCGIFMEDIA: 4223 case SIOCGIFXMEDIA: 4224 err = ifmedia_ioctl(ifp, ifr, &ctx->ifc_media, command); 4225 break; 4226 case SIOCGI2C: 4227 { 4228 struct ifi2creq i2c; 4229 4230 err = copyin(ifr_data_get_ptr(ifr), &i2c, sizeof(i2c)); 4231 if (err != 0) 4232 break; 4233 if (i2c.dev_addr != 0xA0 && i2c.dev_addr != 0xA2) { 4234 err = EINVAL; 4235 break; 4236 } 4237 if (i2c.len > sizeof(i2c.data)) { 4238 err = EINVAL; 4239 break; 4240 } 4241 4242 if ((err = IFDI_I2C_REQ(ctx, &i2c)) == 0) 4243 err = copyout(&i2c, ifr_data_get_ptr(ifr), 4244 sizeof(i2c)); 4245 break; 4246 } 4247 case SIOCSIFCAP: 4248 { 4249 int mask, setmask, oldmask; 4250 4251 oldmask = if_getcapenable(ifp); 4252 mask = ifr->ifr_reqcap ^ oldmask; 4253 mask &= ctx->ifc_softc_ctx.isc_capabilities; 4254 setmask = 0; 4255 #ifdef TCP_OFFLOAD 4256 setmask |= mask & (IFCAP_TOE4|IFCAP_TOE6); 4257 #endif 4258 setmask |= (mask & IFCAP_FLAGS); 4259 setmask |= (mask & IFCAP_WOL); 4260 4261 /* 4262 * If any RX csum has changed, change all the ones that 4263 * are supported by the driver. 4264 */ 4265 if (setmask & (IFCAP_RXCSUM | IFCAP_RXCSUM_IPV6)) { 4266 setmask |= ctx->ifc_softc_ctx.isc_capabilities & 4267 (IFCAP_RXCSUM | IFCAP_RXCSUM_IPV6); 4268 } 4269 4270 /* 4271 * want to ensure that traffic has stopped before we change any of the flags 4272 */ 4273 if (setmask) { 4274 CTX_LOCK(ctx); 4275 bits = if_getdrvflags(ifp); 4276 if (bits & IFF_DRV_RUNNING && setmask & ~IFCAP_WOL) 4277 iflib_stop(ctx); 4278 STATE_LOCK(ctx); 4279 if_togglecapenable(ifp, setmask); 4280 STATE_UNLOCK(ctx); 4281 if (bits & IFF_DRV_RUNNING && setmask & ~IFCAP_WOL) 4282 iflib_init_locked(ctx); 4283 STATE_LOCK(ctx); 4284 if_setdrvflags(ifp, bits); 4285 STATE_UNLOCK(ctx); 4286 CTX_UNLOCK(ctx); 4287 } 4288 if_vlancap(ifp); 4289 break; 4290 } 4291 case SIOCGPRIVATE_0: 4292 case SIOCSDRVSPEC: 4293 case SIOCGDRVSPEC: 4294 CTX_LOCK(ctx); 4295 err = IFDI_PRIV_IOCTL(ctx, command, data); 4296 CTX_UNLOCK(ctx); 4297 break; 4298 default: 4299 err = ether_ioctl(ifp, command, data); 4300 break; 4301 } 4302 if (reinit) 4303 iflib_if_init(ctx); 4304 return (err); 4305 } 4306 4307 static uint64_t 4308 iflib_if_get_counter(if_t ifp, ift_counter cnt) 4309 { 4310 if_ctx_t ctx = if_getsoftc(ifp); 4311 4312 return (IFDI_GET_COUNTER(ctx, cnt)); 4313 } 4314 4315 /********************************************************************* 4316 * 4317 * OTHER FUNCTIONS EXPORTED TO THE STACK 4318 * 4319 **********************************************************************/ 4320 4321 static void 4322 iflib_vlan_register(void *arg, if_t ifp, uint16_t vtag) 4323 { 4324 if_ctx_t ctx = if_getsoftc(ifp); 4325 4326 if ((void *)ctx != arg) 4327 return; 4328 4329 if ((vtag == 0) || (vtag > 4095)) 4330 return; 4331 4332 CTX_LOCK(ctx); 4333 IFDI_VLAN_REGISTER(ctx, vtag); 4334 /* Re-init to load the changes */ 4335 if (if_getcapenable(ifp) & IFCAP_VLAN_HWFILTER) 4336 iflib_if_init_locked(ctx); 4337 CTX_UNLOCK(ctx); 4338 } 4339 4340 static void 4341 iflib_vlan_unregister(void *arg, if_t ifp, uint16_t vtag) 4342 { 4343 if_ctx_t ctx = if_getsoftc(ifp); 4344 4345 if ((void *)ctx != arg) 4346 return; 4347 4348 if ((vtag == 0) || (vtag > 4095)) 4349 return; 4350 4351 CTX_LOCK(ctx); 4352 IFDI_VLAN_UNREGISTER(ctx, vtag); 4353 /* Re-init to load the changes */ 4354 if (if_getcapenable(ifp) & IFCAP_VLAN_HWFILTER) 4355 iflib_if_init_locked(ctx); 4356 CTX_UNLOCK(ctx); 4357 } 4358 4359 static void 4360 iflib_led_func(void *arg, int onoff) 4361 { 4362 if_ctx_t ctx = arg; 4363 4364 CTX_LOCK(ctx); 4365 IFDI_LED_FUNC(ctx, onoff); 4366 CTX_UNLOCK(ctx); 4367 } 4368 4369 /********************************************************************* 4370 * 4371 * BUS FUNCTION DEFINITIONS 4372 * 4373 **********************************************************************/ 4374 4375 int 4376 iflib_device_probe(device_t dev) 4377 { 4378 pci_vendor_info_t *ent; 4379 4380 uint16_t pci_vendor_id, pci_device_id; 4381 uint16_t pci_subvendor_id, pci_subdevice_id; 4382 uint16_t pci_rev_id; 4383 if_shared_ctx_t sctx; 4384 4385 if ((sctx = DEVICE_REGISTER(dev)) == NULL || sctx->isc_magic != IFLIB_MAGIC) 4386 return (ENOTSUP); 4387 4388 pci_vendor_id = pci_get_vendor(dev); 4389 pci_device_id = pci_get_device(dev); 4390 pci_subvendor_id = pci_get_subvendor(dev); 4391 pci_subdevice_id = pci_get_subdevice(dev); 4392 pci_rev_id = pci_get_revid(dev); 4393 if (sctx->isc_parse_devinfo != NULL) 4394 sctx->isc_parse_devinfo(&pci_device_id, &pci_subvendor_id, &pci_subdevice_id, &pci_rev_id); 4395 4396 ent = sctx->isc_vendor_info; 4397 while (ent->pvi_vendor_id != 0) { 4398 if (pci_vendor_id != ent->pvi_vendor_id) { 4399 ent++; 4400 continue; 4401 } 4402 if ((pci_device_id == ent->pvi_device_id) && 4403 ((pci_subvendor_id == ent->pvi_subvendor_id) || 4404 (ent->pvi_subvendor_id == 0)) && 4405 ((pci_subdevice_id == ent->pvi_subdevice_id) || 4406 (ent->pvi_subdevice_id == 0)) && 4407 ((pci_rev_id == ent->pvi_rev_id) || 4408 (ent->pvi_rev_id == 0))) { 4409 4410 device_set_desc_copy(dev, ent->pvi_name); 4411 /* this needs to be changed to zero if the bus probing code 4412 * ever stops re-probing on best match because the sctx 4413 * may have its values over written by register calls 4414 * in subsequent probes 4415 */ 4416 return (BUS_PROBE_DEFAULT); 4417 } 4418 ent++; 4419 } 4420 return (ENXIO); 4421 } 4422 4423 static void 4424 iflib_reset_qvalues(if_ctx_t ctx) 4425 { 4426 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 4427 if_shared_ctx_t sctx = ctx->ifc_sctx; 4428 device_t dev = ctx->ifc_dev; 4429 int i; 4430 4431 scctx->isc_txrx_budget_bytes_max = IFLIB_MAX_TX_BYTES; 4432 scctx->isc_tx_qdepth = IFLIB_DEFAULT_TX_QDEPTH; 4433 /* 4434 * XXX sanity check that ntxd & nrxd are a power of 2 4435 */ 4436 if (ctx->ifc_sysctl_ntxqs != 0) 4437 scctx->isc_ntxqsets = ctx->ifc_sysctl_ntxqs; 4438 if (ctx->ifc_sysctl_nrxqs != 0) 4439 scctx->isc_nrxqsets = ctx->ifc_sysctl_nrxqs; 4440 4441 for (i = 0; i < sctx->isc_ntxqs; i++) { 4442 if (ctx->ifc_sysctl_ntxds[i] != 0) 4443 scctx->isc_ntxd[i] = ctx->ifc_sysctl_ntxds[i]; 4444 else 4445 scctx->isc_ntxd[i] = sctx->isc_ntxd_default[i]; 4446 } 4447 4448 for (i = 0; i < sctx->isc_nrxqs; i++) { 4449 if (ctx->ifc_sysctl_nrxds[i] != 0) 4450 scctx->isc_nrxd[i] = ctx->ifc_sysctl_nrxds[i]; 4451 else 4452 scctx->isc_nrxd[i] = sctx->isc_nrxd_default[i]; 4453 } 4454 4455 for (i = 0; i < sctx->isc_nrxqs; i++) { 4456 if (scctx->isc_nrxd[i] < sctx->isc_nrxd_min[i]) { 4457 device_printf(dev, "nrxd%d: %d less than nrxd_min %d - resetting to min\n", 4458 i, scctx->isc_nrxd[i], sctx->isc_nrxd_min[i]); 4459 scctx->isc_nrxd[i] = sctx->isc_nrxd_min[i]; 4460 } 4461 if (scctx->isc_nrxd[i] > sctx->isc_nrxd_max[i]) { 4462 device_printf(dev, "nrxd%d: %d greater than nrxd_max %d - resetting to max\n", 4463 i, scctx->isc_nrxd[i], sctx->isc_nrxd_max[i]); 4464 scctx->isc_nrxd[i] = sctx->isc_nrxd_max[i]; 4465 } 4466 } 4467 4468 for (i = 0; i < sctx->isc_ntxqs; i++) { 4469 if (scctx->isc_ntxd[i] < sctx->isc_ntxd_min[i]) { 4470 device_printf(dev, "ntxd%d: %d less than ntxd_min %d - resetting to min\n", 4471 i, scctx->isc_ntxd[i], sctx->isc_ntxd_min[i]); 4472 scctx->isc_ntxd[i] = sctx->isc_ntxd_min[i]; 4473 } 4474 if (scctx->isc_ntxd[i] > sctx->isc_ntxd_max[i]) { 4475 device_printf(dev, "ntxd%d: %d greater than ntxd_max %d - resetting to max\n", 4476 i, scctx->isc_ntxd[i], sctx->isc_ntxd_max[i]); 4477 scctx->isc_ntxd[i] = sctx->isc_ntxd_max[i]; 4478 } 4479 } 4480 } 4481 4482 int 4483 iflib_device_register(device_t dev, void *sc, if_shared_ctx_t sctx, if_ctx_t *ctxp) 4484 { 4485 int err, rid, msix; 4486 if_ctx_t ctx; 4487 if_t ifp; 4488 if_softc_ctx_t scctx; 4489 int i; 4490 uint16_t main_txq; 4491 uint16_t main_rxq; 4492 4493 4494 ctx = malloc(sizeof(* ctx), M_IFLIB, M_WAITOK|M_ZERO); 4495 4496 if (sc == NULL) { 4497 sc = malloc(sctx->isc_driver->size, M_IFLIB, M_WAITOK|M_ZERO); 4498 device_set_softc(dev, ctx); 4499 ctx->ifc_flags |= IFC_SC_ALLOCATED; 4500 } 4501 4502 ctx->ifc_sctx = sctx; 4503 ctx->ifc_dev = dev; 4504 ctx->ifc_softc = sc; 4505 4506 if ((err = iflib_register(ctx)) != 0) { 4507 if (ctx->ifc_flags & IFC_SC_ALLOCATED) 4508 free(sc, M_IFLIB); 4509 free(ctx, M_IFLIB); 4510 device_printf(dev, "iflib_register failed %d\n", err); 4511 return (err); 4512 } 4513 iflib_add_device_sysctl_pre(ctx); 4514 4515 scctx = &ctx->ifc_softc_ctx; 4516 ifp = ctx->ifc_ifp; 4517 4518 iflib_reset_qvalues(ctx); 4519 CTX_LOCK(ctx); 4520 if ((err = IFDI_ATTACH_PRE(ctx)) != 0) { 4521 CTX_UNLOCK(ctx); 4522 device_printf(dev, "IFDI_ATTACH_PRE failed %d\n", err); 4523 return (err); 4524 } 4525 _iflib_pre_assert(scctx); 4526 ctx->ifc_txrx = *scctx->isc_txrx; 4527 4528 #ifdef INVARIANTS 4529 MPASS(scctx->isc_capabilities); 4530 if (scctx->isc_capabilities & IFCAP_TXCSUM) 4531 MPASS(scctx->isc_tx_csum_flags); 4532 #endif 4533 4534 if_setcapabilities(ifp, scctx->isc_capabilities | IFCAP_HWSTATS); 4535 if_setcapenable(ifp, scctx->isc_capenable | IFCAP_HWSTATS); 4536 4537 if (scctx->isc_ntxqsets == 0 || (scctx->isc_ntxqsets_max && scctx->isc_ntxqsets_max < scctx->isc_ntxqsets)) 4538 scctx->isc_ntxqsets = scctx->isc_ntxqsets_max; 4539 if (scctx->isc_nrxqsets == 0 || (scctx->isc_nrxqsets_max && scctx->isc_nrxqsets_max < scctx->isc_nrxqsets)) 4540 scctx->isc_nrxqsets = scctx->isc_nrxqsets_max; 4541 4542 #ifdef ACPI_DMAR 4543 if (dmar_get_dma_tag(device_get_parent(dev), dev) != NULL) 4544 ctx->ifc_flags |= IFC_DMAR; 4545 #elif !(defined(__i386__) || defined(__amd64__)) 4546 /* set unconditionally for !x86 */ 4547 ctx->ifc_flags |= IFC_DMAR; 4548 #endif 4549 4550 main_txq = (sctx->isc_flags & IFLIB_HAS_TXCQ) ? 1 : 0; 4551 main_rxq = (sctx->isc_flags & IFLIB_HAS_RXCQ) ? 1 : 0; 4552 4553 /* XXX change for per-queue sizes */ 4554 device_printf(dev, "using %d tx descriptors and %d rx descriptors\n", 4555 scctx->isc_ntxd[main_txq], scctx->isc_nrxd[main_rxq]); 4556 for (i = 0; i < sctx->isc_nrxqs; i++) { 4557 if (!powerof2(scctx->isc_nrxd[i])) { 4558 /* round down instead? */ 4559 device_printf(dev, "# rx descriptors must be a power of 2\n"); 4560 err = EINVAL; 4561 goto fail; 4562 } 4563 } 4564 for (i = 0; i < sctx->isc_ntxqs; i++) { 4565 if (!powerof2(scctx->isc_ntxd[i])) { 4566 device_printf(dev, 4567 "# tx descriptors must be a power of 2"); 4568 err = EINVAL; 4569 goto fail; 4570 } 4571 } 4572 4573 if (scctx->isc_tx_nsegments > scctx->isc_ntxd[main_txq] / 4574 MAX_SINGLE_PACKET_FRACTION) 4575 scctx->isc_tx_nsegments = max(1, scctx->isc_ntxd[main_txq] / 4576 MAX_SINGLE_PACKET_FRACTION); 4577 if (scctx->isc_tx_tso_segments_max > scctx->isc_ntxd[main_txq] / 4578 MAX_SINGLE_PACKET_FRACTION) 4579 scctx->isc_tx_tso_segments_max = max(1, 4580 scctx->isc_ntxd[main_txq] / MAX_SINGLE_PACKET_FRACTION); 4581 4582 /* TSO parameters - dig these out of the data sheet - simply correspond to tag setup */ 4583 if (if_getcapabilities(ifp) & IFCAP_TSO) { 4584 /* 4585 * The stack can't handle a TSO size larger than IP_MAXPACKET, 4586 * but some MACs do. 4587 */ 4588 if_sethwtsomax(ifp, min(scctx->isc_tx_tso_size_max, 4589 IP_MAXPACKET)); 4590 /* 4591 * Take maximum number of m_pullup(9)'s in iflib_parse_header() 4592 * into account. In the worst case, each of these calls will 4593 * add another mbuf and, thus, the requirement for another DMA 4594 * segment. So for best performance, it doesn't make sense to 4595 * advertize a maximum of TSO segments that typically will 4596 * require defragmentation in iflib_encap(). 4597 */ 4598 if_sethwtsomaxsegcount(ifp, scctx->isc_tx_tso_segments_max - 3); 4599 if_sethwtsomaxsegsize(ifp, scctx->isc_tx_tso_segsize_max); 4600 } 4601 if (scctx->isc_rss_table_size == 0) 4602 scctx->isc_rss_table_size = 64; 4603 scctx->isc_rss_table_mask = scctx->isc_rss_table_size-1; 4604 4605 GROUPTASK_INIT(&ctx->ifc_admin_task, 0, _task_fn_admin, ctx); 4606 /* XXX format name */ 4607 taskqgroup_attach(qgroup_if_config_tqg, &ctx->ifc_admin_task, ctx, -1, "admin"); 4608 4609 /* Set up cpu set. If it fails, use the set of all CPUs. */ 4610 if (bus_get_cpus(dev, INTR_CPUS, sizeof(ctx->ifc_cpus), &ctx->ifc_cpus) != 0) { 4611 device_printf(dev, "Unable to fetch CPU list\n"); 4612 CPU_COPY(&all_cpus, &ctx->ifc_cpus); 4613 } 4614 MPASS(CPU_COUNT(&ctx->ifc_cpus) > 0); 4615 4616 /* 4617 ** Now setup MSI or MSI/X, should 4618 ** return us the number of supported 4619 ** vectors. (Will be 1 for MSI) 4620 */ 4621 if (sctx->isc_flags & IFLIB_SKIP_MSIX) { 4622 msix = scctx->isc_vectors; 4623 } else if (scctx->isc_msix_bar != 0) 4624 /* 4625 * The simple fact that isc_msix_bar is not 0 does not mean we 4626 * we have a good value there that is known to work. 4627 */ 4628 msix = iflib_msix_init(ctx); 4629 else { 4630 scctx->isc_vectors = 1; 4631 scctx->isc_ntxqsets = 1; 4632 scctx->isc_nrxqsets = 1; 4633 scctx->isc_intr = IFLIB_INTR_LEGACY; 4634 msix = 0; 4635 } 4636 /* Get memory for the station queues */ 4637 if ((err = iflib_queues_alloc(ctx))) { 4638 device_printf(dev, "Unable to allocate queue memory\n"); 4639 goto fail; 4640 } 4641 4642 if ((err = iflib_qset_structures_setup(ctx))) 4643 goto fail_queues; 4644 4645 /* 4646 * Group taskqueues aren't properly set up until SMP is started, 4647 * so we disable interrupts until we can handle them post 4648 * SI_SUB_SMP. 4649 * 4650 * XXX: disabling interrupts doesn't actually work, at least for 4651 * the non-MSI case. When they occur before SI_SUB_SMP completes, 4652 * we do null handling and depend on this not causing too large an 4653 * interrupt storm. 4654 */ 4655 IFDI_INTR_DISABLE(ctx); 4656 if (msix > 1 && (err = IFDI_MSIX_INTR_ASSIGN(ctx, msix)) != 0) { 4657 device_printf(dev, "IFDI_MSIX_INTR_ASSIGN failed %d\n", err); 4658 goto fail_intr_free; 4659 } 4660 if (msix <= 1) { 4661 rid = 0; 4662 if (scctx->isc_intr == IFLIB_INTR_MSI) { 4663 MPASS(msix == 1); 4664 rid = 1; 4665 } 4666 if ((err = iflib_legacy_setup(ctx, ctx->isc_legacy_intr, ctx->ifc_softc, &rid, "irq0")) != 0) { 4667 device_printf(dev, "iflib_legacy_setup failed %d\n", err); 4668 goto fail_intr_free; 4669 } 4670 } 4671 4672 ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac); 4673 4674 if ((err = IFDI_ATTACH_POST(ctx)) != 0) { 4675 device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err); 4676 goto fail_detach; 4677 } 4678 4679 /* 4680 * Tell the upper layer(s) if IFCAP_VLAN_MTU is supported. 4681 * This must appear after the call to ether_ifattach() because 4682 * ether_ifattach() sets if_hdrlen to the default value. 4683 */ 4684 if (if_getcapabilities(ifp) & IFCAP_VLAN_MTU) 4685 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header)); 4686 4687 if ((err = iflib_netmap_attach(ctx))) { 4688 device_printf(ctx->ifc_dev, "netmap attach failed: %d\n", err); 4689 goto fail_detach; 4690 } 4691 *ctxp = ctx; 4692 4693 NETDUMP_SET(ctx->ifc_ifp, iflib); 4694 4695 if_setgetcounterfn(ctx->ifc_ifp, iflib_if_get_counter); 4696 iflib_add_device_sysctl_post(ctx); 4697 ctx->ifc_flags |= IFC_INIT_DONE; 4698 CTX_UNLOCK(ctx); 4699 return (0); 4700 4701 fail_detach: 4702 ether_ifdetach(ctx->ifc_ifp); 4703 fail_intr_free: 4704 fail_queues: 4705 iflib_tx_structures_free(ctx); 4706 iflib_rx_structures_free(ctx); 4707 fail: 4708 iflib_free_intr_mem(ctx); 4709 IFDI_DETACH(ctx); 4710 CTX_UNLOCK(ctx); 4711 4712 return (err); 4713 } 4714 4715 int 4716 iflib_pseudo_register(device_t dev, if_shared_ctx_t sctx, if_ctx_t *ctxp, 4717 struct iflib_cloneattach_ctx *clctx) 4718 { 4719 int err; 4720 if_ctx_t ctx; 4721 if_t ifp; 4722 if_softc_ctx_t scctx; 4723 int i; 4724 void *sc; 4725 uint16_t main_txq; 4726 uint16_t main_rxq; 4727 4728 ctx = malloc(sizeof(*ctx), M_IFLIB, M_WAITOK|M_ZERO); 4729 sc = malloc(sctx->isc_driver->size, M_IFLIB, M_WAITOK|M_ZERO); 4730 ctx->ifc_flags |= IFC_SC_ALLOCATED; 4731 if (sctx->isc_flags & (IFLIB_PSEUDO|IFLIB_VIRTUAL)) 4732 ctx->ifc_flags |= IFC_PSEUDO; 4733 4734 ctx->ifc_sctx = sctx; 4735 ctx->ifc_softc = sc; 4736 ctx->ifc_dev = dev; 4737 4738 if ((err = iflib_register(ctx)) != 0) { 4739 device_printf(dev, "%s: iflib_register failed %d\n", __func__, err); 4740 free(sc, M_IFLIB); 4741 free(ctx, M_IFLIB); 4742 return (err); 4743 } 4744 iflib_add_device_sysctl_pre(ctx); 4745 4746 scctx = &ctx->ifc_softc_ctx; 4747 ifp = ctx->ifc_ifp; 4748 4749 /* 4750 * XXX sanity check that ntxd & nrxd are a power of 2 4751 */ 4752 iflib_reset_qvalues(ctx); 4753 4754 if ((err = IFDI_ATTACH_PRE(ctx)) != 0) { 4755 device_printf(dev, "IFDI_ATTACH_PRE failed %d\n", err); 4756 return (err); 4757 } 4758 if (sctx->isc_flags & IFLIB_GEN_MAC) 4759 iflib_gen_mac(ctx); 4760 if ((err = IFDI_CLONEATTACH(ctx, clctx->cc_ifc, clctx->cc_name, 4761 clctx->cc_params)) != 0) { 4762 device_printf(dev, "IFDI_CLONEATTACH failed %d\n", err); 4763 return (err); 4764 } 4765 ifmedia_add(&ctx->ifc_media, IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL); 4766 ifmedia_add(&ctx->ifc_media, IFM_ETHER | IFM_AUTO, 0, NULL); 4767 ifmedia_set(&ctx->ifc_media, IFM_ETHER | IFM_AUTO); 4768 4769 #ifdef INVARIANTS 4770 MPASS(scctx->isc_capabilities); 4771 if (scctx->isc_capabilities & IFCAP_TXCSUM) 4772 MPASS(scctx->isc_tx_csum_flags); 4773 #endif 4774 4775 if_setcapabilities(ifp, scctx->isc_capabilities | IFCAP_HWSTATS | IFCAP_LINKSTATE); 4776 if_setcapenable(ifp, scctx->isc_capenable | IFCAP_HWSTATS | IFCAP_LINKSTATE); 4777 4778 ifp->if_flags |= IFF_NOGROUP; 4779 if (sctx->isc_flags & IFLIB_PSEUDO) { 4780 ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac); 4781 4782 if ((err = IFDI_ATTACH_POST(ctx)) != 0) { 4783 device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err); 4784 goto fail_detach; 4785 } 4786 *ctxp = ctx; 4787 4788 /* 4789 * Tell the upper layer(s) if IFCAP_VLAN_MTU is supported. 4790 * This must appear after the call to ether_ifattach() because 4791 * ether_ifattach() sets if_hdrlen to the default value. 4792 */ 4793 if (if_getcapabilities(ifp) & IFCAP_VLAN_MTU) 4794 if_setifheaderlen(ifp, 4795 sizeof(struct ether_vlan_header)); 4796 4797 if_setgetcounterfn(ctx->ifc_ifp, iflib_if_get_counter); 4798 iflib_add_device_sysctl_post(ctx); 4799 ctx->ifc_flags |= IFC_INIT_DONE; 4800 return (0); 4801 } 4802 _iflib_pre_assert(scctx); 4803 ctx->ifc_txrx = *scctx->isc_txrx; 4804 4805 if (scctx->isc_ntxqsets == 0 || (scctx->isc_ntxqsets_max && scctx->isc_ntxqsets_max < scctx->isc_ntxqsets)) 4806 scctx->isc_ntxqsets = scctx->isc_ntxqsets_max; 4807 if (scctx->isc_nrxqsets == 0 || (scctx->isc_nrxqsets_max && scctx->isc_nrxqsets_max < scctx->isc_nrxqsets)) 4808 scctx->isc_nrxqsets = scctx->isc_nrxqsets_max; 4809 4810 main_txq = (sctx->isc_flags & IFLIB_HAS_TXCQ) ? 1 : 0; 4811 main_rxq = (sctx->isc_flags & IFLIB_HAS_RXCQ) ? 1 : 0; 4812 4813 /* XXX change for per-queue sizes */ 4814 device_printf(dev, "using %d tx descriptors and %d rx descriptors\n", 4815 scctx->isc_ntxd[main_txq], scctx->isc_nrxd[main_rxq]); 4816 for (i = 0; i < sctx->isc_nrxqs; i++) { 4817 if (!powerof2(scctx->isc_nrxd[i])) { 4818 /* round down instead? */ 4819 device_printf(dev, "# rx descriptors must be a power of 2\n"); 4820 err = EINVAL; 4821 goto fail; 4822 } 4823 } 4824 for (i = 0; i < sctx->isc_ntxqs; i++) { 4825 if (!powerof2(scctx->isc_ntxd[i])) { 4826 device_printf(dev, 4827 "# tx descriptors must be a power of 2"); 4828 err = EINVAL; 4829 goto fail; 4830 } 4831 } 4832 4833 if (scctx->isc_tx_nsegments > scctx->isc_ntxd[main_txq] / 4834 MAX_SINGLE_PACKET_FRACTION) 4835 scctx->isc_tx_nsegments = max(1, scctx->isc_ntxd[main_txq] / 4836 MAX_SINGLE_PACKET_FRACTION); 4837 if (scctx->isc_tx_tso_segments_max > scctx->isc_ntxd[main_txq] / 4838 MAX_SINGLE_PACKET_FRACTION) 4839 scctx->isc_tx_tso_segments_max = max(1, 4840 scctx->isc_ntxd[main_txq] / MAX_SINGLE_PACKET_FRACTION); 4841 4842 /* TSO parameters - dig these out of the data sheet - simply correspond to tag setup */ 4843 if (if_getcapabilities(ifp) & IFCAP_TSO) { 4844 /* 4845 * The stack can't handle a TSO size larger than IP_MAXPACKET, 4846 * but some MACs do. 4847 */ 4848 if_sethwtsomax(ifp, min(scctx->isc_tx_tso_size_max, 4849 IP_MAXPACKET)); 4850 /* 4851 * Take maximum number of m_pullup(9)'s in iflib_parse_header() 4852 * into account. In the worst case, each of these calls will 4853 * add another mbuf and, thus, the requirement for another DMA 4854 * segment. So for best performance, it doesn't make sense to 4855 * advertize a maximum of TSO segments that typically will 4856 * require defragmentation in iflib_encap(). 4857 */ 4858 if_sethwtsomaxsegcount(ifp, scctx->isc_tx_tso_segments_max - 3); 4859 if_sethwtsomaxsegsize(ifp, scctx->isc_tx_tso_segsize_max); 4860 } 4861 if (scctx->isc_rss_table_size == 0) 4862 scctx->isc_rss_table_size = 64; 4863 scctx->isc_rss_table_mask = scctx->isc_rss_table_size-1; 4864 4865 GROUPTASK_INIT(&ctx->ifc_admin_task, 0, _task_fn_admin, ctx); 4866 /* XXX format name */ 4867 taskqgroup_attach(qgroup_if_config_tqg, &ctx->ifc_admin_task, ctx, -1, "admin"); 4868 4869 /* XXX --- can support > 1 -- but keep it simple for now */ 4870 scctx->isc_intr = IFLIB_INTR_LEGACY; 4871 4872 /* Get memory for the station queues */ 4873 if ((err = iflib_queues_alloc(ctx))) { 4874 device_printf(dev, "Unable to allocate queue memory\n"); 4875 goto fail; 4876 } 4877 4878 if ((err = iflib_qset_structures_setup(ctx))) { 4879 device_printf(dev, "qset structure setup failed %d\n", err); 4880 goto fail_queues; 4881 } 4882 4883 /* 4884 * XXX What if anything do we want to do about interrupts? 4885 */ 4886 ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac); 4887 if ((err = IFDI_ATTACH_POST(ctx)) != 0) { 4888 device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err); 4889 goto fail_detach; 4890 } 4891 4892 /* 4893 * Tell the upper layer(s) if IFCAP_VLAN_MTU is supported. 4894 * This must appear after the call to ether_ifattach() because 4895 * ether_ifattach() sets if_hdrlen to the default value. 4896 */ 4897 if (if_getcapabilities(ifp) & IFCAP_VLAN_MTU) 4898 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header)); 4899 4900 /* XXX handle more than one queue */ 4901 for (i = 0; i < scctx->isc_nrxqsets; i++) 4902 IFDI_RX_CLSET(ctx, 0, i, ctx->ifc_rxqs[i].ifr_fl[0].ifl_sds.ifsd_cl); 4903 4904 *ctxp = ctx; 4905 4906 if_setgetcounterfn(ctx->ifc_ifp, iflib_if_get_counter); 4907 iflib_add_device_sysctl_post(ctx); 4908 ctx->ifc_flags |= IFC_INIT_DONE; 4909 return (0); 4910 fail_detach: 4911 ether_ifdetach(ctx->ifc_ifp); 4912 fail_queues: 4913 iflib_tx_structures_free(ctx); 4914 iflib_rx_structures_free(ctx); 4915 fail: 4916 IFDI_DETACH(ctx); 4917 return (err); 4918 } 4919 4920 int 4921 iflib_pseudo_deregister(if_ctx_t ctx) 4922 { 4923 if_t ifp = ctx->ifc_ifp; 4924 iflib_txq_t txq; 4925 iflib_rxq_t rxq; 4926 int i, j; 4927 struct taskqgroup *tqg; 4928 iflib_fl_t fl; 4929 4930 /* Unregister VLAN events */ 4931 if (ctx->ifc_vlan_attach_event != NULL) 4932 EVENTHANDLER_DEREGISTER(vlan_config, ctx->ifc_vlan_attach_event); 4933 if (ctx->ifc_vlan_detach_event != NULL) 4934 EVENTHANDLER_DEREGISTER(vlan_unconfig, ctx->ifc_vlan_detach_event); 4935 4936 ether_ifdetach(ifp); 4937 /* ether_ifdetach calls if_qflush - lock must be destroy afterwards*/ 4938 CTX_LOCK_DESTROY(ctx); 4939 /* XXX drain any dependent tasks */ 4940 tqg = qgroup_if_io_tqg; 4941 for (txq = ctx->ifc_txqs, i = 0; i < NTXQSETS(ctx); i++, txq++) { 4942 callout_drain(&txq->ift_timer); 4943 if (txq->ift_task.gt_uniq != NULL) 4944 taskqgroup_detach(tqg, &txq->ift_task); 4945 } 4946 for (i = 0, rxq = ctx->ifc_rxqs; i < NRXQSETS(ctx); i++, rxq++) { 4947 if (rxq->ifr_task.gt_uniq != NULL) 4948 taskqgroup_detach(tqg, &rxq->ifr_task); 4949 4950 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) 4951 free(fl->ifl_rx_bitmap, M_IFLIB); 4952 } 4953 tqg = qgroup_if_config_tqg; 4954 if (ctx->ifc_admin_task.gt_uniq != NULL) 4955 taskqgroup_detach(tqg, &ctx->ifc_admin_task); 4956 if (ctx->ifc_vflr_task.gt_uniq != NULL) 4957 taskqgroup_detach(tqg, &ctx->ifc_vflr_task); 4958 4959 if_free(ifp); 4960 4961 iflib_tx_structures_free(ctx); 4962 iflib_rx_structures_free(ctx); 4963 if (ctx->ifc_flags & IFC_SC_ALLOCATED) 4964 free(ctx->ifc_softc, M_IFLIB); 4965 free(ctx, M_IFLIB); 4966 return (0); 4967 } 4968 4969 int 4970 iflib_device_attach(device_t dev) 4971 { 4972 if_ctx_t ctx; 4973 if_shared_ctx_t sctx; 4974 4975 if ((sctx = DEVICE_REGISTER(dev)) == NULL || sctx->isc_magic != IFLIB_MAGIC) 4976 return (ENOTSUP); 4977 4978 pci_enable_busmaster(dev); 4979 4980 return (iflib_device_register(dev, NULL, sctx, &ctx)); 4981 } 4982 4983 int 4984 iflib_device_deregister(if_ctx_t ctx) 4985 { 4986 if_t ifp = ctx->ifc_ifp; 4987 iflib_txq_t txq; 4988 iflib_rxq_t rxq; 4989 device_t dev = ctx->ifc_dev; 4990 int i, j; 4991 struct taskqgroup *tqg; 4992 iflib_fl_t fl; 4993 4994 /* Make sure VLANS are not using driver */ 4995 if (if_vlantrunkinuse(ifp)) { 4996 device_printf(dev, "Vlan in use, detach first\n"); 4997 return (EBUSY); 4998 } 4999 #ifdef PCI_IOV 5000 if (!CTX_IS_VF(ctx) && pci_iov_detach(dev) != 0) { 5001 device_printf(dev, "SR-IOV in use; detach first.\n"); 5002 return (EBUSY); 5003 } 5004 #endif 5005 5006 STATE_LOCK(ctx); 5007 ctx->ifc_flags |= IFC_IN_DETACH; 5008 STATE_UNLOCK(ctx); 5009 5010 CTX_LOCK(ctx); 5011 iflib_stop(ctx); 5012 CTX_UNLOCK(ctx); 5013 5014 /* Unregister VLAN events */ 5015 if (ctx->ifc_vlan_attach_event != NULL) 5016 EVENTHANDLER_DEREGISTER(vlan_config, ctx->ifc_vlan_attach_event); 5017 if (ctx->ifc_vlan_detach_event != NULL) 5018 EVENTHANDLER_DEREGISTER(vlan_unconfig, ctx->ifc_vlan_detach_event); 5019 5020 iflib_netmap_detach(ifp); 5021 ether_ifdetach(ifp); 5022 if (ctx->ifc_led_dev != NULL) 5023 led_destroy(ctx->ifc_led_dev); 5024 /* XXX drain any dependent tasks */ 5025 tqg = qgroup_if_io_tqg; 5026 for (txq = ctx->ifc_txqs, i = 0; i < NTXQSETS(ctx); i++, txq++) { 5027 callout_drain(&txq->ift_timer); 5028 if (txq->ift_task.gt_uniq != NULL) 5029 taskqgroup_detach(tqg, &txq->ift_task); 5030 } 5031 for (i = 0, rxq = ctx->ifc_rxqs; i < NRXQSETS(ctx); i++, rxq++) { 5032 if (rxq->ifr_task.gt_uniq != NULL) 5033 taskqgroup_detach(tqg, &rxq->ifr_task); 5034 5035 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) 5036 free(fl->ifl_rx_bitmap, M_IFLIB); 5037 5038 } 5039 tqg = qgroup_if_config_tqg; 5040 if (ctx->ifc_admin_task.gt_uniq != NULL) 5041 taskqgroup_detach(tqg, &ctx->ifc_admin_task); 5042 if (ctx->ifc_vflr_task.gt_uniq != NULL) 5043 taskqgroup_detach(tqg, &ctx->ifc_vflr_task); 5044 CTX_LOCK(ctx); 5045 IFDI_DETACH(ctx); 5046 CTX_UNLOCK(ctx); 5047 5048 /* ether_ifdetach calls if_qflush - lock must be destroy afterwards*/ 5049 CTX_LOCK_DESTROY(ctx); 5050 device_set_softc(ctx->ifc_dev, NULL); 5051 iflib_free_intr_mem(ctx); 5052 5053 bus_generic_detach(dev); 5054 if_free(ifp); 5055 5056 iflib_tx_structures_free(ctx); 5057 iflib_rx_structures_free(ctx); 5058 if (ctx->ifc_flags & IFC_SC_ALLOCATED) 5059 free(ctx->ifc_softc, M_IFLIB); 5060 STATE_LOCK_DESTROY(ctx); 5061 free(ctx, M_IFLIB); 5062 return (0); 5063 } 5064 5065 static void 5066 iflib_free_intr_mem(if_ctx_t ctx) 5067 { 5068 5069 if (ctx->ifc_softc_ctx.isc_intr != IFLIB_INTR_LEGACY) { 5070 pci_release_msi(ctx->ifc_dev); 5071 } 5072 if (ctx->ifc_softc_ctx.isc_intr != IFLIB_INTR_MSIX) { 5073 iflib_irq_free(ctx, &ctx->ifc_legacy_irq); 5074 } 5075 if (ctx->ifc_msix_mem != NULL) { 5076 bus_release_resource(ctx->ifc_dev, SYS_RES_MEMORY, 5077 ctx->ifc_softc_ctx.isc_msix_bar, ctx->ifc_msix_mem); 5078 ctx->ifc_msix_mem = NULL; 5079 } 5080 } 5081 5082 int 5083 iflib_device_detach(device_t dev) 5084 { 5085 if_ctx_t ctx = device_get_softc(dev); 5086 5087 return (iflib_device_deregister(ctx)); 5088 } 5089 5090 int 5091 iflib_device_suspend(device_t dev) 5092 { 5093 if_ctx_t ctx = device_get_softc(dev); 5094 5095 CTX_LOCK(ctx); 5096 IFDI_SUSPEND(ctx); 5097 CTX_UNLOCK(ctx); 5098 5099 return bus_generic_suspend(dev); 5100 } 5101 int 5102 iflib_device_shutdown(device_t dev) 5103 { 5104 if_ctx_t ctx = device_get_softc(dev); 5105 5106 CTX_LOCK(ctx); 5107 IFDI_SHUTDOWN(ctx); 5108 CTX_UNLOCK(ctx); 5109 5110 return bus_generic_suspend(dev); 5111 } 5112 5113 5114 int 5115 iflib_device_resume(device_t dev) 5116 { 5117 if_ctx_t ctx = device_get_softc(dev); 5118 iflib_txq_t txq = ctx->ifc_txqs; 5119 5120 CTX_LOCK(ctx); 5121 IFDI_RESUME(ctx); 5122 iflib_init_locked(ctx); 5123 CTX_UNLOCK(ctx); 5124 for (int i = 0; i < NTXQSETS(ctx); i++, txq++) 5125 iflib_txq_check_drain(txq, IFLIB_RESTART_BUDGET); 5126 5127 return (bus_generic_resume(dev)); 5128 } 5129 5130 int 5131 iflib_device_iov_init(device_t dev, uint16_t num_vfs, const nvlist_t *params) 5132 { 5133 int error; 5134 if_ctx_t ctx = device_get_softc(dev); 5135 5136 CTX_LOCK(ctx); 5137 error = IFDI_IOV_INIT(ctx, num_vfs, params); 5138 CTX_UNLOCK(ctx); 5139 5140 return (error); 5141 } 5142 5143 void 5144 iflib_device_iov_uninit(device_t dev) 5145 { 5146 if_ctx_t ctx = device_get_softc(dev); 5147 5148 CTX_LOCK(ctx); 5149 IFDI_IOV_UNINIT(ctx); 5150 CTX_UNLOCK(ctx); 5151 } 5152 5153 int 5154 iflib_device_iov_add_vf(device_t dev, uint16_t vfnum, const nvlist_t *params) 5155 { 5156 int error; 5157 if_ctx_t ctx = device_get_softc(dev); 5158 5159 CTX_LOCK(ctx); 5160 error = IFDI_IOV_VF_ADD(ctx, vfnum, params); 5161 CTX_UNLOCK(ctx); 5162 5163 return (error); 5164 } 5165 5166 /********************************************************************* 5167 * 5168 * MODULE FUNCTION DEFINITIONS 5169 * 5170 **********************************************************************/ 5171 5172 /* 5173 * - Start a fast taskqueue thread for each core 5174 * - Start a taskqueue for control operations 5175 */ 5176 static int 5177 iflib_module_init(void) 5178 { 5179 return (0); 5180 } 5181 5182 static int 5183 iflib_module_event_handler(module_t mod, int what, void *arg) 5184 { 5185 int err; 5186 5187 switch (what) { 5188 case MOD_LOAD: 5189 if ((err = iflib_module_init()) != 0) 5190 return (err); 5191 break; 5192 case MOD_UNLOAD: 5193 return (EBUSY); 5194 default: 5195 return (EOPNOTSUPP); 5196 } 5197 5198 return (0); 5199 } 5200 5201 /********************************************************************* 5202 * 5203 * PUBLIC FUNCTION DEFINITIONS 5204 * ordered as in iflib.h 5205 * 5206 **********************************************************************/ 5207 5208 5209 static void 5210 _iflib_assert(if_shared_ctx_t sctx) 5211 { 5212 MPASS(sctx->isc_tx_maxsize); 5213 MPASS(sctx->isc_tx_maxsegsize); 5214 5215 MPASS(sctx->isc_rx_maxsize); 5216 MPASS(sctx->isc_rx_nsegments); 5217 MPASS(sctx->isc_rx_maxsegsize); 5218 5219 MPASS(sctx->isc_nrxd_min[0]); 5220 MPASS(sctx->isc_nrxd_max[0]); 5221 MPASS(sctx->isc_nrxd_default[0]); 5222 MPASS(sctx->isc_ntxd_min[0]); 5223 MPASS(sctx->isc_ntxd_max[0]); 5224 MPASS(sctx->isc_ntxd_default[0]); 5225 } 5226 5227 static void 5228 _iflib_pre_assert(if_softc_ctx_t scctx) 5229 { 5230 5231 MPASS(scctx->isc_txrx->ift_txd_encap); 5232 MPASS(scctx->isc_txrx->ift_txd_flush); 5233 MPASS(scctx->isc_txrx->ift_txd_credits_update); 5234 MPASS(scctx->isc_txrx->ift_rxd_available); 5235 MPASS(scctx->isc_txrx->ift_rxd_pkt_get); 5236 MPASS(scctx->isc_txrx->ift_rxd_refill); 5237 MPASS(scctx->isc_txrx->ift_rxd_flush); 5238 } 5239 5240 static int 5241 iflib_register(if_ctx_t ctx) 5242 { 5243 if_shared_ctx_t sctx = ctx->ifc_sctx; 5244 driver_t *driver = sctx->isc_driver; 5245 device_t dev = ctx->ifc_dev; 5246 if_t ifp; 5247 5248 _iflib_assert(sctx); 5249 5250 CTX_LOCK_INIT(ctx); 5251 STATE_LOCK_INIT(ctx, device_get_nameunit(ctx->ifc_dev)); 5252 ifp = ctx->ifc_ifp = if_alloc(IFT_ETHER); 5253 if (ifp == NULL) { 5254 device_printf(dev, "can not allocate ifnet structure\n"); 5255 return (ENOMEM); 5256 } 5257 5258 /* 5259 * Initialize our context's device specific methods 5260 */ 5261 kobj_init((kobj_t) ctx, (kobj_class_t) driver); 5262 kobj_class_compile((kobj_class_t) driver); 5263 driver->refs++; 5264 5265 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 5266 if_setsoftc(ifp, ctx); 5267 if_setdev(ifp, dev); 5268 if_setinitfn(ifp, iflib_if_init); 5269 if_setioctlfn(ifp, iflib_if_ioctl); 5270 #ifdef ALTQ 5271 if_setstartfn(ifp, iflib_altq_if_start); 5272 if_settransmitfn(ifp, iflib_altq_if_transmit); 5273 if_setsendqready(ifp); 5274 #else 5275 if_settransmitfn(ifp, iflib_if_transmit); 5276 #endif 5277 if_setqflushfn(ifp, iflib_if_qflush); 5278 if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST); 5279 5280 ctx->ifc_vlan_attach_event = 5281 EVENTHANDLER_REGISTER(vlan_config, iflib_vlan_register, ctx, 5282 EVENTHANDLER_PRI_FIRST); 5283 ctx->ifc_vlan_detach_event = 5284 EVENTHANDLER_REGISTER(vlan_unconfig, iflib_vlan_unregister, ctx, 5285 EVENTHANDLER_PRI_FIRST); 5286 5287 ifmedia_init(&ctx->ifc_media, IFM_IMASK, 5288 iflib_media_change, iflib_media_status); 5289 5290 return (0); 5291 } 5292 5293 5294 static int 5295 iflib_queues_alloc(if_ctx_t ctx) 5296 { 5297 if_shared_ctx_t sctx = ctx->ifc_sctx; 5298 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 5299 device_t dev = ctx->ifc_dev; 5300 int nrxqsets = scctx->isc_nrxqsets; 5301 int ntxqsets = scctx->isc_ntxqsets; 5302 iflib_txq_t txq; 5303 iflib_rxq_t rxq; 5304 iflib_fl_t fl = NULL; 5305 int i, j, cpu, err, txconf, rxconf; 5306 iflib_dma_info_t ifdip; 5307 uint32_t *rxqsizes = scctx->isc_rxqsizes; 5308 uint32_t *txqsizes = scctx->isc_txqsizes; 5309 uint8_t nrxqs = sctx->isc_nrxqs; 5310 uint8_t ntxqs = sctx->isc_ntxqs; 5311 int nfree_lists = sctx->isc_nfl ? sctx->isc_nfl : 1; 5312 caddr_t *vaddrs; 5313 uint64_t *paddrs; 5314 5315 KASSERT(ntxqs > 0, ("number of queues per qset must be at least 1")); 5316 KASSERT(nrxqs > 0, ("number of queues per qset must be at least 1")); 5317 5318 /* Allocate the TX ring struct memory */ 5319 if (!(ctx->ifc_txqs = 5320 (iflib_txq_t) malloc(sizeof(struct iflib_txq) * 5321 ntxqsets, M_IFLIB, M_NOWAIT | M_ZERO))) { 5322 device_printf(dev, "Unable to allocate TX ring memory\n"); 5323 err = ENOMEM; 5324 goto fail; 5325 } 5326 5327 /* Now allocate the RX */ 5328 if (!(ctx->ifc_rxqs = 5329 (iflib_rxq_t) malloc(sizeof(struct iflib_rxq) * 5330 nrxqsets, M_IFLIB, M_NOWAIT | M_ZERO))) { 5331 device_printf(dev, "Unable to allocate RX ring memory\n"); 5332 err = ENOMEM; 5333 goto rx_fail; 5334 } 5335 5336 txq = ctx->ifc_txqs; 5337 rxq = ctx->ifc_rxqs; 5338 5339 /* 5340 * XXX handle allocation failure 5341 */ 5342 for (txconf = i = 0, cpu = CPU_FIRST(); i < ntxqsets; i++, txconf++, txq++, cpu = CPU_NEXT(cpu)) { 5343 /* Set up some basics */ 5344 5345 if ((ifdip = malloc(sizeof(struct iflib_dma_info) * ntxqs, M_IFLIB, M_WAITOK|M_ZERO)) == NULL) { 5346 device_printf(dev, "failed to allocate iflib_dma_info\n"); 5347 err = ENOMEM; 5348 goto err_tx_desc; 5349 } 5350 txq->ift_ifdi = ifdip; 5351 for (j = 0; j < ntxqs; j++, ifdip++) { 5352 if (iflib_dma_alloc(ctx, txqsizes[j], ifdip, BUS_DMA_NOWAIT)) { 5353 device_printf(dev, "Unable to allocate Descriptor memory\n"); 5354 err = ENOMEM; 5355 goto err_tx_desc; 5356 } 5357 txq->ift_txd_size[j] = scctx->isc_txd_size[j]; 5358 bzero((void *)ifdip->idi_vaddr, txqsizes[j]); 5359 } 5360 txq->ift_ctx = ctx; 5361 txq->ift_id = i; 5362 if (sctx->isc_flags & IFLIB_HAS_TXCQ) { 5363 txq->ift_br_offset = 1; 5364 } else { 5365 txq->ift_br_offset = 0; 5366 } 5367 /* XXX fix this */ 5368 txq->ift_timer.c_cpu = cpu; 5369 5370 if (iflib_txsd_alloc(txq)) { 5371 device_printf(dev, "Critical Failure setting up TX buffers\n"); 5372 err = ENOMEM; 5373 goto err_tx_desc; 5374 } 5375 5376 /* Initialize the TX lock */ 5377 snprintf(txq->ift_mtx_name, MTX_NAME_LEN, "%s:tx(%d):callout", 5378 device_get_nameunit(dev), txq->ift_id); 5379 mtx_init(&txq->ift_mtx, txq->ift_mtx_name, NULL, MTX_DEF); 5380 callout_init_mtx(&txq->ift_timer, &txq->ift_mtx, 0); 5381 5382 snprintf(txq->ift_db_mtx_name, MTX_NAME_LEN, "%s:tx(%d):db", 5383 device_get_nameunit(dev), txq->ift_id); 5384 5385 err = ifmp_ring_alloc(&txq->ift_br, 2048, txq, iflib_txq_drain, 5386 iflib_txq_can_drain, M_IFLIB, M_WAITOK); 5387 if (err) { 5388 /* XXX free any allocated rings */ 5389 device_printf(dev, "Unable to allocate buf_ring\n"); 5390 goto err_tx_desc; 5391 } 5392 } 5393 5394 for (rxconf = i = 0; i < nrxqsets; i++, rxconf++, rxq++) { 5395 /* Set up some basics */ 5396 5397 if ((ifdip = malloc(sizeof(struct iflib_dma_info) * nrxqs, M_IFLIB, M_WAITOK|M_ZERO)) == NULL) { 5398 device_printf(dev, "failed to allocate iflib_dma_info\n"); 5399 err = ENOMEM; 5400 goto err_tx_desc; 5401 } 5402 5403 rxq->ifr_ifdi = ifdip; 5404 /* XXX this needs to be changed if #rx queues != #tx queues */ 5405 rxq->ifr_ntxqirq = 1; 5406 rxq->ifr_txqid[0] = i; 5407 for (j = 0; j < nrxqs; j++, ifdip++) { 5408 if (iflib_dma_alloc(ctx, rxqsizes[j], ifdip, BUS_DMA_NOWAIT)) { 5409 device_printf(dev, "Unable to allocate Descriptor memory\n"); 5410 err = ENOMEM; 5411 goto err_tx_desc; 5412 } 5413 bzero((void *)ifdip->idi_vaddr, rxqsizes[j]); 5414 } 5415 rxq->ifr_ctx = ctx; 5416 rxq->ifr_id = i; 5417 if (sctx->isc_flags & IFLIB_HAS_RXCQ) { 5418 rxq->ifr_fl_offset = 1; 5419 } else { 5420 rxq->ifr_fl_offset = 0; 5421 } 5422 rxq->ifr_nfl = nfree_lists; 5423 if (!(fl = 5424 (iflib_fl_t) malloc(sizeof(struct iflib_fl) * nfree_lists, M_IFLIB, M_NOWAIT | M_ZERO))) { 5425 device_printf(dev, "Unable to allocate free list memory\n"); 5426 err = ENOMEM; 5427 goto err_tx_desc; 5428 } 5429 rxq->ifr_fl = fl; 5430 for (j = 0; j < nfree_lists; j++) { 5431 fl[j].ifl_rxq = rxq; 5432 fl[j].ifl_id = j; 5433 fl[j].ifl_ifdi = &rxq->ifr_ifdi[j + rxq->ifr_fl_offset]; 5434 fl[j].ifl_rxd_size = scctx->isc_rxd_size[j]; 5435 } 5436 /* Allocate receive buffers for the ring */ 5437 if (iflib_rxsd_alloc(rxq)) { 5438 device_printf(dev, 5439 "Critical Failure setting up receive buffers\n"); 5440 err = ENOMEM; 5441 goto err_rx_desc; 5442 } 5443 5444 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) 5445 fl->ifl_rx_bitmap = bit_alloc(fl->ifl_size, M_IFLIB, M_WAITOK|M_ZERO); 5446 } 5447 5448 /* TXQs */ 5449 vaddrs = malloc(sizeof(caddr_t)*ntxqsets*ntxqs, M_IFLIB, M_WAITOK); 5450 paddrs = malloc(sizeof(uint64_t)*ntxqsets*ntxqs, M_IFLIB, M_WAITOK); 5451 for (i = 0; i < ntxqsets; i++) { 5452 iflib_dma_info_t di = ctx->ifc_txqs[i].ift_ifdi; 5453 5454 for (j = 0; j < ntxqs; j++, di++) { 5455 vaddrs[i*ntxqs + j] = di->idi_vaddr; 5456 paddrs[i*ntxqs + j] = di->idi_paddr; 5457 } 5458 } 5459 if ((err = IFDI_TX_QUEUES_ALLOC(ctx, vaddrs, paddrs, ntxqs, ntxqsets)) != 0) { 5460 device_printf(ctx->ifc_dev, "device queue allocation failed\n"); 5461 iflib_tx_structures_free(ctx); 5462 free(vaddrs, M_IFLIB); 5463 free(paddrs, M_IFLIB); 5464 goto err_rx_desc; 5465 } 5466 free(vaddrs, M_IFLIB); 5467 free(paddrs, M_IFLIB); 5468 5469 /* RXQs */ 5470 vaddrs = malloc(sizeof(caddr_t)*nrxqsets*nrxqs, M_IFLIB, M_WAITOK); 5471 paddrs = malloc(sizeof(uint64_t)*nrxqsets*nrxqs, M_IFLIB, M_WAITOK); 5472 for (i = 0; i < nrxqsets; i++) { 5473 iflib_dma_info_t di = ctx->ifc_rxqs[i].ifr_ifdi; 5474 5475 for (j = 0; j < nrxqs; j++, di++) { 5476 vaddrs[i*nrxqs + j] = di->idi_vaddr; 5477 paddrs[i*nrxqs + j] = di->idi_paddr; 5478 } 5479 } 5480 if ((err = IFDI_RX_QUEUES_ALLOC(ctx, vaddrs, paddrs, nrxqs, nrxqsets)) != 0) { 5481 device_printf(ctx->ifc_dev, "device queue allocation failed\n"); 5482 iflib_tx_structures_free(ctx); 5483 free(vaddrs, M_IFLIB); 5484 free(paddrs, M_IFLIB); 5485 goto err_rx_desc; 5486 } 5487 free(vaddrs, M_IFLIB); 5488 free(paddrs, M_IFLIB); 5489 5490 return (0); 5491 5492 /* XXX handle allocation failure changes */ 5493 err_rx_desc: 5494 err_tx_desc: 5495 rx_fail: 5496 if (ctx->ifc_rxqs != NULL) 5497 free(ctx->ifc_rxqs, M_IFLIB); 5498 ctx->ifc_rxqs = NULL; 5499 if (ctx->ifc_txqs != NULL) 5500 free(ctx->ifc_txqs, M_IFLIB); 5501 ctx->ifc_txqs = NULL; 5502 fail: 5503 return (err); 5504 } 5505 5506 static int 5507 iflib_tx_structures_setup(if_ctx_t ctx) 5508 { 5509 iflib_txq_t txq = ctx->ifc_txqs; 5510 int i; 5511 5512 for (i = 0; i < NTXQSETS(ctx); i++, txq++) 5513 iflib_txq_setup(txq); 5514 5515 return (0); 5516 } 5517 5518 static void 5519 iflib_tx_structures_free(if_ctx_t ctx) 5520 { 5521 iflib_txq_t txq = ctx->ifc_txqs; 5522 if_shared_ctx_t sctx = ctx->ifc_sctx; 5523 int i, j; 5524 5525 for (i = 0; i < NTXQSETS(ctx); i++, txq++) { 5526 iflib_txq_destroy(txq); 5527 for (j = 0; j < sctx->isc_ntxqs; j++) 5528 iflib_dma_free(&txq->ift_ifdi[j]); 5529 } 5530 free(ctx->ifc_txqs, M_IFLIB); 5531 ctx->ifc_txqs = NULL; 5532 IFDI_QUEUES_FREE(ctx); 5533 } 5534 5535 /********************************************************************* 5536 * 5537 * Initialize all receive rings. 5538 * 5539 **********************************************************************/ 5540 static int 5541 iflib_rx_structures_setup(if_ctx_t ctx) 5542 { 5543 iflib_rxq_t rxq = ctx->ifc_rxqs; 5544 int q; 5545 #if defined(INET6) || defined(INET) 5546 int i, err; 5547 #endif 5548 5549 for (q = 0; q < ctx->ifc_softc_ctx.isc_nrxqsets; q++, rxq++) { 5550 #if defined(INET6) || defined(INET) 5551 tcp_lro_free(&rxq->ifr_lc); 5552 if ((err = tcp_lro_init_args(&rxq->ifr_lc, ctx->ifc_ifp, 5553 TCP_LRO_ENTRIES, min(1024, 5554 ctx->ifc_softc_ctx.isc_nrxd[rxq->ifr_fl_offset]))) != 0) { 5555 device_printf(ctx->ifc_dev, "LRO Initialization failed!\n"); 5556 goto fail; 5557 } 5558 rxq->ifr_lro_enabled = TRUE; 5559 #endif 5560 IFDI_RXQ_SETUP(ctx, rxq->ifr_id); 5561 } 5562 return (0); 5563 #if defined(INET6) || defined(INET) 5564 fail: 5565 /* 5566 * Free RX software descriptors allocated so far, we will only handle 5567 * the rings that completed, the failing case will have 5568 * cleaned up for itself. 'q' failed, so its the terminus. 5569 */ 5570 rxq = ctx->ifc_rxqs; 5571 for (i = 0; i < q; ++i, rxq++) { 5572 iflib_rx_sds_free(rxq); 5573 rxq->ifr_cq_gen = rxq->ifr_cq_cidx = rxq->ifr_cq_pidx = 0; 5574 } 5575 return (err); 5576 #endif 5577 } 5578 5579 /********************************************************************* 5580 * 5581 * Free all receive rings. 5582 * 5583 **********************************************************************/ 5584 static void 5585 iflib_rx_structures_free(if_ctx_t ctx) 5586 { 5587 iflib_rxq_t rxq = ctx->ifc_rxqs; 5588 5589 for (int i = 0; i < ctx->ifc_softc_ctx.isc_nrxqsets; i++, rxq++) { 5590 iflib_rx_sds_free(rxq); 5591 } 5592 free(ctx->ifc_rxqs, M_IFLIB); 5593 ctx->ifc_rxqs = NULL; 5594 } 5595 5596 static int 5597 iflib_qset_structures_setup(if_ctx_t ctx) 5598 { 5599 int err; 5600 5601 /* 5602 * It is expected that the caller takes care of freeing queues if this 5603 * fails. 5604 */ 5605 if ((err = iflib_tx_structures_setup(ctx)) != 0) { 5606 device_printf(ctx->ifc_dev, "iflib_tx_structures_setup failed: %d\n", err); 5607 return (err); 5608 } 5609 5610 if ((err = iflib_rx_structures_setup(ctx)) != 0) 5611 device_printf(ctx->ifc_dev, "iflib_rx_structures_setup failed: %d\n", err); 5612 5613 return (err); 5614 } 5615 5616 int 5617 iflib_irq_alloc(if_ctx_t ctx, if_irq_t irq, int rid, 5618 driver_filter_t filter, void *filter_arg, driver_intr_t handler, void *arg, const char *name) 5619 { 5620 5621 return (_iflib_irq_alloc(ctx, irq, rid, filter, handler, arg, name)); 5622 } 5623 5624 #ifdef SMP 5625 static int 5626 find_nth(if_ctx_t ctx, int qid) 5627 { 5628 cpuset_t cpus; 5629 int i, cpuid, eqid, count; 5630 5631 CPU_COPY(&ctx->ifc_cpus, &cpus); 5632 count = CPU_COUNT(&cpus); 5633 eqid = qid % count; 5634 /* clear up to the qid'th bit */ 5635 for (i = 0; i < eqid; i++) { 5636 cpuid = CPU_FFS(&cpus); 5637 MPASS(cpuid != 0); 5638 CPU_CLR(cpuid-1, &cpus); 5639 } 5640 cpuid = CPU_FFS(&cpus); 5641 MPASS(cpuid != 0); 5642 return (cpuid-1); 5643 } 5644 5645 #ifdef SCHED_ULE 5646 extern struct cpu_group *cpu_top; /* CPU topology */ 5647 5648 static int 5649 find_child_with_core(int cpu, struct cpu_group *grp) 5650 { 5651 int i; 5652 5653 if (grp->cg_children == 0) 5654 return -1; 5655 5656 MPASS(grp->cg_child); 5657 for (i = 0; i < grp->cg_children; i++) { 5658 if (CPU_ISSET(cpu, &grp->cg_child[i].cg_mask)) 5659 return i; 5660 } 5661 5662 return -1; 5663 } 5664 5665 /* 5666 * Find the nth "close" core to the specified core 5667 * "close" is defined as the deepest level that shares 5668 * at least an L2 cache. With threads, this will be 5669 * threads on the same core. If the sahred cache is L3 5670 * or higher, simply returns the same core. 5671 */ 5672 static int 5673 find_close_core(int cpu, int core_offset) 5674 { 5675 struct cpu_group *grp; 5676 int i; 5677 int fcpu; 5678 cpuset_t cs; 5679 5680 grp = cpu_top; 5681 if (grp == NULL) 5682 return cpu; 5683 i = 0; 5684 while ((i = find_child_with_core(cpu, grp)) != -1) { 5685 /* If the child only has one cpu, don't descend */ 5686 if (grp->cg_child[i].cg_count <= 1) 5687 break; 5688 grp = &grp->cg_child[i]; 5689 } 5690 5691 /* If they don't share at least an L2 cache, use the same CPU */ 5692 if (grp->cg_level > CG_SHARE_L2 || grp->cg_level == CG_SHARE_NONE) 5693 return cpu; 5694 5695 /* Now pick one */ 5696 CPU_COPY(&grp->cg_mask, &cs); 5697 5698 /* Add the selected CPU offset to core offset. */ 5699 for (i = 0; (fcpu = CPU_FFS(&cs)) != 0; i++) { 5700 if (fcpu - 1 == cpu) 5701 break; 5702 CPU_CLR(fcpu - 1, &cs); 5703 } 5704 MPASS(fcpu); 5705 5706 core_offset += i; 5707 5708 CPU_COPY(&grp->cg_mask, &cs); 5709 for (i = core_offset % grp->cg_count; i > 0; i--) { 5710 MPASS(CPU_FFS(&cs)); 5711 CPU_CLR(CPU_FFS(&cs) - 1, &cs); 5712 } 5713 MPASS(CPU_FFS(&cs)); 5714 return CPU_FFS(&cs) - 1; 5715 } 5716 #else 5717 static int 5718 find_close_core(int cpu, int core_offset __unused) 5719 { 5720 return cpu; 5721 } 5722 #endif 5723 5724 static int 5725 get_core_offset(if_ctx_t ctx, iflib_intr_type_t type, int qid) 5726 { 5727 switch (type) { 5728 case IFLIB_INTR_TX: 5729 /* TX queues get cores which share at least an L2 cache with the corresponding RX queue */ 5730 /* XXX handle multiple RX threads per core and more than two core per L2 group */ 5731 return qid / CPU_COUNT(&ctx->ifc_cpus) + 1; 5732 case IFLIB_INTR_RX: 5733 case IFLIB_INTR_RXTX: 5734 /* RX queues get the specified core */ 5735 return qid / CPU_COUNT(&ctx->ifc_cpus); 5736 default: 5737 return -1; 5738 } 5739 } 5740 #else 5741 #define get_core_offset(ctx, type, qid) CPU_FIRST() 5742 #define find_close_core(cpuid, tid) CPU_FIRST() 5743 #define find_nth(ctx, gid) CPU_FIRST() 5744 #endif 5745 5746 /* Just to avoid copy/paste */ 5747 static inline int 5748 iflib_irq_set_affinity(if_ctx_t ctx, int irq, iflib_intr_type_t type, int qid, 5749 struct grouptask *gtask, struct taskqgroup *tqg, void *uniq, const char *name) 5750 { 5751 int cpuid; 5752 int err, tid; 5753 5754 cpuid = find_nth(ctx, qid); 5755 tid = get_core_offset(ctx, type, qid); 5756 MPASS(tid >= 0); 5757 cpuid = find_close_core(cpuid, tid); 5758 err = taskqgroup_attach_cpu(tqg, gtask, uniq, cpuid, irq, name); 5759 if (err) { 5760 device_printf(ctx->ifc_dev, "taskqgroup_attach_cpu failed %d\n", err); 5761 return (err); 5762 } 5763 #ifdef notyet 5764 if (cpuid > ctx->ifc_cpuid_highest) 5765 ctx->ifc_cpuid_highest = cpuid; 5766 #endif 5767 return 0; 5768 } 5769 5770 int 5771 iflib_irq_alloc_generic(if_ctx_t ctx, if_irq_t irq, int rid, 5772 iflib_intr_type_t type, driver_filter_t *filter, 5773 void *filter_arg, int qid, const char *name) 5774 { 5775 struct grouptask *gtask; 5776 struct taskqgroup *tqg; 5777 iflib_filter_info_t info; 5778 gtask_fn_t *fn; 5779 int tqrid, err; 5780 driver_filter_t *intr_fast; 5781 void *q; 5782 5783 info = &ctx->ifc_filter_info; 5784 tqrid = rid; 5785 5786 switch (type) { 5787 /* XXX merge tx/rx for netmap? */ 5788 case IFLIB_INTR_TX: 5789 q = &ctx->ifc_txqs[qid]; 5790 info = &ctx->ifc_txqs[qid].ift_filter_info; 5791 gtask = &ctx->ifc_txqs[qid].ift_task; 5792 tqg = qgroup_if_io_tqg; 5793 fn = _task_fn_tx; 5794 intr_fast = iflib_fast_intr; 5795 GROUPTASK_INIT(gtask, 0, fn, q); 5796 ctx->ifc_flags |= IFC_NETMAP_TX_IRQ; 5797 break; 5798 case IFLIB_INTR_RX: 5799 q = &ctx->ifc_rxqs[qid]; 5800 info = &ctx->ifc_rxqs[qid].ifr_filter_info; 5801 gtask = &ctx->ifc_rxqs[qid].ifr_task; 5802 tqg = qgroup_if_io_tqg; 5803 fn = _task_fn_rx; 5804 intr_fast = iflib_fast_intr; 5805 GROUPTASK_INIT(gtask, 0, fn, q); 5806 break; 5807 case IFLIB_INTR_RXTX: 5808 q = &ctx->ifc_rxqs[qid]; 5809 info = &ctx->ifc_rxqs[qid].ifr_filter_info; 5810 gtask = &ctx->ifc_rxqs[qid].ifr_task; 5811 tqg = qgroup_if_io_tqg; 5812 fn = _task_fn_rx; 5813 intr_fast = iflib_fast_intr_rxtx; 5814 GROUPTASK_INIT(gtask, 0, fn, q); 5815 break; 5816 case IFLIB_INTR_ADMIN: 5817 q = ctx; 5818 tqrid = -1; 5819 info = &ctx->ifc_filter_info; 5820 gtask = &ctx->ifc_admin_task; 5821 tqg = qgroup_if_config_tqg; 5822 fn = _task_fn_admin; 5823 intr_fast = iflib_fast_intr_ctx; 5824 break; 5825 default: 5826 panic("unknown net intr type"); 5827 } 5828 5829 info->ifi_filter = filter; 5830 info->ifi_filter_arg = filter_arg; 5831 info->ifi_task = gtask; 5832 info->ifi_ctx = q; 5833 5834 err = _iflib_irq_alloc(ctx, irq, rid, intr_fast, NULL, info, name); 5835 if (err != 0) { 5836 device_printf(ctx->ifc_dev, "_iflib_irq_alloc failed %d\n", err); 5837 return (err); 5838 } 5839 if (type == IFLIB_INTR_ADMIN) 5840 return (0); 5841 5842 if (tqrid != -1) { 5843 err = iflib_irq_set_affinity(ctx, rman_get_start(irq->ii_res), type, qid, gtask, tqg, q, name); 5844 if (err) 5845 return (err); 5846 } else { 5847 taskqgroup_attach(tqg, gtask, q, rman_get_start(irq->ii_res), name); 5848 } 5849 5850 return (0); 5851 } 5852 5853 void 5854 iflib_softirq_alloc_generic(if_ctx_t ctx, if_irq_t irq, iflib_intr_type_t type, void *arg, int qid, const char *name) 5855 { 5856 struct grouptask *gtask; 5857 struct taskqgroup *tqg; 5858 gtask_fn_t *fn; 5859 void *q; 5860 int irq_num = -1; 5861 int err; 5862 5863 switch (type) { 5864 case IFLIB_INTR_TX: 5865 q = &ctx->ifc_txqs[qid]; 5866 gtask = &ctx->ifc_txqs[qid].ift_task; 5867 tqg = qgroup_if_io_tqg; 5868 fn = _task_fn_tx; 5869 if (irq != NULL) 5870 irq_num = rman_get_start(irq->ii_res); 5871 break; 5872 case IFLIB_INTR_RX: 5873 q = &ctx->ifc_rxqs[qid]; 5874 gtask = &ctx->ifc_rxqs[qid].ifr_task; 5875 tqg = qgroup_if_io_tqg; 5876 fn = _task_fn_rx; 5877 if (irq != NULL) 5878 irq_num = rman_get_start(irq->ii_res); 5879 break; 5880 case IFLIB_INTR_IOV: 5881 q = ctx; 5882 gtask = &ctx->ifc_vflr_task; 5883 tqg = qgroup_if_config_tqg; 5884 fn = _task_fn_iov; 5885 break; 5886 default: 5887 panic("unknown net intr type"); 5888 } 5889 GROUPTASK_INIT(gtask, 0, fn, q); 5890 if (irq_num != -1) { 5891 err = iflib_irq_set_affinity(ctx, irq_num, type, qid, gtask, tqg, q, name); 5892 if (err) 5893 taskqgroup_attach(tqg, gtask, q, irq_num, name); 5894 } 5895 else { 5896 taskqgroup_attach(tqg, gtask, q, irq_num, name); 5897 } 5898 } 5899 5900 void 5901 iflib_irq_free(if_ctx_t ctx, if_irq_t irq) 5902 { 5903 if (irq->ii_tag) 5904 bus_teardown_intr(ctx->ifc_dev, irq->ii_res, irq->ii_tag); 5905 5906 if (irq->ii_res) 5907 bus_release_resource(ctx->ifc_dev, SYS_RES_IRQ, irq->ii_rid, irq->ii_res); 5908 } 5909 5910 static int 5911 iflib_legacy_setup(if_ctx_t ctx, driver_filter_t filter, void *filter_arg, int *rid, const char *name) 5912 { 5913 iflib_txq_t txq = ctx->ifc_txqs; 5914 iflib_rxq_t rxq = ctx->ifc_rxqs; 5915 if_irq_t irq = &ctx->ifc_legacy_irq; 5916 iflib_filter_info_t info; 5917 struct grouptask *gtask; 5918 struct taskqgroup *tqg; 5919 gtask_fn_t *fn; 5920 int tqrid; 5921 void *q; 5922 int err; 5923 5924 q = &ctx->ifc_rxqs[0]; 5925 info = &rxq[0].ifr_filter_info; 5926 gtask = &rxq[0].ifr_task; 5927 tqg = qgroup_if_io_tqg; 5928 tqrid = irq->ii_rid = *rid; 5929 fn = _task_fn_rx; 5930 5931 ctx->ifc_flags |= IFC_LEGACY; 5932 info->ifi_filter = filter; 5933 info->ifi_filter_arg = filter_arg; 5934 info->ifi_task = gtask; 5935 info->ifi_ctx = ctx; 5936 5937 /* We allocate a single interrupt resource */ 5938 if ((err = _iflib_irq_alloc(ctx, irq, tqrid, iflib_fast_intr_ctx, NULL, info, name)) != 0) 5939 return (err); 5940 GROUPTASK_INIT(gtask, 0, fn, q); 5941 taskqgroup_attach(tqg, gtask, q, rman_get_start(irq->ii_res), name); 5942 5943 GROUPTASK_INIT(&txq->ift_task, 0, _task_fn_tx, txq); 5944 taskqgroup_attach(qgroup_if_io_tqg, &txq->ift_task, txq, rman_get_start(irq->ii_res), "tx"); 5945 return (0); 5946 } 5947 5948 void 5949 iflib_led_create(if_ctx_t ctx) 5950 { 5951 5952 ctx->ifc_led_dev = led_create(iflib_led_func, ctx, 5953 device_get_nameunit(ctx->ifc_dev)); 5954 } 5955 5956 void 5957 iflib_tx_intr_deferred(if_ctx_t ctx, int txqid) 5958 { 5959 5960 GROUPTASK_ENQUEUE(&ctx->ifc_txqs[txqid].ift_task); 5961 } 5962 5963 void 5964 iflib_rx_intr_deferred(if_ctx_t ctx, int rxqid) 5965 { 5966 5967 GROUPTASK_ENQUEUE(&ctx->ifc_rxqs[rxqid].ifr_task); 5968 } 5969 5970 void 5971 iflib_admin_intr_deferred(if_ctx_t ctx) 5972 { 5973 #ifdef INVARIANTS 5974 struct grouptask *gtask; 5975 5976 gtask = &ctx->ifc_admin_task; 5977 MPASS(gtask != NULL && gtask->gt_taskqueue != NULL); 5978 #endif 5979 5980 GROUPTASK_ENQUEUE(&ctx->ifc_admin_task); 5981 } 5982 5983 void 5984 iflib_iov_intr_deferred(if_ctx_t ctx) 5985 { 5986 5987 GROUPTASK_ENQUEUE(&ctx->ifc_vflr_task); 5988 } 5989 5990 void 5991 iflib_io_tqg_attach(struct grouptask *gt, void *uniq, int cpu, char *name) 5992 { 5993 5994 taskqgroup_attach_cpu(qgroup_if_io_tqg, gt, uniq, cpu, -1, name); 5995 } 5996 5997 void 5998 iflib_config_gtask_init(void *ctx, struct grouptask *gtask, gtask_fn_t *fn, 5999 const char *name) 6000 { 6001 6002 GROUPTASK_INIT(gtask, 0, fn, ctx); 6003 taskqgroup_attach(qgroup_if_config_tqg, gtask, gtask, -1, name); 6004 } 6005 6006 void 6007 iflib_config_gtask_deinit(struct grouptask *gtask) 6008 { 6009 6010 taskqgroup_detach(qgroup_if_config_tqg, gtask); 6011 } 6012 6013 void 6014 iflib_link_state_change(if_ctx_t ctx, int link_state, uint64_t baudrate) 6015 { 6016 if_t ifp = ctx->ifc_ifp; 6017 iflib_txq_t txq = ctx->ifc_txqs; 6018 6019 if_setbaudrate(ifp, baudrate); 6020 if (baudrate >= IF_Gbps(10)) { 6021 STATE_LOCK(ctx); 6022 ctx->ifc_flags |= IFC_PREFETCH; 6023 STATE_UNLOCK(ctx); 6024 } 6025 /* If link down, disable watchdog */ 6026 if ((ctx->ifc_link_state == LINK_STATE_UP) && (link_state == LINK_STATE_DOWN)) { 6027 for (int i = 0; i < ctx->ifc_softc_ctx.isc_ntxqsets; i++, txq++) 6028 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 6029 } 6030 ctx->ifc_link_state = link_state; 6031 if_link_state_change(ifp, link_state); 6032 } 6033 6034 static int 6035 iflib_tx_credits_update(if_ctx_t ctx, iflib_txq_t txq) 6036 { 6037 int credits; 6038 #ifdef INVARIANTS 6039 int credits_pre = txq->ift_cidx_processed; 6040 #endif 6041 6042 if (ctx->isc_txd_credits_update == NULL) 6043 return (0); 6044 6045 if ((credits = ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, true)) == 0) 6046 return (0); 6047 6048 txq->ift_processed += credits; 6049 txq->ift_cidx_processed += credits; 6050 6051 MPASS(credits_pre + credits == txq->ift_cidx_processed); 6052 if (txq->ift_cidx_processed >= txq->ift_size) 6053 txq->ift_cidx_processed -= txq->ift_size; 6054 return (credits); 6055 } 6056 6057 static int 6058 iflib_rxd_avail(if_ctx_t ctx, iflib_rxq_t rxq, qidx_t cidx, qidx_t budget) 6059 { 6060 6061 return (ctx->isc_rxd_available(ctx->ifc_softc, rxq->ifr_id, cidx, 6062 budget)); 6063 } 6064 6065 void 6066 iflib_add_int_delay_sysctl(if_ctx_t ctx, const char *name, 6067 const char *description, if_int_delay_info_t info, 6068 int offset, int value) 6069 { 6070 info->iidi_ctx = ctx; 6071 info->iidi_offset = offset; 6072 info->iidi_value = value; 6073 SYSCTL_ADD_PROC(device_get_sysctl_ctx(ctx->ifc_dev), 6074 SYSCTL_CHILDREN(device_get_sysctl_tree(ctx->ifc_dev)), 6075 OID_AUTO, name, CTLTYPE_INT|CTLFLAG_RW, 6076 info, 0, iflib_sysctl_int_delay, "I", description); 6077 } 6078 6079 struct sx * 6080 iflib_ctx_lock_get(if_ctx_t ctx) 6081 { 6082 6083 return (&ctx->ifc_ctx_sx); 6084 } 6085 6086 static int 6087 iflib_msix_init(if_ctx_t ctx) 6088 { 6089 device_t dev = ctx->ifc_dev; 6090 if_shared_ctx_t sctx = ctx->ifc_sctx; 6091 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 6092 int vectors, queues, rx_queues, tx_queues, queuemsgs, msgs; 6093 int iflib_num_tx_queues, iflib_num_rx_queues; 6094 int err, admincnt, bar; 6095 6096 iflib_num_tx_queues = ctx->ifc_sysctl_ntxqs; 6097 iflib_num_rx_queues = ctx->ifc_sysctl_nrxqs; 6098 6099 device_printf(dev, "msix_init qsets capped at %d\n", imax(scctx->isc_ntxqsets, scctx->isc_nrxqsets)); 6100 6101 bar = ctx->ifc_softc_ctx.isc_msix_bar; 6102 admincnt = sctx->isc_admin_intrcnt; 6103 /* Override by tuneable */ 6104 if (scctx->isc_disable_msix) 6105 goto msi; 6106 6107 /* 6108 * bar == -1 => "trust me I know what I'm doing" 6109 * Some drivers are for hardware that is so shoddily 6110 * documented that no one knows which bars are which 6111 * so the developer has to map all bars. This hack 6112 * allows shoddy garbage to use msix in this framework. 6113 */ 6114 if (bar != -1) { 6115 ctx->ifc_msix_mem = bus_alloc_resource_any(dev, 6116 SYS_RES_MEMORY, &bar, RF_ACTIVE); 6117 if (ctx->ifc_msix_mem == NULL) { 6118 /* May not be enabled */ 6119 device_printf(dev, "Unable to map MSIX table \n"); 6120 goto msi; 6121 } 6122 } 6123 /* First try MSI/X */ 6124 if ((msgs = pci_msix_count(dev)) == 0) { /* system has msix disabled */ 6125 device_printf(dev, "System has MSIX disabled \n"); 6126 bus_release_resource(dev, SYS_RES_MEMORY, 6127 bar, ctx->ifc_msix_mem); 6128 ctx->ifc_msix_mem = NULL; 6129 goto msi; 6130 } 6131 #if IFLIB_DEBUG 6132 /* use only 1 qset in debug mode */ 6133 queuemsgs = min(msgs - admincnt, 1); 6134 #else 6135 queuemsgs = msgs - admincnt; 6136 #endif 6137 #ifdef RSS 6138 queues = imin(queuemsgs, rss_getnumbuckets()); 6139 #else 6140 queues = queuemsgs; 6141 #endif 6142 queues = imin(CPU_COUNT(&ctx->ifc_cpus), queues); 6143 device_printf(dev, "pxm cpus: %d queue msgs: %d admincnt: %d\n", 6144 CPU_COUNT(&ctx->ifc_cpus), queuemsgs, admincnt); 6145 #ifdef RSS 6146 /* If we're doing RSS, clamp at the number of RSS buckets */ 6147 if (queues > rss_getnumbuckets()) 6148 queues = rss_getnumbuckets(); 6149 #endif 6150 if (iflib_num_rx_queues > 0 && iflib_num_rx_queues < queuemsgs - admincnt) 6151 rx_queues = iflib_num_rx_queues; 6152 else 6153 rx_queues = queues; 6154 6155 if (rx_queues > scctx->isc_nrxqsets) 6156 rx_queues = scctx->isc_nrxqsets; 6157 6158 /* 6159 * We want this to be all logical CPUs by default 6160 */ 6161 if (iflib_num_tx_queues > 0 && iflib_num_tx_queues < queues) 6162 tx_queues = iflib_num_tx_queues; 6163 else 6164 tx_queues = mp_ncpus; 6165 6166 if (tx_queues > scctx->isc_ntxqsets) 6167 tx_queues = scctx->isc_ntxqsets; 6168 6169 if (ctx->ifc_sysctl_qs_eq_override == 0) { 6170 #ifdef INVARIANTS 6171 if (tx_queues != rx_queues) 6172 device_printf(dev, 6173 "queue equality override not set, capping rx_queues at %d and tx_queues at %d\n", 6174 min(rx_queues, tx_queues), min(rx_queues, tx_queues)); 6175 #endif 6176 tx_queues = min(rx_queues, tx_queues); 6177 rx_queues = min(rx_queues, tx_queues); 6178 } 6179 6180 device_printf(dev, "using %d rx queues %d tx queues \n", rx_queues, tx_queues); 6181 6182 vectors = rx_queues + admincnt; 6183 if ((err = pci_alloc_msix(dev, &vectors)) == 0) { 6184 device_printf(dev, "Using MSIX interrupts with %d vectors\n", vectors); 6185 scctx->isc_vectors = vectors; 6186 scctx->isc_nrxqsets = rx_queues; 6187 scctx->isc_ntxqsets = tx_queues; 6188 scctx->isc_intr = IFLIB_INTR_MSIX; 6189 6190 return (vectors); 6191 } else { 6192 device_printf(dev, 6193 "failed to allocate %d msix vectors, err: %d - using MSI\n", vectors, err); 6194 bus_release_resource(dev, SYS_RES_MEMORY, bar, 6195 ctx->ifc_msix_mem); 6196 ctx->ifc_msix_mem = NULL; 6197 } 6198 msi: 6199 vectors = pci_msi_count(dev); 6200 scctx->isc_nrxqsets = 1; 6201 scctx->isc_ntxqsets = 1; 6202 scctx->isc_vectors = vectors; 6203 if (vectors == 1 && pci_alloc_msi(dev, &vectors) == 0) { 6204 device_printf(dev,"Using an MSI interrupt\n"); 6205 scctx->isc_intr = IFLIB_INTR_MSI; 6206 } else { 6207 scctx->isc_vectors = 1; 6208 device_printf(dev,"Using a Legacy interrupt\n"); 6209 scctx->isc_intr = IFLIB_INTR_LEGACY; 6210 } 6211 6212 return (vectors); 6213 } 6214 6215 static const char *ring_states[] = { "IDLE", "BUSY", "STALLED", "ABDICATED" }; 6216 6217 static int 6218 mp_ring_state_handler(SYSCTL_HANDLER_ARGS) 6219 { 6220 int rc; 6221 uint16_t *state = ((uint16_t *)oidp->oid_arg1); 6222 struct sbuf *sb; 6223 const char *ring_state = "UNKNOWN"; 6224 6225 /* XXX needed ? */ 6226 rc = sysctl_wire_old_buffer(req, 0); 6227 MPASS(rc == 0); 6228 if (rc != 0) 6229 return (rc); 6230 sb = sbuf_new_for_sysctl(NULL, NULL, 80, req); 6231 MPASS(sb != NULL); 6232 if (sb == NULL) 6233 return (ENOMEM); 6234 if (state[3] <= 3) 6235 ring_state = ring_states[state[3]]; 6236 6237 sbuf_printf(sb, "pidx_head: %04hd pidx_tail: %04hd cidx: %04hd state: %s", 6238 state[0], state[1], state[2], ring_state); 6239 rc = sbuf_finish(sb); 6240 sbuf_delete(sb); 6241 return(rc); 6242 } 6243 6244 enum iflib_ndesc_handler { 6245 IFLIB_NTXD_HANDLER, 6246 IFLIB_NRXD_HANDLER, 6247 }; 6248 6249 static int 6250 mp_ndesc_handler(SYSCTL_HANDLER_ARGS) 6251 { 6252 if_ctx_t ctx = (void *)arg1; 6253 enum iflib_ndesc_handler type = arg2; 6254 char buf[256] = {0}; 6255 qidx_t *ndesc; 6256 char *p, *next; 6257 int nqs, rc, i; 6258 6259 MPASS(type == IFLIB_NTXD_HANDLER || type == IFLIB_NRXD_HANDLER); 6260 6261 nqs = 8; 6262 switch(type) { 6263 case IFLIB_NTXD_HANDLER: 6264 ndesc = ctx->ifc_sysctl_ntxds; 6265 if (ctx->ifc_sctx) 6266 nqs = ctx->ifc_sctx->isc_ntxqs; 6267 break; 6268 case IFLIB_NRXD_HANDLER: 6269 ndesc = ctx->ifc_sysctl_nrxds; 6270 if (ctx->ifc_sctx) 6271 nqs = ctx->ifc_sctx->isc_nrxqs; 6272 break; 6273 default: 6274 panic("unhandled type"); 6275 } 6276 if (nqs == 0) 6277 nqs = 8; 6278 6279 for (i=0; i<8; i++) { 6280 if (i >= nqs) 6281 break; 6282 if (i) 6283 strcat(buf, ","); 6284 sprintf(strchr(buf, 0), "%d", ndesc[i]); 6285 } 6286 6287 rc = sysctl_handle_string(oidp, buf, sizeof(buf), req); 6288 if (rc || req->newptr == NULL) 6289 return rc; 6290 6291 for (i = 0, next = buf, p = strsep(&next, " ,"); i < 8 && p; 6292 i++, p = strsep(&next, " ,")) { 6293 ndesc[i] = strtoul(p, NULL, 10); 6294 } 6295 6296 return(rc); 6297 } 6298 6299 #define NAME_BUFLEN 32 6300 static void 6301 iflib_add_device_sysctl_pre(if_ctx_t ctx) 6302 { 6303 device_t dev = iflib_get_dev(ctx); 6304 struct sysctl_oid_list *child, *oid_list; 6305 struct sysctl_ctx_list *ctx_list; 6306 struct sysctl_oid *node; 6307 6308 ctx_list = device_get_sysctl_ctx(dev); 6309 child = SYSCTL_CHILDREN(device_get_sysctl_tree(dev)); 6310 ctx->ifc_sysctl_node = node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, "iflib", 6311 CTLFLAG_RD, NULL, "IFLIB fields"); 6312 oid_list = SYSCTL_CHILDREN(node); 6313 6314 SYSCTL_ADD_STRING(ctx_list, oid_list, OID_AUTO, "driver_version", 6315 CTLFLAG_RD, ctx->ifc_sctx->isc_driver_version, 0, 6316 "driver version"); 6317 6318 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_ntxqs", 6319 CTLFLAG_RWTUN, &ctx->ifc_sysctl_ntxqs, 0, 6320 "# of txqs to use, 0 => use default #"); 6321 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_nrxqs", 6322 CTLFLAG_RWTUN, &ctx->ifc_sysctl_nrxqs, 0, 6323 "# of rxqs to use, 0 => use default #"); 6324 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_qs_enable", 6325 CTLFLAG_RWTUN, &ctx->ifc_sysctl_qs_eq_override, 0, 6326 "permit #txq != #rxq"); 6327 SYSCTL_ADD_INT(ctx_list, oid_list, OID_AUTO, "disable_msix", 6328 CTLFLAG_RWTUN, &ctx->ifc_softc_ctx.isc_disable_msix, 0, 6329 "disable MSIX (default 0)"); 6330 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "rx_budget", 6331 CTLFLAG_RWTUN, &ctx->ifc_sysctl_rx_budget, 0, 6332 "set the rx budget"); 6333 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "tx_abdicate", 6334 CTLFLAG_RWTUN, &ctx->ifc_sysctl_tx_abdicate, 0, 6335 "cause tx to abdicate instead of running to completion"); 6336 6337 /* XXX change for per-queue sizes */ 6338 SYSCTL_ADD_PROC(ctx_list, oid_list, OID_AUTO, "override_ntxds", 6339 CTLTYPE_STRING|CTLFLAG_RWTUN, ctx, IFLIB_NTXD_HANDLER, 6340 mp_ndesc_handler, "A", 6341 "list of # of tx descriptors to use, 0 = use default #"); 6342 SYSCTL_ADD_PROC(ctx_list, oid_list, OID_AUTO, "override_nrxds", 6343 CTLTYPE_STRING|CTLFLAG_RWTUN, ctx, IFLIB_NRXD_HANDLER, 6344 mp_ndesc_handler, "A", 6345 "list of # of rx descriptors to use, 0 = use default #"); 6346 } 6347 6348 static void 6349 iflib_add_device_sysctl_post(if_ctx_t ctx) 6350 { 6351 if_shared_ctx_t sctx = ctx->ifc_sctx; 6352 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 6353 device_t dev = iflib_get_dev(ctx); 6354 struct sysctl_oid_list *child; 6355 struct sysctl_ctx_list *ctx_list; 6356 iflib_fl_t fl; 6357 iflib_txq_t txq; 6358 iflib_rxq_t rxq; 6359 int i, j; 6360 char namebuf[NAME_BUFLEN]; 6361 char *qfmt; 6362 struct sysctl_oid *queue_node, *fl_node, *node; 6363 struct sysctl_oid_list *queue_list, *fl_list; 6364 ctx_list = device_get_sysctl_ctx(dev); 6365 6366 node = ctx->ifc_sysctl_node; 6367 child = SYSCTL_CHILDREN(node); 6368 6369 if (scctx->isc_ntxqsets > 100) 6370 qfmt = "txq%03d"; 6371 else if (scctx->isc_ntxqsets > 10) 6372 qfmt = "txq%02d"; 6373 else 6374 qfmt = "txq%d"; 6375 for (i = 0, txq = ctx->ifc_txqs; i < scctx->isc_ntxqsets; i++, txq++) { 6376 snprintf(namebuf, NAME_BUFLEN, qfmt, i); 6377 queue_node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, namebuf, 6378 CTLFLAG_RD, NULL, "Queue Name"); 6379 queue_list = SYSCTL_CHILDREN(queue_node); 6380 #if MEMORY_LOGGING 6381 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_dequeued", 6382 CTLFLAG_RD, 6383 &txq->ift_dequeued, "total mbufs freed"); 6384 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_enqueued", 6385 CTLFLAG_RD, 6386 &txq->ift_enqueued, "total mbufs enqueued"); 6387 #endif 6388 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "mbuf_defrag", 6389 CTLFLAG_RD, 6390 &txq->ift_mbuf_defrag, "# of times m_defrag was called"); 6391 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "m_pullups", 6392 CTLFLAG_RD, 6393 &txq->ift_pullups, "# of times m_pullup was called"); 6394 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "mbuf_defrag_failed", 6395 CTLFLAG_RD, 6396 &txq->ift_mbuf_defrag_failed, "# of times m_defrag failed"); 6397 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "no_desc_avail", 6398 CTLFLAG_RD, 6399 &txq->ift_no_desc_avail, "# of times no descriptors were available"); 6400 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "tx_map_failed", 6401 CTLFLAG_RD, 6402 &txq->ift_map_failed, "# of times dma map failed"); 6403 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txd_encap_efbig", 6404 CTLFLAG_RD, 6405 &txq->ift_txd_encap_efbig, "# of times txd_encap returned EFBIG"); 6406 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "no_tx_dma_setup", 6407 CTLFLAG_RD, 6408 &txq->ift_no_tx_dma_setup, "# of times map failed for other than EFBIG"); 6409 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_pidx", 6410 CTLFLAG_RD, 6411 &txq->ift_pidx, 1, "Producer Index"); 6412 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_cidx", 6413 CTLFLAG_RD, 6414 &txq->ift_cidx, 1, "Consumer Index"); 6415 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_cidx_processed", 6416 CTLFLAG_RD, 6417 &txq->ift_cidx_processed, 1, "Consumer Index seen by credit update"); 6418 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_in_use", 6419 CTLFLAG_RD, 6420 &txq->ift_in_use, 1, "descriptors in use"); 6421 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_processed", 6422 CTLFLAG_RD, 6423 &txq->ift_processed, "descriptors procesed for clean"); 6424 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_cleaned", 6425 CTLFLAG_RD, 6426 &txq->ift_cleaned, "total cleaned"); 6427 SYSCTL_ADD_PROC(ctx_list, queue_list, OID_AUTO, "ring_state", 6428 CTLTYPE_STRING | CTLFLAG_RD, __DEVOLATILE(uint64_t *, &txq->ift_br->state), 6429 0, mp_ring_state_handler, "A", "soft ring state"); 6430 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_enqueues", 6431 CTLFLAG_RD, &txq->ift_br->enqueues, 6432 "# of enqueues to the mp_ring for this queue"); 6433 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_drops", 6434 CTLFLAG_RD, &txq->ift_br->drops, 6435 "# of drops in the mp_ring for this queue"); 6436 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_starts", 6437 CTLFLAG_RD, &txq->ift_br->starts, 6438 "# of normal consumer starts in the mp_ring for this queue"); 6439 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_stalls", 6440 CTLFLAG_RD, &txq->ift_br->stalls, 6441 "# of consumer stalls in the mp_ring for this queue"); 6442 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_restarts", 6443 CTLFLAG_RD, &txq->ift_br->restarts, 6444 "# of consumer restarts in the mp_ring for this queue"); 6445 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_abdications", 6446 CTLFLAG_RD, &txq->ift_br->abdications, 6447 "# of consumer abdications in the mp_ring for this queue"); 6448 } 6449 6450 if (scctx->isc_nrxqsets > 100) 6451 qfmt = "rxq%03d"; 6452 else if (scctx->isc_nrxqsets > 10) 6453 qfmt = "rxq%02d"; 6454 else 6455 qfmt = "rxq%d"; 6456 for (i = 0, rxq = ctx->ifc_rxqs; i < scctx->isc_nrxqsets; i++, rxq++) { 6457 snprintf(namebuf, NAME_BUFLEN, qfmt, i); 6458 queue_node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, namebuf, 6459 CTLFLAG_RD, NULL, "Queue Name"); 6460 queue_list = SYSCTL_CHILDREN(queue_node); 6461 if (sctx->isc_flags & IFLIB_HAS_RXCQ) { 6462 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "rxq_cq_pidx", 6463 CTLFLAG_RD, 6464 &rxq->ifr_cq_pidx, 1, "Producer Index"); 6465 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "rxq_cq_cidx", 6466 CTLFLAG_RD, 6467 &rxq->ifr_cq_cidx, 1, "Consumer Index"); 6468 } 6469 6470 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) { 6471 snprintf(namebuf, NAME_BUFLEN, "rxq_fl%d", j); 6472 fl_node = SYSCTL_ADD_NODE(ctx_list, queue_list, OID_AUTO, namebuf, 6473 CTLFLAG_RD, NULL, "freelist Name"); 6474 fl_list = SYSCTL_CHILDREN(fl_node); 6475 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "pidx", 6476 CTLFLAG_RD, 6477 &fl->ifl_pidx, 1, "Producer Index"); 6478 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "cidx", 6479 CTLFLAG_RD, 6480 &fl->ifl_cidx, 1, "Consumer Index"); 6481 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "credits", 6482 CTLFLAG_RD, 6483 &fl->ifl_credits, 1, "credits available"); 6484 #if MEMORY_LOGGING 6485 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_m_enqueued", 6486 CTLFLAG_RD, 6487 &fl->ifl_m_enqueued, "mbufs allocated"); 6488 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_m_dequeued", 6489 CTLFLAG_RD, 6490 &fl->ifl_m_dequeued, "mbufs freed"); 6491 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_cl_enqueued", 6492 CTLFLAG_RD, 6493 &fl->ifl_cl_enqueued, "clusters allocated"); 6494 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_cl_dequeued", 6495 CTLFLAG_RD, 6496 &fl->ifl_cl_dequeued, "clusters freed"); 6497 #endif 6498 6499 } 6500 } 6501 6502 } 6503 6504 void 6505 iflib_request_reset(if_ctx_t ctx) 6506 { 6507 6508 STATE_LOCK(ctx); 6509 ctx->ifc_flags |= IFC_DO_RESET; 6510 STATE_UNLOCK(ctx); 6511 } 6512 6513 #ifndef __NO_STRICT_ALIGNMENT 6514 static struct mbuf * 6515 iflib_fixup_rx(struct mbuf *m) 6516 { 6517 struct mbuf *n; 6518 6519 if (m->m_len <= (MCLBYTES - ETHER_HDR_LEN)) { 6520 bcopy(m->m_data, m->m_data + ETHER_HDR_LEN, m->m_len); 6521 m->m_data += ETHER_HDR_LEN; 6522 n = m; 6523 } else { 6524 MGETHDR(n, M_NOWAIT, MT_DATA); 6525 if (n == NULL) { 6526 m_freem(m); 6527 return (NULL); 6528 } 6529 bcopy(m->m_data, n->m_data, ETHER_HDR_LEN); 6530 m->m_data += ETHER_HDR_LEN; 6531 m->m_len -= ETHER_HDR_LEN; 6532 n->m_len = ETHER_HDR_LEN; 6533 M_MOVE_PKTHDR(n, m); 6534 n->m_next = m; 6535 } 6536 return (n); 6537 } 6538 #endif 6539 6540 #ifdef NETDUMP 6541 static void 6542 iflib_netdump_init(struct ifnet *ifp, int *nrxr, int *ncl, int *clsize) 6543 { 6544 if_ctx_t ctx; 6545 6546 ctx = if_getsoftc(ifp); 6547 CTX_LOCK(ctx); 6548 *nrxr = NRXQSETS(ctx); 6549 *ncl = ctx->ifc_rxqs[0].ifr_fl->ifl_size; 6550 *clsize = ctx->ifc_rxqs[0].ifr_fl->ifl_buf_size; 6551 CTX_UNLOCK(ctx); 6552 } 6553 6554 static void 6555 iflib_netdump_event(struct ifnet *ifp, enum netdump_ev event) 6556 { 6557 if_ctx_t ctx; 6558 if_softc_ctx_t scctx; 6559 iflib_fl_t fl; 6560 iflib_rxq_t rxq; 6561 int i, j; 6562 6563 ctx = if_getsoftc(ifp); 6564 scctx = &ctx->ifc_softc_ctx; 6565 6566 switch (event) { 6567 case NETDUMP_START: 6568 for (i = 0; i < scctx->isc_nrxqsets; i++) { 6569 rxq = &ctx->ifc_rxqs[i]; 6570 for (j = 0; j < rxq->ifr_nfl; j++) { 6571 fl = rxq->ifr_fl; 6572 fl->ifl_zone = m_getzone(fl->ifl_buf_size); 6573 } 6574 } 6575 iflib_no_tx_batch = 1; 6576 break; 6577 default: 6578 break; 6579 } 6580 } 6581 6582 static int 6583 iflib_netdump_transmit(struct ifnet *ifp, struct mbuf *m) 6584 { 6585 if_ctx_t ctx; 6586 iflib_txq_t txq; 6587 int error; 6588 6589 ctx = if_getsoftc(ifp); 6590 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 6591 IFF_DRV_RUNNING) 6592 return (EBUSY); 6593 6594 txq = &ctx->ifc_txqs[0]; 6595 error = iflib_encap(txq, &m); 6596 if (error == 0) 6597 (void)iflib_txd_db_check(ctx, txq, true, txq->ift_in_use); 6598 return (error); 6599 } 6600 6601 static int 6602 iflib_netdump_poll(struct ifnet *ifp, int count) 6603 { 6604 if_ctx_t ctx; 6605 if_softc_ctx_t scctx; 6606 iflib_txq_t txq; 6607 int i; 6608 6609 ctx = if_getsoftc(ifp); 6610 scctx = &ctx->ifc_softc_ctx; 6611 6612 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 6613 IFF_DRV_RUNNING) 6614 return (EBUSY); 6615 6616 txq = &ctx->ifc_txqs[0]; 6617 (void)iflib_completed_tx_reclaim(txq, RECLAIM_THRESH(ctx)); 6618 6619 for (i = 0; i < scctx->isc_nrxqsets; i++) 6620 (void)iflib_rxeof(&ctx->ifc_rxqs[i], 16 /* XXX */); 6621 return (0); 6622 } 6623 #endif /* NETDUMP */
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