Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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sys/net/sff8472.h
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1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2013 George V. Neville-Neil 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 * $FreeBSD$ 29 */ 30 31 /* 32 * The following set of constants are from Document SFF-8472 33 * "Diagnostic Monitoring Interface for Optical Transceivers" revision 34 * 11.3 published by the SFF Committee on June 11, 2013 35 * 36 * The SFF standard defines two ranges of addresses, each 255 bytes 37 * long for the storage of data and diagnostics on cables, such as 38 * SFP+ optics and TwinAx cables. The ranges are defined in the 39 * following way: 40 * 41 * Base Address 0xa0 (Identification Data) 42 * 0-95 Serial ID Defined by SFP MSA 43 * 96-127 Vendor Specific Data 44 * 128-255 Reserved 45 * 46 * Base Address 0xa2 (Diagnostic Data) 47 * 0-55 Alarm and Warning Thresholds 48 * 56-95 Cal Constants 49 * 96-119 Real Time Diagnostic Interface 50 * 120-127 Vendor Specific 51 * 128-247 User Writable EEPROM 52 * 248-255 Vendor Specific 53 * 54 * Note that not all addresses are supported. Where support is 55 * optional this is noted and instructions for checking for the 56 * support are supplied. 57 * 58 * All these values are read across an I2C (i squared C) bus. Any 59 * device wishing to read these addresses must first have support for 60 * i2c calls. The Chelsio T4/T5 driver (dev/cxgbe) is one such 61 * driver. 62 */ 63 64 /* Table 3.1 Two-wire interface ID: Data Fields */ 65 66 enum { 67 SFF_8472_BASE = 0xa0, /* Base address for all our queries. */ 68 SFF_8472_ID = 0, /* Transceiver Type (Table 3.2) */ 69 SFF_8472_EXT_ID = 1, /* Extended transceiver type (Table 3.3) */ 70 SFF_8472_CONNECTOR = 2, /* Connector type (Table 3.4) */ 71 SFF_8472_TRANS_START = 3, /* Elec or Optical Compatibility 72 * (Table 3.5) */ 73 SFF_8472_TRANS_END = 10, 74 SFF_8472_ENCODING = 11, /* Encoding Code for high speed 75 * serial encoding algorithm (see 76 * Table 3.6) */ 77 SFF_8472_BITRATE = 12, /* Nominal signaling rate, units 78 * of 100MBd. (see details for 79 * rates > 25.0Gb/s) */ 80 SFF_8472_RATEID = 13, /* Type of rate select 81 * functionality (see Table 82 * 3.6a) */ 83 SFF_8472_LEN_SMF_KM = 14, /* Link length supported for single 84 * mode fiber, units of km */ 85 SFF_8472_LEN_SMF = 15, /* Link length supported for single 86 * mode fiber, units of 100 m */ 87 SFF_8472_LEN_50UM = 16, /* Link length supported for 50 um 88 * OM2 fiber, units of 10 m */ 89 SFF_8472_LEN_625UM = 17, /* Link length supported for 62.5 90 * um OM1 fiber, units of 10 m */ 91 SFF_8472_LEN_OM4 = 18, /* Link length supported for 50um 92 * OM4 fiber, units of 10m. 93 * Alternatively copper or direct 94 * attach cable, units of m */ 95 SFF_8472_LEN_OM3 = 19, /* Link length supported for 50 um OM3 fiber, units of 10 m */ 96 SFF_8472_VENDOR_START = 20, /* Vendor name [Address A0h, Bytes 97 * 20-35] */ 98 SFF_8472_VENDOR_END = 35, 99 SFF_8472_TRANS = 36, /* Transceiver Code for electronic 100 * or optical compatibility (see 101 * Table 3.5) */ 102 SFF_8472_VENDOR_OUI_START = 37, /* Vendor OUI SFP vendor IEEE 103 * company ID */ 104 SFF_8472_VENDOR_OUI_END = 39, 105 SFF_8472_PN_START = 40, /* Vendor PN */ 106 SFF_8472_PN_END = 55, 107 SFF_8472_REV_START = 56, /* Vendor Revision */ 108 SFF_8472_REV_END = 59, 109 SFF_8472_WAVELEN_START = 60, /* Wavelength Laser wavelength 110 * (Passive/Active Cable 111 * Specification Compliance) */ 112 SFF_8472_WAVELEN_END = 61, 113 SFF_8472_CC_BASE = 63, /* CC_BASE Check code for Base ID 114 * Fields (addresses 0 to 62) */ 115 116 /* 117 * Extension Fields (optional) check the options before reading other 118 * addresses. 119 */ 120 SFF_8472_OPTIONS_MSB = 64, /* Options Indicates which optional 121 * transceiver signals are 122 * implemented */ 123 SFF_8472_OPTIONS_LSB = 65, /* (see Table 3.7) */ 124 SFF_8472_BR_MAX = 66, /* BR max Upper bit rate margin, 125 * units of % (see details for 126 * rates > 25.0Gb/s) */ 127 SFF_8472_BR_MIN = 67, /* Lower bit rate margin, units of 128 * % (see details for rates > 129 * 25.0Gb/s) */ 130 SFF_8472_SN_START = 68, /* Vendor SN [Address A0h, Bytes 68-83] */ 131 SFF_8472_SN_END = 83, 132 SFF_8472_DATE_START = 84, /* Date code Vendor’s manufacturing 133 * date code (see Table 3.8) */ 134 SFF_8472_DATE_END = 91, 135 SFF_8472_DIAG_TYPE = 92, /* Diagnostic Monitoring Type 136 * Indicates which type of 137 * diagnostic monitoring is 138 * implemented (if any) in the 139 * transceiver (see Table 3.9) 140 */ 141 142 SFF_8472_ENHANCED = 93, /* Enhanced Options Indicates which 143 * optional enhanced features are 144 * implemented (if any) in the 145 * transceiver (see Table 3.10) */ 146 SFF_8472_COMPLIANCE = 94, /* SFF-8472 Compliance Indicates 147 * which revision of SFF-8472 the 148 * transceiver complies with. (see 149 * Table 3.12)*/ 150 SFF_8472_CC_EXT = 95, /* Check code for the Extended ID 151 * Fields (addresses 64 to 94) 152 */ 153 154 SFF_8472_VENDOR_RSRVD_START = 96, 155 SFF_8472_VENDOR_RSRVD_END = 127, 156 157 SFF_8472_RESERVED_START = 128, 158 SFF_8472_RESERVED_END = 255 159 }; 160 161 #define SFF_8472_DIAG_IMPL (1 << 6) /* Required to be 1 */ 162 #define SFF_8472_DIAG_INTERNAL (1 << 5) /* Internal measurements. */ 163 #define SFF_8472_DIAG_EXTERNAL (1 << 4) /* External measurements. */ 164 #define SFF_8472_DIAG_POWER (1 << 3) /* Power measurement type */ 165 #define SFF_8472_DIAG_ADDR_CHG (1 << 2) /* Address change required. 166 * See SFF-8472 doc. */ 167 168 /* 169 * Diagnostics are available at the two wire address 0xa2. All 170 * diagnostics are OPTIONAL so you should check 0xa0 registers 92 to 171 * see which, if any are supported. 172 */ 173 174 enum {SFF_8472_DIAG = 0xa2}; /* Base address for diagnostics. */ 175 176 /* 177 * Table 3.15 Alarm and Warning Thresholds All values are 2 bytes 178 * and MUST be read in a single read operation starting at the MSB 179 */ 180 181 enum { 182 SFF_8472_TEMP_HIGH_ALM = 0, /* Temp High Alarm */ 183 SFF_8472_TEMP_LOW_ALM = 2, /* Temp Low Alarm */ 184 SFF_8472_TEMP_HIGH_WARN = 4, /* Temp High Warning */ 185 SFF_8472_TEMP_LOW_WARN = 6, /* Temp Low Warning */ 186 SFF_8472_VOLTAGE_HIGH_ALM = 8, /* Voltage High Alarm */ 187 SFF_8472_VOLTAGE_LOW_ALM = 10, /* Voltage Low Alarm */ 188 SFF_8472_VOLTAGE_HIGH_WARN = 12, /* Voltage High Warning */ 189 SFF_8472_VOLTAGE_LOW_WARN = 14, /* Voltage Low Warning */ 190 SFF_8472_BIAS_HIGH_ALM = 16, /* Bias High Alarm */ 191 SFF_8472_BIAS_LOW_ALM = 18, /* Bias Low Alarm */ 192 SFF_8472_BIAS_HIGH_WARN = 20, /* Bias High Warning */ 193 SFF_8472_BIAS_LOW_WARN = 22, /* Bias Low Warning */ 194 SFF_8472_TX_POWER_HIGH_ALM = 24, /* TX Power High Alarm */ 195 SFF_8472_TX_POWER_LOW_ALM = 26, /* TX Power Low Alarm */ 196 SFF_8472_TX_POWER_HIGH_WARN = 28, /* TX Power High Warning */ 197 SFF_8472_TX_POWER_LOW_WARN = 30, /* TX Power Low Warning */ 198 SFF_8472_RX_POWER_HIGH_ALM = 32, /* RX Power High Alarm */ 199 SFF_8472_RX_POWER_LOW_ALM = 34, /* RX Power Low Alarm */ 200 SFF_8472_RX_POWER_HIGH_WARN = 36, /* RX Power High Warning */ 201 SFF_8472_RX_POWER_LOW_WARN = 38, /* RX Power Low Warning */ 202 203 SFF_8472_RX_POWER4 = 56, /* Rx_PWR(4) Single precision 204 * floating point calibration data 205 * - Rx optical power. Bit 7 of 206 * byte 56 is MSB. Bit 0 of byte 207 * 59 is LSB. Rx_PWR(4) should be 208 * set to zero for “internally 209 * calibrated” devices. */ 210 SFF_8472_RX_POWER3 = 60, /* Rx_PWR(3) Single precision 211 * floating point calibration data 212 * - Rx optical power. Bit 7 of 213 * byte 60 is MSB. Bit 0 of byte 63 214 * is LSB. Rx_PWR(3) should be set 215 * to zero for “internally 216 * calibrated” devices.*/ 217 SFF_8472_RX_POWER2 = 64, /* Rx_PWR(2) Single precision 218 * floating point calibration data, 219 * Rx optical power. Bit 7 of byte 220 * 64 is MSB, bit 0 of byte 67 is 221 * LSB. Rx_PWR(2) should be set to 222 * zero for “internally calibrated” 223 * devices. */ 224 SFF_8472_RX_POWER1 = 68, /* Rx_PWR(1) Single precision 225 * floating point calibration data, 226 * Rx optical power. Bit 7 of byte 227 * 68 is MSB, bit 0 of byte 71 is 228 * LSB. Rx_PWR(1) should be set to 229 * 1 for “internally calibrated” 230 * devices. */ 231 SFF_8472_RX_POWER0 = 72, /* Rx_PWR(0) Single precision 232 * floating point calibration data, 233 * Rx optical power. Bit 7 of byte 234 * 72 is MSB, bit 0 of byte 75 is 235 * LSB. Rx_PWR(0) should be set to 236 * zero for “internally calibrated” 237 * devices. */ 238 SFF_8472_TX_I_SLOPE = 76, /* Tx_I(Slope) Fixed decimal 239 * (unsigned) calibration data, 240 * laser bias current. Bit 7 of 241 * byte 76 is MSB, bit 0 of byte 77 242 * is LSB. Tx_I(Slope) should be 243 * set to 1 for “internally 244 * calibrated” devices. */ 245 SFF_8472_TX_I_OFFSET = 78, /* Tx_I(Offset) Fixed decimal 246 * (signed two’s complement) 247 * calibration data, laser bias 248 * current. Bit 7 of byte 78 is 249 * MSB, bit 0 of byte 79 is 250 * LSB. Tx_I(Offset) should be set 251 * to zero for “internally 252 * calibrated” devices. */ 253 SFF_8472_TX_POWER_SLOPE = 80, /* Tx_PWR(Slope) Fixed decimal 254 * (unsigned) calibration data, 255 * transmitter coupled output 256 * power. Bit 7 of byte 80 is MSB, 257 * bit 0 of byte 81 is LSB. 258 * Tx_PWR(Slope) should be set to 1 259 * for “internally calibrated” 260 * devices. */ 261 SFF_8472_TX_POWER_OFFSET = 82, /* Tx_PWR(Offset) Fixed decimal 262 * (signed two’s complement) 263 * calibration data, transmitter 264 * coupled output power. Bit 7 of 265 * byte 82 is MSB, bit 0 of byte 83 266 * is LSB. Tx_PWR(Offset) should be 267 * set to zero for “internally 268 * calibrated” devices. */ 269 SFF_8472_T_SLOPE = 84, /* T (Slope) Fixed decimal 270 * (unsigned) calibration data, 271 * internal module temperature. Bit 272 * 7 of byte 84 is MSB, bit 0 of 273 * byte 85 is LSB. T(Slope) should 274 * be set to 1 for “internally 275 * calibrated” devices. */ 276 SFF_8472_T_OFFSET = 86, /* T (Offset) Fixed decimal (signed 277 * two’s complement) calibration 278 * data, internal module 279 * temperature. Bit 7 of byte 86 is 280 * MSB, bit 0 of byte 87 is LSB. 281 * T(Offset) should be set to zero 282 * for “internally calibrated” 283 * devices. */ 284 SFF_8472_V_SLOPE = 88, /* V (Slope) Fixed decimal 285 * (unsigned) calibration data, 286 * internal module supply 287 * voltage. Bit 7 of byte 88 is 288 * MSB, bit 0 of byte 89 is 289 * LSB. V(Slope) should be set to 1 290 * for “internally calibrated” 291 * devices. */ 292 SFF_8472_V_OFFSET = 90, /* V (Offset) Fixed decimal (signed 293 * two’s complement) calibration 294 * data, internal module supply 295 * voltage. Bit 7 of byte 90 is 296 * MSB. Bit 0 of byte 91 is 297 * LSB. V(Offset) should be set to 298 * zero for “internally calibrated” 299 * devices. */ 300 SFF_8472_CHECKSUM = 95, /* Checksum Byte 95 contains the 301 * low order 8 bits of the sum of 302 * bytes 0 – 94. */ 303 /* Internal measurements. */ 304 305 SFF_8472_TEMP = 96, /* Internally measured module temperature. */ 306 SFF_8472_VCC = 98, /* Internally measured supply 307 * voltage in transceiver. 308 */ 309 SFF_8472_TX_BIAS = 100, /* Internally measured TX Bias Current. */ 310 SFF_8472_TX_POWER = 102, /* Measured TX output power. */ 311 SFF_8472_RX_POWER = 104, /* Measured RX input power. */ 312 313 SFF_8472_STATUS = 110 /* See below */ 314 }; 315 /* Status Bits Described */ 316 317 /* 318 * TX Disable State Digital state of the TX Disable Input Pin. Updated 319 * within 100ms of change on pin. 320 */ 321 #define SFF_8472_STATUS_TX_DISABLE (1 << 7) 322 323 /* 324 * Select Read/write bit that allows software disable of 325 * laser. Writing ‘1’ disables laser. See Table 3.11 for 326 * enable/disable timing requirements. This bit is “OR”d with the hard 327 * TX_DISABLE pin value. Note, per SFP MSA TX_DISABLE pin is default 328 * enabled unless pulled low by hardware. If Soft TX Disable is not 329 * implemented, the transceiver ignores the value of this bit. Default 330 * power up value is zero/low. 331 */ 332 #define SFF_8472_STATUS_SOFT_TX_DISABLE (1 << 6) 333 334 /* 335 * RS(1) State Digital state of SFP input pin AS(1) per SFF-8079 or 336 * RS(1) per SFF-8431. Updated within 100ms of change on pin. See A2h 337 * Byte 118, Bit 3 for Soft RS(1) Select control information. 338 */ 339 #define SFF_8472_RS_STATE (1 << 5) 340 341 /* 342 * Rate_Select State [aka. “RS(0)”] Digital state of the SFP 343 * Rate_Select Input Pin. Updated within 100ms of change on pin. Note: 344 * This pin is also known as AS(0) in SFF-8079 and RS(0) in SFF-8431. 345 */ 346 #define SFF_8472_STATUS_SELECT_STATE (1 << 4) 347 348 /* 349 * Read/write bit that allows software rate select control. Writing 350 * ‘1’ selects full bandwidth operation. This bit is “OR’d with the 351 * hard Rate_Select, AS(0) or RS(0) pin value. See Table 3.11 for 352 * timing requirements. Default at power up is logic zero/low. If Soft 353 * Rate Select is not implemented, the transceiver ignores the value 354 * of this bit. Note: Specific transceiver behaviors of this bit are 355 * identified in Table 3.6a and referenced documents. See Table 3.18a, 356 * byte 118, bit 3 for Soft RS(1) Select. 357 */ 358 #define SFF_8472_STATUS_SOFT_RATE_SELECT (1 << 3) 359 360 /* 361 * TX Fault State Digital state of the TX Fault Output Pin. Updated 362 * within 100ms of change on pin. 363 */ 364 #define SFF_8472_STATUS_TX_FAULT_STATE (1 << 2) 365 366 /* 367 * Digital state of the RX_LOS Output Pin. Updated within 100ms of 368 * change on pin. 369 */ 370 #define SFF_8472_STATUS_RX_LOS (1 << 1) 371 372 /* 373 * Indicates transceiver has achieved power up and data is ready. Bit 374 * remains high until data is ready to be read at which time the 375 * device sets the bit low. 376 */ 377 #define SFF_8472_STATUS_DATA_READY (1 << 0) 378 379 /* 380 * Table 3.2 Identifier values. 381 * Identifier constants has taken from SFF-8024 rev 4.6 table 4.1 382 * (as referenced by table 3.2 footer) 383 * */ 384 enum { 385 SFF_8024_ID_UNKNOWN = 0x0, /* Unknown or unspecified */ 386 SFF_8024_ID_GBIC = 0x1, /* GBIC */ 387 SFF_8024_ID_SFF = 0x2, /* Module soldered to motherboard (ex: SFF)*/ 388 SFF_8024_ID_SFP = 0x3, /* SFP or SFP “Plus” */ 389 SFF_8024_ID_XBI = 0x4, /* 300 pin XBI */ 390 SFF_8024_ID_XENPAK = 0x5, /* Xenpak */ 391 SFF_8024_ID_XFP = 0x6, /* XFP */ 392 SFF_8024_ID_XFF = 0x7, /* XFF */ 393 SFF_8024_ID_XFPE = 0x8, /* XFP-E */ 394 SFF_8024_ID_XPAK = 0x9, /* XPAk */ 395 SFF_8024_ID_X2 = 0xA, /* X2 */ 396 SFF_8024_ID_DWDM_SFP = 0xB, /* DWDM-SFP */ 397 SFF_8024_ID_QSFP = 0xC, /* QSFP */ 398 SFF_8024_ID_QSFPPLUS = 0xD, /* QSFP+ or later */ 399 SFF_8024_ID_CXP = 0xE, /* CXP */ 400 SFF_8024_ID_HD4X = 0xF, /* Shielded Mini Multilane HD 4X */ 401 SFF_8024_ID_HD8X = 0x10, /* Shielded Mini Multilane HD 8X */ 402 SFF_8024_ID_QSFP28 = 0x11, /* QSFP28 or later */ 403 SFF_8024_ID_CXP2 = 0x12, /* CXP2 (aka CXP28) */ 404 SFF_8024_ID_CDFP = 0x13, /* CDFP (Style 1/Style 2) */ 405 SFF_8024_ID_SMM4 = 0x14, /* Shielded Mini Multilate HD 4X Fanout */ 406 SFF_8024_ID_SMM8 = 0x15, /* Shielded Mini Multilate HD 8X Fanout */ 407 SFF_8024_ID_CDFP3 = 0x16, /* CDFP (Style3) */ 408 SFF_8024_ID_MICROQSFP = 0x17, /* microQSFP */ 409 SFF_8024_ID_QSFP_DD = 0x18, /* QSFP-DD 8X Pluggable Transceiver */ 410 SFF_8024_ID_OSFP8X = 0x19, /* OSFP 8X Pluggable Transceiver */ 411 SFF_8024_ID_SFP_DD = 0x1A, /* SFP-DD 2X Pluggable Transceiver */ 412 SFF_8024_ID_DSFP = 0x1B, /* DSFP Dual SFF Pluggable Transceiver */ 413 SFF_8024_ID_X4ML = 0x1C, /* x4 MiniLink/OcuLink */ 414 SFF_8024_ID_X8ML = 0x1D, /* x8 MiniLink */ 415 SFF_8024_ID_QSFP_CMIS = 0x1E, /* QSFP+ or later w/ Common Management 416 Interface Specification */ 417 SFF_8024_ID_LAST = SFF_8024_ID_QSFP_CMIS 418 }; 419 420 static const char *sff_8024_id[SFF_8024_ID_LAST + 1] = { 421 "Unknown", 422 "GBIC", 423 "SFF", 424 "SFP/SFP+/SFP28", 425 "XBI", 426 "Xenpak", 427 "XFP", 428 "XFF", 429 "XFP-E", 430 "XPAK", 431 "X2", 432 "DWDM-SFP/SFP+", 433 "QSFP", 434 "QSFP+", 435 "CXP", 436 "HD4X", 437 "HD8X", 438 "QSFP28", 439 "CXP2", 440 "CDFP", 441 "SMM4", 442 "SMM8", 443 "CDFP3", 444 "microQSFP", 445 "QSFP-DD", 446 "QSFP8X", 447 "SFP-DD", 448 "DSFP", 449 "x4MiniLink/OcuLink", 450 "x8MiniLink", 451 "QSFP+(CIMS)" 452 }; 453 454 /* Keep compatibility with old definitions */ 455 #define SFF_8472_ID_UNKNOWN SFF_8024_ID_UNKNOWN 456 #define SFF_8472_ID_GBIC SFF_8024_ID_GBIC 457 #define SFF_8472_ID_SFF SFF_8024_ID_SFF 458 #define SFF_8472_ID_SFP SFF_8024_ID_SFP 459 #define SFF_8472_ID_XBI SFF_8024_ID_XBI 460 #define SFF_8472_ID_XENPAK SFF_8024_ID_XENPAK 461 #define SFF_8472_ID_XFP SFF_8024_ID_XFP 462 #define SFF_8472_ID_XFF SFF_8024_ID_XFF 463 #define SFF_8472_ID_XFPE SFF_8024_ID_XFPE 464 #define SFF_8472_ID_XPAK SFF_8024_ID_XPAK 465 #define SFF_8472_ID_X2 SFF_8024_ID_X2 466 #define SFF_8472_ID_DWDM_SFP SFF_8024_ID_DWDM_SFP 467 #define SFF_8472_ID_QSFP SFF_8024_ID_QSFP 468 #define SFF_8472_ID_LAST SFF_8024_ID_LAST 469 470 #define sff_8472_id sff_8024_id 471 472 /* 473 * Table 3.9 Diagnostic Monitoring Type (byte 92) 474 * bits described. 475 */ 476 477 /* 478 * Digital diagnostic monitoring implemented. 479 * Set to 1 for transceivers implementing DDM. 480 */ 481 #define SFF_8472_DDM_DONE (1 << 6) 482 483 /* 484 * Measurements are internally calibrated. 485 */ 486 #define SFF_8472_DDM_INTERNAL (1 << 5) 487 488 /* 489 * Measurements are externally calibrated. 490 */ 491 #define SFF_8472_DDM_EXTERNAL (1 << 4) 492 493 /* 494 * Received power measurement type 495 * 0 = OMA, 1 = average power 496 */ 497 #define SFF_8472_DDM_PMTYPE (1 << 3) 498 499 /* Table 3.13 and 3.14 Temperature Conversion Values */ 500 #define SFF_8472_TEMP_SIGN (1 << 15) 501 #define SFF_8472_TEMP_SHIFT 8 502 #define SFF_8472_TEMP_MSK 0xEF00 503 #define SFF_8472_TEMP_FRAC 0x00FF 504 505 /* Internal Callibration Conversion factors */ 506 507 /* 508 * Represented as a 16 bit unsigned integer with the voltage defined 509 * as the full 16 bit value (0 – 65535) with LSB equal to 100 uVolt, 510 * yielding a total range of 0 to +6.55 Volts. 511 */ 512 #define SFF_8472_VCC_FACTOR 10000.0 513 514 /* 515 * Represented as a 16 bit unsigned integer with the current defined 516 * as the full 16 bit value (0 – 65535) with LSB equal to 2 uA, 517 * yielding a total range of 0 to 131 mA. 518 */ 519 520 #define SFF_8472_BIAS_FACTOR 2000.0 521 522 /* 523 * Represented as a 16 bit unsigned integer with the power defined as 524 * the full 16 bit value (0 – 65535) with LSB equal to 0.1 uW, 525 * yielding a total range of 0 to 6.5535 mW (~ -40 to +8.2 dBm). 526 */ 527 528 #define SFF_8472_POWER_FACTOR 10000.0
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