Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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sys/osfmk/ppc/Firmware.s
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1 /* 2 * Copyright (c) 2000-2005 Apple Computer, Inc. All rights reserved. 3 * 4 * @APPLE_LICENSE_HEADER_START@ 5 * 6 * The contents of this file constitute Original Code as defined in and 7 * are subject to the Apple Public Source License Version 1.1 (the 8 * "License"). You may not use this file except in compliance with the 9 * License. Please obtain a copy of the License at 10 * http://www.apple.com/publicsource and read it before using this file. 11 * 12 * This Original Code and all software distributed under the License are 13 * distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, EITHER 14 * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES, 15 * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT. Please see the 17 * License for the specific language governing rights and limitations 18 * under the License. 19 * 20 * @APPLE_LICENSE_HEADER_END@ 21 */ 22 /* 23 * @OSF_FREE_COPYRIGHT@ 24 */ 25 /* 26 * @APPLE_FREE_COPYRIGHT@ 27 */ 28 29 /* 30 Firmware.s 31 32 Handle things that should be treated as an extension of the hardware 33 34 Lovingly crafted by Bill Angell using traditional methods and only natural or recycled materials. 35 No animal products are used other than rendered otter bile and deep fried pork lard. 36 37 */ 38 39 #include <ppc/asm.h> 40 #include <ppc/proc_reg.h> 41 #include <ppc/spec_reg.h> 42 #include <ppc/exception.h> 43 #include <mach/machine/vm_param.h> 44 #include <assym.s> 45 46 47 /* 48 * Here we generate the table of supported firmware calls 49 */ 50 51 52 53 .data 54 .align 5 /* Line up on cache line */ 55 56 .globl EXT(FWtable) 57 58 EXT(FWtable): 59 60 .globl CutTrace /* Let everyone know 'bout it */ 61 .set CutTrace,(.-EXT(FWtable))/4|0x80000000 /* Call number for CutTrace */ 62 .long callUnimp /* This was already handled in lowmem_vectors */ 63 64 #include <ppc/FirmwareCalls.h> 65 66 .set EXT(FirmwareCnt), (.-EXT(FWtable))/4 /* Get the top number */ 67 68 .text 69 70 #define SIMPLESCC 1 71 #define NOTQUITEASSIMPLE 1 72 /* 73 * This routine handles the firmware call routine. It must be entered with IR and DR off, 74 * interruptions disabled, and in supervisor state. 75 * 76 * When we enter, we expect R0 to have call number, and LR 77 * to point to the return. Also, all registers saved in savearea in R13. 78 * R3 is as passed in by the user. All others must be gotten from the save area 79 */ 80 81 82 .align 5 83 .globl EXT(FirmwareCall) 84 85 LEXT(FirmwareCall) 86 87 rlwinm r1,r0,2,1,29 /* Clear out bit 0 and multiply by 4 */ 88 lis r12,HIGH_ADDR(EXT(FWtable)) /* Get the high part of the firmware call table */ 89 cmplwi r1,EXT(FirmwareCnt)*4 /* Is it a valid firmware call number */ 90 ori r12,r12,LOW_ADDR(EXT(FWtable)) /* Now the low part */ 91 ble+ goodCall /* Yeah, it is... */ 92 93 li r3,T_SYSTEM_CALL /* Tell the vector handler that we know nothing */ 94 b EXT(FCReturn) ; Bye dudes... 95 96 goodCall: mfsprg r10,0 /* Make sure about the per_proc block */ 97 lwzx r1,r1,r12 /* Pick up the address of the routine */ 98 lwz r4,saver4+4(r13) /* Pass in caller's R4 */ 99 lwz r5,saver5+4(r13) /* Pass in caller's R5 */ 100 rlwinm. r1,r1,0,0,29 /* Make sure the flag bits are clear */ 101 102 mtlr r1 /* Put it in the LR */ 103 beq- callUnimp /* This one was unimplimented... */ 104 105 blrl /* Call the routine... */ 106 107 stw r3,saver3+4(r13) /* Pass back the return code to caller */ 108 li r3,T_IN_VAIN /* Tell the vector handler that we took care of it */ 109 b EXT(FCReturn) ; Bye dudes... 110 111 callUnimp: li r3,T_SYSTEM_CALL /* Tell the vector handler that we know nothing */ 112 b EXT(FCReturn) ; Bye dudes... 113 114 /* 115 * This routine is used to store using a real address. It stores parmeter1 at parameter2. 116 */ 117 118 .align 5 119 .globl EXT(StoreReal) 120 121 LEXT(StoreReal) 122 123 lis r0,HIGH_ADDR(StoreRealCall) /* Get the top part of the SC number */ 124 ori r0,r0,LOW_ADDR(StoreRealCall) /* and the bottom part */ 125 sc /* Do it to it */ 126 blr /* Bye bye, Birdie... */ 127 128 .align 5 129 .globl EXT(StoreRealLL) 130 131 LEXT(StoreRealLL) 132 133 stw r3,0(r4) /* Store the word */ 134 blr /* Leave... */ 135 136 /* 137 * This routine is used to clear a range of physical pages. 138 */ 139 140 .align 5 141 .globl EXT(ClearReal) 142 143 LEXT(ClearReal) 144 145 lis r0,HIGH_ADDR(ClearRealCall) /* Get the top part of the SC number */ 146 ori r0,r0,LOW_ADDR(ClearRealCall) /* and the bottom part */ 147 sc /* Do it to it */ 148 blr /* Bye bye, Birdie... */ 149 150 151 .align 5 152 .globl EXT(ClearRealLL) 153 154 LEXT(ClearRealLL) 155 156 /* 157 * We take the first parameter as a physical address. The second is the length in bytes. 158 * Being crazy, I'll round the address down, and the length up. We could end up clearing 159 * an extra page at the start and one at the end, but we don't really care. If someone 160 * is stupid enough to give me unaligned addresses and lengths, I am just arrogant enough 161 * to take them at their word and to hell with them. 162 */ 163 164 neg r5,r3 /* Negate the address */ 165 addi r4,r4,4095 /* Round length up */ 166 rlwinm r5,r5,0,20,31 /* Save extra length */ 167 rlwinm r3,r3,0,0,19 /* Round the page on down */ 168 add r4,r4,r5 /* Add up all extra lengths */ 169 li r6,32 /* Get a displacement */ 170 rlwinm r4,r4,0,0,19 /* Round the length back down */ 171 172 clrloop: subi r4,r4,32 /* Back off a cache line */ 173 dcbz 0,r3 /* Do the even line */ 174 sub. r4,r4,r6 /* Back off a second time (we only do this to generate a CR */ 175 dcbz r6,r3 /* Clear the even line */ 176 addi r3,r3,64 /* Move up to every other line */ 177 bgt+ clrloop /* Go until we've done it all... */ 178 179 blr /* Leave... */ 180 /* 181 * This routine will read in 32 byte of real storage. 182 */ 183 184 .align 5 185 .globl EXT(ReadReal) 186 187 LEXT(ReadReal) 188 189 mfsprg r9,2 ; Get the features 190 mfmsr r0 ; Get the MSR 191 li r8,lo16(MASK(MSR_DR)) ; Get the DR bit 192 rlwinm. r9,r9,0,pf64Bitb,pf64Bitb ; Are we 64-bit? 193 ori r8,r8,lo16(MASK(MSR_EE)) ; Add in the EE bit 194 li r7,1 ; Get set for it 195 andc r8,r0,r8 ; Turn off EE and DR 196 bt-- cr0_eq,rr32a ; Yes, we are... 197 198 rldimi r8,r7,63,MSR_SF_BIT ; Set SF bit (bit 0) 199 sldi r3,r3,32 ; Slide on over for true 64-bit address 200 mtmsrd r8 201 isync 202 or r3,r3,r4 ; Join top and bottom of address 203 mr r4,r5 ; Set destination address 204 b rrJoina ; Join on up... 205 206 rr32a: mr r3,r4 ; Position bottom of long long 207 mr r4,r5 ; Set destination address 208 mtmsr r8 /* Disable EE and DR */ 209 isync /* Just make sure about it */ 210 211 rrJoina: lwz r5,0(r3) /* Get word 0 */ 212 lwz r6,4(r3) /* Get word 1 */ 213 lwz r7,8(r3) /* Get word 2 */ 214 lwz r8,12(r3) /* Get word 3 */ 215 lis r2,hi16(MASK(MSR_VEC)) ; Get the vector enable 216 lwz r9,16(r3) /* Get word 4 */ 217 ori r2,r2,lo16(MASK(MSR_FP)) ; Get the FP enable 218 lwz r10,20(r3) /* Get word 5 */ 219 andc r0,r0,r2 ; Clear VEC and FP enables 220 lwz r11,24(r3) /* Get word 6 */ 221 lwz r12,28(r3) /* Get word 7 */ 222 223 bt-- cr0_eq,rr32b ; We are not 64-bit... 224 225 mtmsrd r0 226 isync 227 b rrJoinb ; Join on up... 228 229 rr32b: mtmsr r0 /* Restore original machine state */ 230 isync /* Insure goodness */ 231 232 rrJoinb: stw r5,0(r4) /* Set word 0 */ 233 stw r6,4(r4) /* Set word 1 */ 234 stw r7,8(r4) /* Set word 2 */ 235 stw r8,12(r4) /* Set word 3 */ 236 stw r9,16(r4) /* Set word 4 */ 237 stw r10,20(r4) /* Set word 5 */ 238 stw r11,24(r4) /* Set word 6 */ 239 stw r12,28(r4) /* Set word 7 */ 240 241 blr 242 243 244 /* 245 * This routine is used to load all 4 DBATs. 246 */ 247 248 .align 5 249 .globl EXT(LoadDBATs) 250 251 LEXT(LoadDBATs) 252 253 254 lis r0,HIGH_ADDR(LoadDBATsCall) /* Top half of LoadDBATsCall firmware call number */ 255 ori r0,r0,LOW_ADDR(LoadDBATsCall) /* Bottom half */ 256 sc /* Do it to it */ 257 258 blr /* Bye bye, Birdie... */ 259 260 261 .align 5 262 .globl EXT(xLoadDBATsLL) 263 264 LEXT(xLoadDBATsLL) 265 266 lwz r4,0(r3) /* Get DBAT 0 high */ 267 lwz r5,4(r3) /* Get DBAT 0 low */ 268 lwz r6,8(r3) /* Get DBAT 1 high */ 269 lwz r7,12(r3) /* Get DBAT 1 low */ 270 lwz r8,16(r3) /* Get DBAT 2 high */ 271 lwz r9,20(r3) /* Get DBAT 2 low */ 272 lwz r10,24(r3) /* Get DBAT 3 high */ 273 lwz r11,28(r3) /* Get DBAT 3 low */ 274 275 sync /* Common decency and the state law require that you wash your hands */ 276 mtdbatu 0,r4 /* Load DBAT 0 high */ 277 mtdbatl 0,r5 /* Load DBAT 0 low */ 278 mtdbatu 1,r6 /* Load DBAT 1 high */ 279 mtdbatl 1,r7 /* Load DBAT 1 low */ 280 mtdbatu 2,r8 /* Load DBAT 2 high */ 281 mtdbatl 2,r9 /* Load DBAT 2 low */ 282 mtdbatu 3,r10 /* Load DBAT 3 high */ 283 mtdbatl 3,r11 /* Load DBAT 3 low */ 284 sync /* Make sure it's done */ 285 isync /* Toss out anything new */ 286 287 blr /* Leave... */ 288 289 /* 290 * This routine is used to load all 4 IBATs. 291 */ 292 293 .align 5 294 .globl EXT(LoadIBATs) 295 296 LEXT(LoadIBATs) 297 298 299 lis r0,HIGH_ADDR(LoadIBATsCall) /* Top half of LoadIBATsCall firmware call number */ 300 ori r0,r0,LOW_ADDR(LoadIBATsCall) /* Bottom half */ 301 sc /* Do it to it */ 302 blr /* Bye bye, Birdie... */ 303 304 .align 5 305 .globl EXT(xLoadIBATsLL) 306 307 LEXT(xLoadIBATsLL) 308 309 lwz r4,0(r3) /* Get IBAT 0 high */ 310 lwz r5,4(r3) /* Get IBAT 0 low */ 311 lwz r6,8(r3) /* Get IBAT 1 high */ 312 lwz r7,12(r3) /* Get IBAT 1 low */ 313 lwz r8,16(r3) /* Get IBAT 2 high */ 314 lwz r9,20(r3) /* Get IBAT 2 low */ 315 lwz r10,24(r3) /* Get IBAT 3 high */ 316 lwz r11,28(r3) /* Get IBAT 3 low */ 317 318 sync /* Common decency and the state law require that you wash your hands */ 319 mtibatu 0,r4 /* Load IBAT 0 high */ 320 mtibatl 0,r5 /* Load IBAT 0 low */ 321 mtibatu 1,r6 /* Load IBAT 1 high */ 322 mtibatl 1,r7 /* Load IBAT 1 low */ 323 mtibatu 2,r8 /* Load IBAT 2 high */ 324 mtibatl 2,r9 /* Load IBAT 2 low */ 325 mtibatu 3,r10 /* Load IBAT 3 high */ 326 mtibatl 3,r11 /* Load IBAT 3 low */ 327 sync /* Make sure it's done */ 328 isync /* Toss out anything new */ 329 330 blr /* Leave... */ 331 332 333 /* 334 * This is the glue to call the CutTrace firmware call 335 * dbgTrace(id, p1, p2, p3, p4) 336 */ 337 338 .align 5 339 .globl EXT(dbgTrace) 340 341 LEXT(dbgTrace) 342 343 mr r2,r3 344 mr r3,r4 345 lis r0,HIGH_ADDR(CutTrace) /* Top half of CreateFakeIO firmware call number */ 346 mr r4,r5 347 mr r5,r6 348 ori r0,r0,LOW_ADDR(CutTrace) /* Bottom half */ 349 mr r6,r7 350 sc /* Do it to it */ 351 blr /* Bye bye, Birdie... */ 352 353 /* 354 * This is the glue to create a fake I/O interruption 355 */ 356 357 .align 5 358 .globl EXT(CreateFakeIO) 359 360 LEXT(CreateFakeIO) 361 362 lis r0,HIGH_ADDR(CreateFakeIOCall) /* Top half of CreateFakeIO firmware call number */ 363 ori r0,r0,LOW_ADDR(CreateFakeIOCall) /* Bottom half */ 364 sc /* Do it to it */ 365 blr /* Bye bye, Birdie... */ 366 367 /* 368 * This is the glue to create a fake Dec interruption 369 */ 370 371 .align 5 372 .globl EXT(CreateFakeDEC) 373 374 LEXT(CreateFakeDEC) 375 376 #if 0 377 mflr r4 ; (TEST/DEBUG) 378 bl EXT(ml_sense_nmi) ; (TEST/DEBUG) 379 mtlr r4 ; (TEST/DEBUG) 380 #endif 381 382 lis r0,HIGH_ADDR(CreateFakeDECCall) /* Top half of CreateFakeDEC firmware call number */ 383 ori r0,r0,LOW_ADDR(CreateFakeDECCall) /* Bottom half */ 384 sc /* Do it to it */ 385 blr /* Bye bye, Birdie... */ 386 387 388 /* 389 * This is the glue to create a shutdown context 390 */ 391 392 .align 5 393 .globl EXT(CreateShutdownCTX) 394 395 LEXT(CreateShutdownCTX) 396 397 lis r0,HIGH_ADDR(CreateShutdownCTXCall) /* Top half of CreateFakeIO firmware call number */ 398 ori r0,r0,LOW_ADDR(CreateShutdownCTXCall) /* Bottom half */ 399 sc /* Do it to it */ 400 blr /* Bye bye, Birdie... */ 401 402 /* 403 * This is the glue to choke system 404 */ 405 406 .align 5 407 .globl EXT(ChokeSys) 408 409 LEXT(ChokeSys) 410 411 lis r0,HIGH_ADDR(Choke) /* Top half of Choke firmware call number */ 412 ori r0,r0,LOW_ADDR(Choke) /* Bottom half */ 413 sc /* Do it to it */ 414 blr /* Bye bye, Birdie... */ 415 416 /* 417 * Used to initialize the SCC for debugging output 418 */ 419 420 421 .align 5 422 .globl EXT(fwSCCinit) 423 424 LEXT(fwSCCinit) 425 426 mfmsr r8 /* Save the MSR */ 427 mr. r3,r3 /* See if printer or modem */ 428 rlwinm r12,r8,0,28,25 /* Turn off translation */ 429 lis r10,0xF301 /* Set the top part */ 430 rlwinm r12,r12,0,17,15 /* Turn off interruptions */ 431 #if 0 432 mtmsr r12 /* Smash the MSR */ 433 isync /* Make it clean */ 434 #endif 435 436 ori r10,r10,0x2000 /* Assume the printer (this is the normal one) */ 437 beq+ fwSCCprnt /* It sure are... */ 438 ori r10,r10,0x0002 /* Move it over to the modem port */ 439 440 fwSCCprnt: dcbf 0,r10 /* Insure it is out */ 441 sync 442 eieio 443 dcbi 0,r10 /* Toss it */ 444 sync 445 446 447 li r7,0x09 /* Set the register */ 448 stb r7,0(r10) /* Set the register */ 449 dcbf 0,r10 /* Force it out */ 450 sync /* Make sure it's out there */ 451 dcbi 0,r10 452 eieio 453 454 li r7,0x80 /* Reset channel A */ 455 stb r7,0(r10) /* Set the register */ 456 dcbf 0,r10 /* Force it out */ 457 sync /* Make sure it's out there */ 458 dcbi 0,r10 459 eieio 460 461 li r7,0x04 /* Set the register */ 462 stb r7,0(r10) /* Set the register */ 463 dcbf 0,r10 /* Force it out */ 464 sync /* Make sure it's out there */ 465 dcbi 0,r10 466 eieio 467 468 li r7,0x44 /* x16 clock, 1 stop bit */ 469 stb r7,0(r10) /* Set the register */ 470 dcbf 0,r10 /* Force it out */ 471 sync /* Make sure it's out there */ 472 dcbi 0,r10 473 eieio 474 475 li r7,0x03 /* Set the register */ 476 stb r7,0(r10) /* Set the register */ 477 dcbf 0,r10 /* Force it out */ 478 sync /* Make sure it's out there */ 479 dcbi 0,r10 480 eieio 481 482 li r7,0xC0 /* 8 bits per char */ 483 stb r7,0(r10) /* Set the register */ 484 dcbf 0,r10 /* Force it out */ 485 sync /* Make sure it's out there */ 486 dcbi 0,r10 487 eieio 488 489 li r7,0x05 /* Set the register */ 490 stb r7,0(r10) /* Set the register */ 491 dcbf 0,r10 /* Force it out */ 492 sync /* Make sure it's out there */ 493 dcbi 0,r10 494 eieio 495 496 li r7,0xE2 /* DTR mode, 8bit/char */ 497 stb r7,0(r10) /* Set the register */ 498 dcbf 0,r10 /* Force it out */ 499 sync /* Make sure it's out there */ 500 dcbi 0,r10 501 eieio 502 503 li r7,0x02 /* Set the register */ 504 stb r7,0(r10) /* Set the register */ 505 dcbf 0,r10 /* Force it out */ 506 sync /* Make sure it's out there */ 507 dcbi 0,r10 508 eieio 509 510 li r7,0x00 /* Vector 0 */ 511 stb r7,0(r10) /* Set the register */ 512 dcbf 0,r10 /* Force it out */ 513 sync /* Make sure it's out there */ 514 dcbi 0,r10 515 eieio 516 517 li r7,0x0A /* Set the register */ 518 stb r7,0(r10) /* Set the register */ 519 dcbf 0,r10 /* Force it out */ 520 sync /* Make sure it's out there */ 521 dcbi 0,r10 522 eieio 523 524 li r7,0x00 /* Clear misc controls */ 525 stb r7,0(r10) /* Set the register */ 526 dcbf 0,r10 /* Force it out */ 527 sync /* Make sure it's out there */ 528 dcbi 0,r10 529 eieio 530 531 li r7,0x0B /* Set the register */ 532 stb r7,0(r10) /* Set the register */ 533 dcbf 0,r10 /* Force it out */ 534 sync /* Make sure it's out there */ 535 dcbi 0,r10 536 eieio 537 538 li r7,0x50 /* B/R gen T/R */ 539 stb r7,0(r10) /* Set the register */ 540 dcbf 0,r10 /* Force it out */ 541 sync /* Make sure it's out there */ 542 dcbi 0,r10 543 eieio 544 545 li r7,0x0C /* Set the register */ 546 stb r7,0(r10) /* Set the register */ 547 dcbf 0,r10 /* Force it out */ 548 sync /* Make sure it's out there */ 549 dcbi 0,r10 550 eieio 551 552 li r7,0x0A /* 9600 baud low */ 553 stb r7,0(r10) /* Set the register */ 554 dcbf 0,r10 /* Force it out */ 555 sync /* Make sure it's out there */ 556 dcbi 0,r10 557 eieio 558 559 li r7,0x0D /* Set the register */ 560 stb r7,0(r10) /* Set the register */ 561 dcbf 0,r10 /* Force it out */ 562 sync /* Make sure it's out there */ 563 dcbi 0,r10 564 eieio 565 566 li r7,0x00 /* 9600 baud high */ 567 stb r7,0(r10) /* Set the register */ 568 dcbf 0,r10 /* Force it out */ 569 sync /* Make sure it's out there */ 570 dcbi 0,r10 571 eieio 572 573 li r7,0x03 /* Set the register */ 574 stb r7,0(r10) /* Set the register */ 575 dcbf 0,r10 /* Force it out */ 576 sync /* Make sure it's out there */ 577 dcbi 0,r10 578 eieio 579 580 li r7,0xC1 /* 8 bits/char, Rx enable */ 581 stb r7,0(r10) /* Set the register */ 582 dcbf 0,r10 /* Force it out */ 583 sync /* Make sure it's out there */ 584 dcbi 0,r10 585 eieio 586 587 li r7,0x05 /* Set the register */ 588 stb r7,0(r10) /* Set the register */ 589 dcbf 0,r10 /* Force it out */ 590 sync /* Make sure it's out there */ 591 dcbi 0,r10 592 eieio 593 594 li r7,0xEA /* 8 bits/char, Tx enable */ 595 stb r7,0(r10) /* Set the register */ 596 dcbf 0,r10 /* Force it out */ 597 sync /* Make sure it's out there */ 598 dcbi 0,r10 599 eieio 600 601 li r7,0x0E /* Set the register */ 602 stb r7,0(r10) /* Set the register */ 603 dcbf 0,r10 /* Force it out */ 604 sync /* Make sure it's out there */ 605 dcbi 0,r10 606 eieio 607 608 li r7,0x01 /* BR rate gen enable */ 609 stb r7,0(r10) /* Set the register */ 610 dcbf 0,r10 /* Force it out */ 611 sync /* Make sure it's out there */ 612 dcbi 0,r10 613 eieio 614 615 li r7,0x0F /* Set the register */ 616 stb r7,0(r10) /* Set the register */ 617 dcbf 0,r10 /* Force it out */ 618 sync /* Make sure it's out there */ 619 dcbi 0,r10 620 eieio 621 622 li r7,0x00 /* ints off */ 623 stb r7,0(r10) /* Set the register */ 624 dcbf 0,r10 /* Force it out */ 625 sync /* Make sure it's out there */ 626 dcbi 0,r10 627 eieio 628 629 li r7,0x10 /* Reset ext/stat ints */ 630 stb r7,0(r10) /* Set the register */ 631 dcbf 0,r10 /* Force it out */ 632 sync /* Make sure it's out there */ 633 dcbi 0,r10 634 eieio 635 636 li r7,0x10 /* Reset ext/stat ints */ 637 stb r7,0(r10) /* Set the register */ 638 dcbf 0,r10 /* Force it out */ 639 sync /* Make sure it's out there */ 640 dcbi 0,r10 641 eieio 642 643 li r7,0x01 /* Set the register */ 644 stb r7,0(r10) /* Set the register */ 645 dcbf 0,r10 /* Force it out */ 646 sync /* Make sure it's out there */ 647 dcbi 0,r10 648 eieio 649 650 li r7,0x10 /* int on Rx, no Tx int enable */ 651 stb r7,0(r10) /* Set the register */ 652 dcbf 0,r10 /* Force it out */ 653 sync /* Make sure it's out there */ 654 dcbi 0,r10 655 eieio 656 657 li r7,0x09 /* Set the register */ 658 stb r7,0(r10) /* Set the register */ 659 dcbf 0,r10 /* Force it out */ 660 sync /* Make sure it's out there */ 661 dcbi 0,r10 662 eieio 663 664 li r7,0x0A /* int on Rx, Tx int enable */ 665 stb r7,0(r10) /* Set the register */ 666 dcbf 0,r10 /* Force it out */ 667 sync /* Master enable, no vector */ 668 dcbi 0,r10 669 eieio 670 671 li r7,0x09 /* Set the register */ 672 stb r7,0(r10) /* Set the register */ 673 dcbf 0,r10 /* Force it out */ 674 sync /* Make sure it's out there */ 675 dcbi 0,r10 676 eieio 677 678 li r7,0x02 /* No vector */ 679 stb r7,0(r10) /* Set the register */ 680 dcbf 0,r10 /* Force it out */ 681 sync /* Master enable, no vector */ 682 dcbi 0,r10 683 eieio 684 685 lbz r7,0(r10) /* Clear interrupts */ 686 sync /* Master enable, no vector */ 687 dcbi 0,r10 688 eieio 689 690 wSCCrdy: eieio /* Barricade it */ 691 lbz r7,0(r10) /* Get current status */ 692 dcbi 0,r10 693 sync 694 andi. r7,r7,0x04 /* Is transmitter empty? */ 695 beq wSCCrdy /* Nope... */ 696 697 eieio 698 699 #if 0 700 mtmsr r8 /* Restore 'rupts and TR */ 701 isync 702 #endif 703 blr /* Leave... */ 704 705 /* 706 * This routine is used to write debug output to either the modem or printer port. 707 * parm 1 is printer (0) or modem (1); parm 2 is ID (printed directly); parm 3 converted to hex 708 */ 709 710 .align 5 711 .globl EXT(dbgDisp) 712 713 LEXT(dbgDisp) 714 715 mr r12,r0 /* Keep R0 pristene */ 716 lis r0,HIGH_ADDR(dbgDispCall) /* Top half of dbgDispCall firmware call number */ 717 ori r0,r0,LOW_ADDR(dbgDispCall) /* Bottom half */ 718 719 sc /* Go display the stuff */ 720 721 mr r0,r12 /* Restore R0 */ 722 blr /* Return... */ 723 724 /* Here's the low-level part of dbgDisp */ 725 726 .align 5 727 .globl EXT(dbgDispLL) 728 729 LEXT(dbgDispLL) 730 731 dbgDispInt: mfmsr r8 /* Save the MSR */ 732 733 #if 0 734 lis r10,0xF301 /* (TEST/DEBUG) */ 735 ori r10,r10,0x2002 /* (TEST/DEBUG) */ 736 dcbf 0,r10 /* (TEST/DEBUG) */ 737 sync /* (TEST/DEBUG) */ 738 dcbi 0,r10 /* (TEST/DEBUG) */ 739 eieio /* (TEST/DEBUG) */ 740 li r7,0x35 /* (TEST/DEBUG) */ 741 stb r7,4(r10) /* (TEST/DEBUG) */ 742 743 lis r7,10 /* (TEST/DEBUG) */ 744 spw6: addi r7,r7,-1 /* (TEST/DEBUG) */ 745 mr. r7,r7 /* (TEST/DEBUG) */ 746 bne- spw6 /* (TEST/DEBUG) */ 747 dcbf 0,r10 /* (TEST/DEBUG) */ 748 sync /* (TEST/DEBUG) */ 749 dcbi 0,r10 /* (TEST/DEBUG) */ 750 eieio /* (TEST/DEBUG) */ 751 #endif 752 753 rlwinm r12,r8,0,28,25 /* Turn off translation */ 754 rlwinm r12,r12,0,17,15 /* Turn off interruptions */ 755 756 mflr r11 /* Save the link register */ 757 758 #if 0 759 mr r7,r12 /* (TEST/DEBUG) */ 760 bl dumpr7 /* (TEST/DEBUG) */ 761 #endif 762 763 mr. r3,r3 /* See if printer or modem */ 764 lis r10,0xF301 /* Set the top part */ 765 mr r3,r4 /* Copy the ID parameter */ 766 767 #if 0 768 mr r9,r12 /* (TEST/DEBUG) */ 769 770 mtmsr r12 /* (TEST/DEBUG) */ 771 isync /* (TEST/DEBUG) */ 772 773 #if 0 774 mtmsr r8 /* (TEST/DEBUG) */ 775 isync /* (TEST/DEBUG) */ 776 #endif 777 778 lis r12,0xF301 /* (TEST/DEBUG) */ 779 ori r12,r12,0x2002 /* (TEST/DEBUG) */ 780 #if 1 781 dcbf 0,r12 /* (TEST/DEBUG) */ 782 sync /* (TEST/DEBUG) */ 783 dcbi 0,r12 /* (TEST/DEBUG) */ 784 #endif 785 786 xqrw1: eieio /* (TEST/DEBUG) */ 787 lbz r7,0(r12) /* (TEST/DEBUG) */ 788 dcbi 0,r12 /* (TEST/DEBUG) */ 789 sync /* (TEST/DEBUG) */ 790 andi. r7,r7,0x04 /* (TEST/DEBUG) */ 791 beq xqrw1 /* (TEST/DEBUG) */ 792 793 eieio /* (TEST/DEBUG) */ 794 li r7,0x36 /* (TEST/DEBUG) */ 795 stb r7,4(r12) /* (TEST/DEBUG) */ 796 eieio 797 dcbf 0,r12 /* (TEST/DEBUG) */ 798 sync /* (TEST/DEBUG) */ 799 dcbi 0,r12 /* (TEST/DEBUG) */ 800 eieio /* (TEST/DEBUG) */ 801 802 803 lis r7,10 /* (TEST/DEBUG) */ 804 spw7: addi r7,r7,-1 /* (TEST/DEBUG) */ 805 mr. r7,r7 /* (TEST/DEBUG) */ 806 bne- spw7 /* (TEST/DEBUG) */ 807 dcbf 0,r12 /* (TEST/DEBUG) */ 808 sync /* (TEST/DEBUG) */ 809 dcbi 0,r12 /* (TEST/DEBUG) */ 810 eieio /* (TEST/DEBUG) */ 811 mr r12,r9 /* (TEST/DEBUG) */ 812 #endif 813 814 mtmsr r12 /* Smash the MSR */ 815 isync /* Make it clean */ 816 817 818 #if SIMPLESCC && !NOTQUITEASSIMPLE 819 ori r10,r10,0x3010 /* Assume the printer (this is the normal one) */ 820 #else 821 ori r10,r10,0x2000 /* Assume the printer (this is the normal one) */ 822 #endif 823 beq+ dbgDprintr /* It sure are... */ 824 #if SIMPLESCC && !NOTQUITEASSIMPLE 825 ori r10,r10,0x0020 /* Move it over to the modem port */ 826 #else 827 ori r10,r10,0x0002 /* Move it over to the modem port */ 828 829 #if !NOTQUITEASSIMPLE 830 lis r7,0xF300 /* Address of SCC rounded to 128k */ 831 ori r7,r7,0x0032 /* Make it cache inhibited */ 832 mtdbatl 3,r7 /* Load DBAT 3 low */ 833 lis r7,0xF300 /* Address of SCC rounded to 128k */ 834 ori r7,r7,0x0002 /* Make it supervisor only */ 835 mtdbatu 3,r7 /* Load DBAT 3 high */ 836 ori r12,r12,0x0010 /* Turn on DR */ 837 mtmsr r12 /* Smash the MSR */ 838 isync /* Make it clean */ 839 840 #endif 841 #endif 842 843 dbgDprintr: sync 844 #if 0 845 mr r7,r10 /* (TEST/DEBUG) */ 846 bl dumpr7 /* (TEST/DEBUG) */ 847 #endif 848 849 dcbi 0,r10 /* Toss it */ 850 eieio 851 852 #if 0 853 lis r12,0xF301 /* (TEST/DEBUG) */ 854 ori r12,r12,0x2002 /* (TEST/DEBUG) */ 855 dcbf 0,r12 /* (TEST/DEBUG) */ 856 sync /* (TEST/DEBUG) */ 857 dcbi 0,r12 /* (TEST/DEBUG) */ 858 eieio /* (TEST/DEBUG) */ 859 li r7,0x37 /* (TEST/DEBUG) */ 860 stb r7,4(r12) /* (TEST/DEBUG) */ 861 862 lis r7,12 /* (TEST/DEBUG) */ 863 spw8: addi r7,r7,-1 /* (TEST/DEBUG) */ 864 mr. r7,r7 /* (TEST/DEBUG) */ 865 bne- spw8 /* (TEST/DEBUG) */ 866 dcbf 0,r12 /* (TEST/DEBUG) */ 867 sync /* (TEST/DEBUG) */ 868 dcbi 0,r12 /* (TEST/DEBUG) */ 869 eieio /* (TEST/DEBUG) */ 870 #endif 871 872 873 /* Print the ID parameter */ 874 875 lis r12,HIGH_ADDR(fwdisplock) /* Get the display locker outer */ 876 ori r12,r12,LOW_ADDR(fwdisplock) /* Last part */ 877 878 lwarx r7,0,r12 ; ? 879 880 ddwait0: lwarx r7,0,r12 /* Get the lock */ 881 mr. r7,r7 /* Is it locked? */ 882 bne- ddwait0 /* Yup... */ 883 stwcx. r12,0,r12 /* Try to get it */ 884 bne- ddwait0 /* Nope, start all over... */ 885 886 #if 0 887 dcbf 0,r10 /* (TEST/DEBUG) */ 888 sync /* (TEST/DEBUG) */ 889 dcbi 0,r10 /* (TEST/DEBUG) */ 890 eieio /* (TEST/DEBUG) */ 891 li r7,0x38 /* (TEST/DEBUG) */ 892 stb r7,6(r10) /* (TEST/DEBUG) */ 893 894 lis r7,10 /* (TEST/DEBUG) */ 895 spwa: addi r7,r7,-1 /* (TEST/DEBUG) */ 896 mr. r7,r7 /* (TEST/DEBUG) */ 897 bne- spwa /* (TEST/DEBUG) */ 898 dcbf 0,r10 /* (TEST/DEBUG) */ 899 sync /* (TEST/DEBUG) */ 900 dcbi 0,r10 /* (TEST/DEBUG) */ 901 eieio /* (TEST/DEBUG) */ 902 #endif 903 904 rlwinm r3,r3,8,0,31 /* Get the first character */ 905 bl dbgDchar /* Print it */ 906 rlwinm r3,r3,8,0,31 /* Get the second character */ 907 bl dbgDchar /* Print it */ 908 rlwinm r3,r3,8,0,31 /* Get the third character */ 909 bl dbgDchar /* Print it */ 910 rlwinm r3,r3,8,0,31 /* Get the fourth character */ 911 bl dbgDchar /* Print it */ 912 913 li r3,0x20 /* Get a space for a separator */ 914 bl dbgDchar /* Print it */ 915 bl dbg4byte /* Print register 5 in hex */ 916 917 li r3,0x0A /* Linefeed */ 918 bl dbgDchar /* Send it */ 919 li r3,0x0D /* Carriage return */ 920 bl dbgDchar /* Send it */ 921 922 mtlr r11 /* Get back the return */ 923 #if !SIMPLESCC && !NOTQUITEASSIMPLE 924 li r7,0 /* Get a zero */ 925 mtdbatu 3,r7 /* Invalidate DBAT 3 upper */ 926 mtdbatl 3,r7 /* Invalidate DBAT 3 lower */ 927 #endif 928 lis r12,HIGH_ADDR(fwdisplock) /* Get the display locker outer */ 929 li r7,0 /* Get a zero */ 930 ori r12,r12,LOW_ADDR(fwdisplock) /* Last part */ 931 dcbi 0,r10 /* ? */ 932 stw r7,0(r12) /* Release the display lock */ 933 mtmsr r8 /* Restore the MSR */ 934 isync /* Wait for it */ 935 blr /* Leave... */ 936 937 938 dbg4byte: mflr r12 /* Save the return */ 939 940 lis r4,HIGH_ADDR(hexTab) /* Point to the top of table */ 941 li r6,8 /* Set number of hex digits to dump */ 942 ori r4,r4,LOW_ADDR(hexTab) /* Point to the bottom of table */ 943 944 dbgDnext: rlwinm r5,r5,4,0,31 /* Rotate a nybble */ 945 subi r6,r6,1 /* Back down the count */ 946 rlwinm r3,r5,0,28,31 /* Isolate the last nybble */ 947 lbzx r3,r4,r3 /* Convert to ascii */ 948 bl dbgDchar /* Print it */ 949 mr. r6,r6 /* Any more? */ 950 bne+ dbgDnext /* Convert 'em all... */ 951 952 li r3,0x20 /* Space */ 953 bl dbgDchar /* Send it */ 954 mtlr r12 /* Restore LR */ 955 blr /* Return... */ 956 957 /* Write to whichever serial port. Try to leave it clean, but not too hard (this is a hack) */ 958 959 dbgDchar: 960 #if SIMPLESCC && !NOTQUITEASSIMPLE 961 stb r3,0(r10) /* ? */ 962 dcbf 0,r10 /* Force it out */ 963 sync /* Make sure it's out there */ 964 965 lis r7,3 /* Get enough for about 1ms */ 966 967 dbgDchar0: addi r7,r7,-1 /* Count down */ 968 mr. r7,r7 /* Waited long enough? */ 969 bgt+ dbgDchar0 /* Nope... */ 970 #endif 971 #if NOTQUITEASSIMPLE 972 #if 0 973 li r7,0x01 /* ? */ 974 stb r7,0(r10) /* ? */ 975 dcbf 0,r10 /* Force it out */ 976 sync /* Make sure it's out there */ 977 dcbi 0,r10 978 eieio 979 980 lbz r7,0(r10) /* ? */ 981 dcbi 0,r10 /* Force it out */ 982 sync /* kill it off */ 983 eieio 984 985 li r7,0x00 /* ? */ 986 stb r7,0(r10) /* ? */ 987 dcbf 0,r10 /* Force it out */ 988 sync /* Make sure it's out there */ 989 dcbi 0,r10 990 eieio 991 992 lbz r7,0(r10) /* ? */ 993 dcbi 0,r10 /* Force it out */ 994 sync /* kill it off */ 995 eieio 996 #endif 997 998 qrw1: eieio /* Barricade it */ 999 lbz r7,0(r10) /* ? */ 1000 dcbi 0,r10 1001 sync 1002 andi. r7,r7,0x04 /* ? */ 1003 beq qrw1 /* Nope... */ 1004 1005 eieio 1006 1007 stb r3,4(r10) /* ? */ 1008 dcbf 0,r10 /* Force it out */ 1009 sync /* Make sure it's out there */ 1010 dcbi 0,r10 1011 eieio 1012 1013 qrw2: eieio /* Barricade it */ 1014 lbz r7,0(r10) /* ? */ 1015 dcbi 0,r10 1016 sync 1017 andi. r7,r7,0x04 /* ? */ 1018 beq qrw2 /* Nope... */ 1019 1020 #if 0 1021 eieio 1022 li r7,0x10 /* ? */ 1023 stb r7,0(r10) /* ? */ 1024 dcbf 0,r10 /* Force it out */ 1025 sync /* Make sure it's out there */ 1026 dcbi 0,r10 1027 eieio 1028 1029 lbz r7,0(r10) /* ? */ 1030 dcbi 0,r10 /* Force it out */ 1031 sync /* kill it off */ 1032 eieio 1033 #endif 1034 1035 lis r7,0x0080 /* ? */ 1036 lis r9,0xF300 /* ? */ 1037 ori r7,r7,0x010F /* ? */ 1038 stw r7,0x28(r9) /* ? */ 1039 dcbf 0,r10 /* Force it out */ 1040 sync /* Make sure it's out there */ 1041 dcbi 0,r10 1042 eieio 1043 1044 #endif 1045 #if !SIMPLESCC && !NOTQUITEASSIMPLE 1046 rlwinm r9,r10,0,0,29 /* Get channel a */ 1047 eieio /* Barricade it */ 1048 1049 li r7,0x03 /* ? */ 1050 stb r7,0(r9) /* ? */ 1051 eieio /* Barricade it */ 1052 1053 lbz r7,0(r9) /* ? */ 1054 1055 eieio /* Barricade it */ 1056 lbz r7,0(r9) /* ? */ 1057 1058 dchrw1: eieio /* Barricade it */ 1059 lbz r7,0(r10) /* ? */ 1060 andi. r7,r7,0x04 /* ? */ 1061 beq dchrw1 /* Nope... */ 1062 1063 stb r3,4(r10) /* ? */ 1064 sync /* Make sure it's there */ 1065 eieio /* Don't get confused */ 1066 1067 dchrw2: eieio /* Barricade it */ 1068 lbz r7,0(r10) /* ? */ 1069 andi. r7,r7,0x04 /* ? */ 1070 beq dchrw2 /* Nope... */ 1071 1072 eieio /* Avoid confusion */ 1073 lbz r7,0(r10) /* ? */ 1074 andi. r7,r7,0x40 /* ? */ 1075 beq+ nounder /* Nope... */ 1076 1077 eieio /* Avoid confusion */ 1078 li r7,0xC0 /* ? */ 1079 stb r7,0(r10) /* ? */ 1080 1081 nounder: eieio /* Avoid confusion */ 1082 li r7,0x10 /* ? */ 1083 stb r7,0(r10) /* ? */ 1084 1085 eieio /* Avoid confusion */ 1086 li r7,0x38 /* ? */ 1087 stb r7,0(r9) /* ? */ 1088 1089 eieio /* Avoid confusion */ 1090 li r7,0x30 /* ? */ 1091 stb r7,0(r10) /* ? */ 1092 1093 eieio /* Avoid confusion */ 1094 li r7,0x20 /* ? */ 1095 stb r7,0(r10) /* ? */ 1096 eieio /* Avoid confusion */ 1097 sync 1098 1099 #endif 1100 blr /* Return */ 1101 1102 .globl hexTab 1103 1104 hexTab: STRINGD "0123456789ABCDEF" /* Convert hex numbers to printable hex */ 1105 1106 1107 /* 1108 * Dumps all the registers in the savearea in R13 1109 */ 1110 1111 1112 .align 5 1113 .globl EXT(dbgRegsLL) 1114 1115 LEXT(dbgRegsLL) 1116 1117 b EXT(FCReturn) ; Bye dudes... 1118 #if 0 1119 li r3,0 /* ? */ 1120 bl dbgRegsCm /* Join on up... */ 1121 b EXT(FCReturn) ; Bye dudes... 1122 1123 1124 .align 5 1125 .globl EXT(dbgRegs) 1126 1127 LEXT(dbgRegs) 1128 1129 dbgRegsCm: mfmsr r8 /* Save the MSR */ 1130 mr. r3,r3 /* ? */ 1131 rlwinm r12,r8,0,28,25 /* Turn off translation */ 1132 lis r10,0xF301 /* Set the top part */ 1133 rlwinm r12,r12,0,17,15 /* Turn off interruptions */ 1134 mtmsr r12 /* Smash the MSR */ 1135 isync /* Make it clean */ 1136 #if SIMPLESCC && !NOTQUITEASSIMPLE 1137 ori r10,r10,0x3010 /* ? */ 1138 #else 1139 ori r10,r10,0x2000 /* ? */ 1140 #endif 1141 mflr r11 /* Save the link register */ 1142 beq+ dbgDprints /* It sure are... */ 1143 #if SIMPLESCC && !NOTQUITEASSIMPLE 1144 ori r10,r10,0x0020 /* ? */ 1145 #else 1146 ori r10,r10,0x0002 /* ? */ 1147 1148 dcbf 0,r10 /* Insure it is out */ 1149 sync 1150 dcbi 0,r10 /* Toss it */ 1151 #if !NOTQUITEASSIMPLE 1152 lis r7,0xF300 /* ? */ 1153 ori r7,r7,0x0032 /* ? */ 1154 mtdbatl 3,r7 /* ? */ 1155 lis r7,0xF300 /* ? */ 1156 ori r7,r7,0x0002 /* ? */ 1157 mtdbatu 3,r7 /* ? */ 1158 ori r12,r12,0x0010 /* ? */ 1159 mtmsr r12 /* ? */ 1160 isync /* ? */ 1161 #endif 1162 #endif 1163 1164 dbgDprints: 1165 lis r3,HIGH_ADDR(fwdisplock) /* Get the display locker outer */ 1166 ori r3,r3,LOW_ADDR(fwdisplock) /* Last part */ 1167 1168 lwarx r5,0,r3 ; ? 1169 ddwait1: lwarx r5,0,r3 /* Get the lock */ 1170 mr. r5,r5 /* Is it locked? */ 1171 bne- ddwait1 /* Yup... */ 1172 stwcx. r3,0,r3 /* Try to get it */ 1173 bne- ddwait1 /* Nope, start all over... */ 1174 1175 li r3,0x52 /* Print eyecatcher */ 1176 bl dbgDchar /* Send it */ 1177 li r3,0x65 /* Print eyecatcher */ 1178 bl dbgDchar /* Send it */ 1179 li r3,0x67 /* Print eyecatcher */ 1180 bl dbgDchar /* Send it */ 1181 li r3,0x73 /* Print eyecatcher */ 1182 bl dbgDchar /* Send it */ 1183 li r3,0x20 /* Print eyecatcher */ 1184 bl dbgDchar /* Send it */ 1185 1186 lwz r5,saver0(r13) /* Do register */ 1187 bl dbg4byte /* Print */ 1188 lwz r5,saver1(r13) /* Do register */ 1189 bl dbg4byte /* Print */ 1190 lwz r5,saver2(r13) /* Do register */ 1191 bl dbg4byte /* Print */ 1192 lwz r5,saver3(r13) /* Do register */ 1193 bl dbg4byte /* Print */ 1194 li r3,0x0A /* Linefeed */ 1195 bl dbgDchar /* Send it */ 1196 li r3,0x0D /* Carriage return */ 1197 bl dbgDchar /* Send it */ 1198 1199 li r3,0x20 /* Print eyecatcher */ 1200 bl dbgDchar /* Send it */ 1201 li r3,0x20 /* Print eyecatcher */ 1202 bl dbgDchar /* Send it */ 1203 li r3,0x20 /* Print eyecatcher */ 1204 bl dbgDchar /* Send it */ 1205 li r3,0x20 /* Print eyecatcher */ 1206 bl dbgDchar /* Send it */ 1207 li r3,0x20 /* Print eyecatcher */ 1208 bl dbgDchar /* Send it */ 1209 lwz r5,saver4(r13) /* Do register */ 1210 bl dbg4byte /* Print */ 1211 lwz r5,saver5(r13) /* Do register */ 1212 bl dbg4byte /* Print */ 1213 lwz r5,saver6(r13) /* Do register */ 1214 bl dbg4byte /* Print */ 1215 lwz r5,saver7(r13) /* Do register */ 1216 bl dbg4byte /* Print */ 1217 li r3,0x0A /* Linefeed */ 1218 bl dbgDchar /* Send it */ 1219 li r3,0x0D /* Carriage return */ 1220 bl dbgDchar /* Send it */ 1221 1222 li r3,0x20 /* Print eyecatcher */ 1223 bl dbgDchar /* Send it */ 1224 li r3,0x20 /* Print eyecatcher */ 1225 bl dbgDchar /* Send it */ 1226 li r3,0x20 /* Print eyecatcher */ 1227 bl dbgDchar /* Send it */ 1228 li r3,0x20 /* Print eyecatcher */ 1229 bl dbgDchar /* Send it */ 1230 li r3,0x20 /* Print eyecatcher */ 1231 bl dbgDchar /* Send it */ 1232 lwz r5,saver8(r13) /* Do register */ 1233 bl dbg4byte /* Print */ 1234 lwz r5,saver9(r13) /* Do register */ 1235 bl dbg4byte /* Print */ 1236 lwz r5,saver10(r13) /* Do register */ 1237 bl dbg4byte /* Print */ 1238 lwz r5,saver11(r13) /* Do register */ 1239 bl dbg4byte /* Print */ 1240 li r3,0x0A /* Linefeed */ 1241 bl dbgDchar /* Send it */ 1242 li r3,0x0D /* Carriage return */ 1243 bl dbgDchar /* Send it */ 1244 1245 li r3,0x20 /* Print eyecatcher */ 1246 bl dbgDchar /* Send it */ 1247 li r3,0x20 /* Print eyecatcher */ 1248 bl dbgDchar /* Send it */ 1249 li r3,0x20 /* Print eyecatcher */ 1250 bl dbgDchar /* Send it */ 1251 li r3,0x20 /* Print eyecatcher */ 1252 bl dbgDchar /* Send it */ 1253 li r3,0x20 /* Print eyecatcher */ 1254 bl dbgDchar /* Send it */ 1255 lwz r5,saver12(r13) /* Do register */ 1256 bl dbg4byte /* Print */ 1257 lwz r5,saver13(r13) /* Do register */ 1258 bl dbg4byte /* Print */ 1259 lwz r5,saver14(r13) /* Do register */ 1260 bl dbg4byte /* Print */ 1261 lwz r5,saver15(r13) /* Do register */ 1262 bl dbg4byte /* Print */ 1263 li r3,0x0A /* Linefeed */ 1264 bl dbgDchar /* Send it */ 1265 li r3,0x0D /* Carriage return */ 1266 bl dbgDchar /* Send it */ 1267 1268 li r3,0x20 /* Print eyecatcher */ 1269 bl dbgDchar /* Send it */ 1270 li r3,0x20 /* Print eyecatcher */ 1271 bl dbgDchar /* Send it */ 1272 li r3,0x20 /* Print eyecatcher */ 1273 bl dbgDchar /* Send it */ 1274 li r3,0x20 /* Print eyecatcher */ 1275 bl dbgDchar /* Send it */ 1276 li r3,0x20 /* Print eyecatcher */ 1277 bl dbgDchar /* Send it */ 1278 lwz r5,saver16(r13) /* Do register */ 1279 bl dbg4byte /* Print */ 1280 lwz r5,saver17(r13) /* Do register */ 1281 bl dbg4byte /* Print */ 1282 lwz r5,saver18(r13) /* Do register */ 1283 bl dbg4byte /* Print */ 1284 lwz r5,saver19(r13) /* Do register */ 1285 bl dbg4byte /* Print */ 1286 li r3,0x0A /* Linefeed */ 1287 bl dbgDchar /* Send it */ 1288 li r3,0x0D /* Carriage return */ 1289 bl dbgDchar /* Send it */ 1290 1291 li r3,0x20 /* Print eyecatcher */ 1292 bl dbgDchar /* Send it */ 1293 li r3,0x20 /* Print eyecatcher */ 1294 bl dbgDchar /* Send it */ 1295 li r3,0x20 /* Print eyecatcher */ 1296 bl dbgDchar /* Send it */ 1297 li r3,0x20 /* Print eyecatcher */ 1298 bl dbgDchar /* Send it */ 1299 li r3,0x20 /* Print eyecatcher */ 1300 bl dbgDchar /* Send it */ 1301 lwz r5,saver20(r13) /* Do register */ 1302 bl dbg4byte /* Print */ 1303 lwz r5,saver21(r13) /* Do register */ 1304 bl dbg4byte /* Print */ 1305 lwz r5,saver22(r13) /* Do register */ 1306 bl dbg4byte /* Print */ 1307 lwz r5,saver23(r13) /* Do register */ 1308 bl dbg4byte /* Print */ 1309 li r3,0x0A /* Linefeed */ 1310 bl dbgDchar /* Send it */ 1311 li r3,0x0D /* Carriage return */ 1312 bl dbgDchar /* Send it */ 1313 1314 li r3,0x20 /* Print eyecatcher */ 1315 bl dbgDchar /* Send it */ 1316 li r3,0x20 /* Print eyecatcher */ 1317 bl dbgDchar /* Send it */ 1318 li r3,0x20 /* Print eyecatcher */ 1319 bl dbgDchar /* Send it */ 1320 li r3,0x20 /* Print eyecatcher */ 1321 bl dbgDchar /* Send it */ 1322 li r3,0x20 /* Print eyecatcher */ 1323 bl dbgDchar /* Send it */ 1324 lwz r5,saver24(r13) /* Do register */ 1325 bl dbg4byte /* Print */ 1326 lwz r5,saver25(r13) /* Do register */ 1327 bl dbg4byte /* Print */ 1328 lwz r5,saver26(r13) /* Do register */ 1329 bl dbg4byte /* Print */ 1330 lwz r5,saver27(r13) /* Do register */ 1331 bl dbg4byte /* Print */ 1332 li r3,0x0A /* Linefeed */ 1333 bl dbgDchar /* Send it */ 1334 li r3,0x0D /* Carriage return */ 1335 bl dbgDchar /* Send it */ 1336 1337 li r3,0x20 /* Print eyecatcher */ 1338 bl dbgDchar /* Send it */ 1339 li r3,0x20 /* Print eyecatcher */ 1340 bl dbgDchar /* Send it */ 1341 li r3,0x20 /* Print eyecatcher */ 1342 bl dbgDchar /* Send it */ 1343 li r3,0x20 /* Print eyecatcher */ 1344 bl dbgDchar /* Send it */ 1345 li r3,0x20 /* Print eyecatcher */ 1346 bl dbgDchar /* Send it */ 1347 lwz r5,saver28(r13) /* Do register */ 1348 bl dbg4byte /* Print */ 1349 lwz r5,saver29(r13) /* Do register */ 1350 bl dbg4byte /* Print */ 1351 lwz r5,saver30(r13) /* Do register */ 1352 bl dbg4byte /* Print */ 1353 lwz r5,saver31(r13) /* Do register */ 1354 bl dbg4byte /* Print */ 1355 li r3,0x0A /* Linefeed */ 1356 bl dbgDchar /* Send it */ 1357 li r3,0x0D /* Carriage return */ 1358 bl dbgDchar /* Send it */ 1359 1360 /* Segment registers */ 1361 1362 li r3,0x53 /* Print eyecatcher */ 1363 bl dbgDchar /* Send it */ 1364 li r3,0x65 /* Print eyecatcher */ 1365 bl dbgDchar /* Send it */ 1366 li r3,0x67 /* Print eyecatcher */ 1367 bl dbgDchar /* Send it */ 1368 li r3,0x73 /* Print eyecatcher */ 1369 bl dbgDchar /* Send it */ 1370 li r3,0x20 /* Print eyecatcher */ 1371 bl dbgDchar /* Send it */ 1372 1373 lwz r5,savesr0(r13) /* Do register */ 1374 bl dbg4byte /* Print */ 1375 lwz r5,savesr1(r13) /* Do register */ 1376 bl dbg4byte /* Print */ 1377 lwz r5,savesr2(r13) /* Do register */ 1378 bl dbg4byte /* Print */ 1379 lwz r5,savesr3(r13) /* Do register */ 1380 bl dbg4byte /* Print */ 1381 li r3,0x0A /* Linefeed */ 1382 bl dbgDchar /* Send it */ 1383 li r3,0x0D /* Carriage return */ 1384 bl dbgDchar /* Send it */ 1385 1386 li r3,0x20 /* Print eyecatcher */ 1387 bl dbgDchar /* Send it */ 1388 li r3,0x20 /* Print eyecatcher */ 1389 bl dbgDchar /* Send it */ 1390 li r3,0x20 /* Print eyecatcher */ 1391 bl dbgDchar /* Send it */ 1392 li r3,0x20 /* Print eyecatcher */ 1393 bl dbgDchar /* Send it */ 1394 li r3,0x20 /* Print eyecatcher */ 1395 bl dbgDchar /* Send it */ 1396 lwz r5,savesr4(r13) /* Do register */ 1397 bl dbg4byte /* Print */ 1398 lwz r5,savesr5(r13) /* Do register */ 1399 bl dbg4byte /* Print */ 1400 lwz r5,savesr6(r13) /* Do register */ 1401 bl dbg4byte /* Print */ 1402 lwz r5,savesr7(r13) /* Do register */ 1403 bl dbg4byte /* Print */ 1404 li r3,0x0A /* Linefeed */ 1405 bl dbgDchar /* Send it */ 1406 li r3,0x0D /* Carriage return */ 1407 bl dbgDchar /* Send it */ 1408 1409 li r3,0x20 /* Print eyecatcher */ 1410 bl dbgDchar /* Send it */ 1411 li r3,0x20 /* Print eyecatcher */ 1412 bl dbgDchar /* Send it */ 1413 li r3,0x20 /* Print eyecatcher */ 1414 bl dbgDchar /* Send it */ 1415 li r3,0x20 /* Print eyecatcher */ 1416 bl dbgDchar /* Send it */ 1417 li r3,0x20 /* Print eyecatcher */ 1418 bl dbgDchar /* Send it */ 1419 lwz r5,savesr8(r13) /* Do register */ 1420 bl dbg4byte /* Print */ 1421 lwz r5,savesr9(r13) /* Do register */ 1422 bl dbg4byte /* Print */ 1423 lwz r5,savesr10(r13) /* Do register */ 1424 bl dbg4byte /* Print */ 1425 lwz r5,savesr11(r13) /* Do register */ 1426 bl dbg4byte /* Print */ 1427 li r3,0x0A /* Linefeed */ 1428 bl dbgDchar /* Send it */ 1429 li r3,0x0D /* Carriage return */ 1430 bl dbgDchar /* Send it */ 1431 1432 li r3,0x20 /* Print eyecatcher */ 1433 bl dbgDchar /* Send it */ 1434 li r3,0x20 /* Print eyecatcher */ 1435 bl dbgDchar /* Send it */ 1436 li r3,0x20 /* Print eyecatcher */ 1437 bl dbgDchar /* Send it */ 1438 li r3,0x20 /* Print eyecatcher */ 1439 bl dbgDchar /* Send it */ 1440 li r3,0x20 /* Print eyecatcher */ 1441 bl dbgDchar /* Send it */ 1442 lwz r5,savesr12(r13) /* Do register */ 1443 bl dbg4byte /* Print */ 1444 lwz r5,savesr13(r13) /* Do register */ 1445 bl dbg4byte /* Print */ 1446 lwz r5,savesr14(r13) /* Do register */ 1447 bl dbg4byte /* Print */ 1448 lwz r5,savesr15(r13) /* Do register */ 1449 bl dbg4byte /* Print */ 1450 li r3,0x0A /* Linefeed */ 1451 bl dbgDchar /* Send it */ 1452 li r3,0x0D /* Carriage return */ 1453 bl dbgDchar /* Send it */ 1454 1455 li r3,0x30 /* Print eyecatcher */ 1456 bl dbgDchar /* Send it */ 1457 li r3,0x31 /* Print eyecatcher */ 1458 bl dbgDchar /* Send it */ 1459 li r3,0x64 /* Print eyecatcher */ 1460 bl dbgDchar /* Send it */ 1461 li r3,0x64 /* Print eyecatcher */ 1462 bl dbgDchar /* Send it */ 1463 li r3,0x20 /* Print eyecatcher */ 1464 bl dbgDchar /* Send it */ 1465 lwz r5,savesrr0(r13) /* Do register */ 1466 bl dbg4byte /* Print */ 1467 lwz r5,savesrr1(r13) /* Do register */ 1468 bl dbg4byte /* Print */ 1469 lwz r5,savedar(r13) /* Do register */ 1470 bl dbg4byte /* Print */ 1471 lwz r5,savedsisr(r13) /* Do register */ 1472 bl dbg4byte /* Print */ 1473 li r3,0x0A /* Linefeed */ 1474 bl dbgDchar /* Send it */ 1475 li r3,0x0D /* Carriage return */ 1476 bl dbgDchar /* Send it */ 1477 1478 li r3,0x20 /* Print eyecatcher */ 1479 bl dbgDchar /* Send it */ 1480 li r3,0x6C /* Print eyecatcher */ 1481 bl dbgDchar /* Send it */ 1482 li r3,0x63 /* Print eyecatcher */ 1483 bl dbgDchar /* Send it */ 1484 li r3,0x63 /* Print eyecatcher */ 1485 bl dbgDchar /* Send it */ 1486 li r3,0x20 /* Print eyecatcher */ 1487 bl dbgDchar /* Send it */ 1488 lwz r5,savelr(r13) /* Do register */ 1489 bl dbg4byte /* Print */ 1490 lwz r5,savecr(r13) /* Do register */ 1491 bl dbg4byte /* Print */ 1492 lwz r5,savectr(r13) /* Do register */ 1493 bl dbg4byte /* Print */ 1494 li r3,0x0A /* Linefeed */ 1495 bl dbgDchar /* Send it */ 1496 li r3,0x0D /* Carriage return */ 1497 bl dbgDchar /* Send it */ 1498 mtlr r11 /* Get back the return */ 1499 dcbi 0,r10 /* ? */ 1500 #if !SIMPLESCC && !NOTQUITEASSIMPLE 1501 li r7,0 /* Get a zero */ 1502 mtdbatu 3,r7 /* Invalidate DBAT 3 upper */ 1503 mtdbatl 3,r7 /* Invalidate DBAT 3 lower */ 1504 #endif 1505 lis r3,HIGH_ADDR(fwdisplock) /* Get the display locker outer */ 1506 li r7,0 /* Get a zero */ 1507 ori r3,r3,LOW_ADDR(fwdisplock) /* Last part */ 1508 stw r7,0(r3) /* Clear display lock */ 1509 mtmsr r8 /* Restore the MSR */ 1510 isync /* Wait for it */ 1511 blr /* Leave... */ 1512 #endif 1513 1514 /* 1515 * Used for debugging to leave stuff in 0x380-0x3FF (128 bytes). 1516 * Mapping is V=R. Stores and loads are real. 1517 */ 1518 1519 .align 5 1520 .globl EXT(dbgCkpt) 1521 1522 LEXT(dbgCkpt) 1523 1524 mr r12,r0 /* Keep R0 pristene */ 1525 lis r0,HIGH_ADDR(dbgCkptCall) /* Top half of dbgCkptCall firmware call number */ 1526 ori r0,r0,LOW_ADDR(dbgCkptCall) /* Bottom half */ 1527 1528 sc /* Go stash the stuff */ 1529 1530 mr r0,r12 /* Restore R0 */ 1531 blr /* Return... */ 1532 1533 /* Here's the low-level part of dbgCkpt */ 1534 1535 .align 5 1536 .globl EXT(dbgCkptLL) 1537 1538 LEXT(dbgCkptLL) 1539 1540 1541 li r12,0x380 /* Point to output area */ 1542 li r1,32 /* Get line size */ 1543 dcbz 0,r12 /* Make sure we don't fetch a cache line */ 1544 1545 lwz r4,0x00(r3) /* Load up storage to checkpoint */ 1546 1547 dcbt r1,r3 /* Start in the next line */ 1548 1549 lwz r5,0x04(r3) /* Load up storage to checkpoint */ 1550 lwz r6,0x08(r3) /* Load up storage to checkpoint */ 1551 lwz r7,0x0C(r3) /* Load up storage to checkpoint */ 1552 lwz r8,0x10(r3) /* Load up storage to checkpoint */ 1553 lwz r9,0x14(r3) /* Load up storage to checkpoint */ 1554 lwz r10,0x18(r3) /* Load up storage to checkpoint */ 1555 lwz r11,0x1C(r3) /* Load up storage to checkpoint */ 1556 1557 add r3,r3,r1 /* Bump input */ 1558 1559 stw r4,0x00(r12) /* Store it */ 1560 stw r5,0x04(r12) /* Store it */ 1561 stw r6,0x08(r12) /* Store it */ 1562 stw r7,0x0C(r12) /* Store it */ 1563 stw r8,0x10(r12) /* Store it */ 1564 stw r9,0x14(r12) /* Store it */ 1565 stw r10,0x18(r12) /* Store it */ 1566 stw r11,0x1C(r12) /* Store it */ 1567 1568 dcbz r1,r12 /* Clear the next line */ 1569 add r12,r12,r1 /* Point to next output line */ 1570 1571 lwz r4,0x00(r3) /* Load up storage to checkpoint */ 1572 lwz r5,0x04(r3) /* Load up storage to checkpoint */ 1573 lwz r6,0x08(r3) /* Load up storage to checkpoint */ 1574 lwz r7,0x0C(r3) /* Load up storage to checkpoint */ 1575 lwz r8,0x10(r3) /* Load up storage to checkpoint */ 1576 lwz r9,0x14(r3) /* Load up storage to checkpoint */ 1577 lwz r10,0x18(r3) /* Load up storage to checkpoint */ 1578 lwz r11,0x1C(r3) /* Load up storage to checkpoint */ 1579 1580 dcbt r1,r3 /* Touch the next line */ 1581 add r3,r3,r1 /* Point to next input line */ 1582 1583 stw r4,0x00(r12) /* Store it */ 1584 stw r5,0x04(r12) /* Store it */ 1585 stw r6,0x08(r12) /* Store it */ 1586 stw r7,0x0C(r12) /* Store it */ 1587 stw r8,0x10(r12) /* Store it */ 1588 stw r9,0x14(r12) /* Store it */ 1589 stw r10,0x18(r12) /* Store it */ 1590 stw r11,0x1C(r12) /* Store it */ 1591 1592 dcbz r1,r12 /* Clear the next line */ 1593 add r12,r12,r1 /* Point to next output line */ 1594 1595 lwz r4,0x00(r3) /* Load up storage to checkpoint */ 1596 lwz r5,0x04(r3) /* Load up storage to checkpoint */ 1597 lwz r6,0x08(r3) /* Load up storage to checkpoint */ 1598 lwz r7,0x0C(r3) /* Load up storage to checkpoint */ 1599 lwz r8,0x10(r3) /* Load up storage to checkpoint */ 1600 lwz r9,0x14(r3) /* Load up storage to checkpoint */ 1601 lwz r10,0x18(r3) /* Load up storage to checkpoint */ 1602 lwz r11,0x1C(r3) /* Load up storage to checkpoint */ 1603 1604 dcbt r1,r3 /* Touch the next line */ 1605 add r3,r3,r1 /* Point to next input line */ 1606 1607 stw r4,0x00(r12) /* Store it */ 1608 stw r5,0x04(r12) /* Store it */ 1609 stw r6,0x08(r12) /* Store it */ 1610 stw r7,0x0C(r12) /* Store it */ 1611 stw r8,0x10(r12) /* Store it */ 1612 stw r9,0x14(r12) /* Store it */ 1613 stw r10,0x18(r12) /* Store it */ 1614 stw r11,0x1C(r12) /* Store it */ 1615 1616 dcbz r1,r12 /* Clear the next line */ 1617 add r12,r12,r1 /* Point to next output line */ 1618 1619 lwz r4,0x00(r3) /* Load up storage to checkpoint */ 1620 lwz r5,0x04(r3) /* Load up storage to checkpoint */ 1621 lwz r6,0x08(r3) /* Load up storage to checkpoint */ 1622 lwz r7,0x0C(r3) /* Load up storage to checkpoint */ 1623 lwz r8,0x10(r3) /* Load up storage to checkpoint */ 1624 lwz r9,0x14(r3) /* Load up storage to checkpoint */ 1625 lwz r10,0x18(r3) /* Load up storage to checkpoint */ 1626 lwz r11,0x1C(r3) /* Load up storage to checkpoint */ 1627 1628 stw r4,0x00(r12) /* Store it */ 1629 stw r5,0x04(r12) /* Store it */ 1630 stw r6,0x08(r12) /* Store it */ 1631 stw r7,0x0C(r12) /* Store it */ 1632 stw r8,0x10(r12) /* Store it */ 1633 stw r9,0x14(r12) /* Store it */ 1634 stw r10,0x18(r12) /* Store it */ 1635 stw r11,0x1C(r12) /* Store it */ 1636 1637 blr 1638 1639 1640 /* 1641 * Do Preemption. Forces a T_PREEMPT trap to allow a preemption to occur. 1642 */ 1643 1644 .align 5 1645 .globl EXT(DoPreemptLL) 1646 1647 LEXT(DoPreemptLL) 1648 1649 li r3,T_PREEMPT /* Set preemption interrupt value */ 1650 stw r3,saveexception(r13) /* Modify the exception type to preemption */ 1651 b EXT(FCReturn) ; Bye dudes... 1652 1653 1654 /* 1655 * Force 'rupt handler to dispatch with new context 1656 * R3 at the call contains the new savearea. 1657 * R4 at the call contains a return code to pass back in R3. 1658 * Forces a T_CSWITCH 1659 */ 1660 1661 .align 5 1662 .globl EXT(SwitchContextLL) 1663 1664 LEXT(SwitchContextLL) 1665 1666 li r3,T_CSWITCH /* Set context switch value */ 1667 stw r3,saveexception(r13) /* Modify the exception type to switch context */ 1668 b EXT(FCReturn) ; Bye dudes... 1669 1670 1671 /* 1672 * Create a fake I/O 'rupt. 1673 * Forces a T_INTERRUPT trap to pretend that an actual I/O interrupt occurred. 1674 */ 1675 1676 .align 5 1677 .globl EXT(CreateFakeIOLL) 1678 1679 LEXT(CreateFakeIOLL) 1680 1681 li r3,T_INTERRUPT /* Set external interrupt value */ 1682 stw r3,saveexception(r13) /* Modify the exception type to external */ 1683 b EXT(FCReturn) ; Bye dudes... 1684 1685 /* 1686 * Create a shutdown context 1687 * Forces a T_SHUTDOWN trap. 1688 */ 1689 1690 .align 5 1691 .globl EXT(CreateShutdownCTXLL) 1692 1693 LEXT(CreateShutdownCTXLL) 1694 1695 li r3,T_SHUTDOWN /* Set external interrupt value */ 1696 stw r3,saveexception(r13) /* Modify the exception type to external */ 1697 b EXT(FCReturn) ; Bye dudes... 1698 1699 /* 1700 * Create a fake decrementer 'rupt. 1701 * Forces a T_DECREMENTER trap to pretend that an actual decrementer interrupt occurred. 1702 */ 1703 1704 .align 5 1705 .globl EXT(CreateFakeDECLL) 1706 1707 LEXT(CreateFakeDECLL) 1708 1709 li r3,T_DECREMENTER /* Set decrementer interrupt value */ 1710 stw r3,saveexception(r13) /* Modify the exception type to external */ 1711 b EXT(FCReturn) ; Bye dudes... 1712 1713 /* 1714 * Choke the system. 1715 */ 1716 1717 .align 5 1718 .globl EXT(DoChokeLL) 1719 1720 LEXT(DoChokeLL) 1721 1722 li r3,T_CHOKE ; Set external interrupt value 1723 stw r3,saveexception(r13) ; Modify the exception type to external 1724 b EXT(FCReturn) ; Bye dudes... 1725 1726 /* 1727 * Null firmware call 1728 */ 1729 1730 .align 5 1731 .globl EXT(NullLL) 1732 1733 LEXT(NullLL) 1734 1735 li r3,T_IN_VAIN ; Set to just ignore this one 1736 b EXT(FCReturn) ; Bye dudes... 1737 1738 ; 1739 ; Null firmware call 1740 ; 1741 1742 .align 5 1743 .globl EXT(iNullLL) 1744 1745 LEXT(iNullLL) 1746 1747 mfspr r4,pmc1 ; Get stamp 1748 stw r4,0x6100+(9*16)+0x0(0) ; Save it 1749 #if 1 1750 mfspr r4,pmc2 ; Get stamp 1751 stw r4,0x6100+(9*16)+0x4(0) ; Save it 1752 mfspr r4,pmc3 ; Get stamp 1753 stw r4,0x6100+(9*16)+0x8(0) ; Save it 1754 mfspr r4,pmc4 ; Get stamp 1755 stw r4,0x6100+(9*16)+0xC(0) ; Save it 1756 #endif 1757 li r3,T_IN_VAIN ; Set to just ignore this one 1758 b EXT(FCReturn) ; Bye dudes... 1759 1760 ; 1761 ; Set the low level trace flags 1762 ; 1763 1764 .align 5 1765 .globl EXT(LLTraceSet) 1766 1767 LEXT(LLTraceSet) 1768 1769 mr r4,r3 ; Save the new value 1770 1771 lwz r3,traceMask(0) ; Get the old trace flags to pass back 1772 stw r4,traceMask(0) ; Replace with the new ones 1773 blr ; Leave... 1774 1775 #if 0 1776 1777 /* 1778 ; *************************************************************************** 1779 ; 1780 ; ----------------- Grateful Deb ---------------- 1781 ; 1782 ; Debugging: direct draw into main screen menu bar 1783 ; 1784 ; Takes R4 value, converts it to hex characters and displays it. 1785 ; 1786 ; Gotta make sure the DCBST is done to force the pixels from the cache. 1787 ; 1788 ; Position is taken as column, row (0 based) from R3. 1789 ; Characters are from hexfont, and are 16x16 pixels. 1790 ; 1791 ; Only works with two processors so far 1792 ; 1793 ; 1794 ; *************************************************************************** 1795 */ 1796 1797 #define GDfromright 20 1798 #define GDfontsize 16 1799 1800 .align 5 1801 .globl EXT(GratefulDeb) 1802 1803 LEXT(GratefulDeb) 1804 1805 mfspr r6,pir /* Get the PIR */ 1806 lis r5,HIGH_ADDR(EXT(GratefulDebWork)) /* Point to our work area */ 1807 rlwinm r6,r6,8,23,23 /* Get part of the offset to our processors area */ 1808 ori r5,r5,LOW_ADDR(EXT(GratefulDebWork)) /* Start building the address */ 1809 rlwimi r6,r6,2,21,21 /* Get the rest of the offset to our processors area */ 1810 add r6,r6,r5 /* Point at our CPU's work area */ 1811 mfmsr r5 /* Get that MSR */ 1812 stmw r0,GDsave(r6) /* Save all registers */ 1813 lwz r10,GDready(r6) /* See if we're all ready to go */ 1814 ori r0,r5,0x2000 /* Turn on the floating point */ 1815 mr r31,r6 /* Get a more sane base register */ 1816 mr. r10,r10 /* Are we all set? */ 1817 mtmsr r0 /* Enable floating point */ 1818 isync 1819 1820 stfd f0,GDfp0(r31) /* Save FP */ 1821 stfd f1,GDfp1(r31) /* Save FP */ 1822 stfd f2,GDfp2(r31) /* Save FP */ 1823 stfd f3,GDfp3(r31) /* Save FP */ 1824 1825 beq- GDbailout /* Go and bail... */ 1826 1827 rlwinm r25,r3,0,16,31 /* Isolate just the row number */ 1828 lwz r28,GDtopleft(r31) /* Get the physical address of our line 0 */ 1829 rlwinm r3,r3,16,16,31 /* Isolate the column number */ 1830 lwz r27,GDrowbytes(r31) /* Get the number of bytes per row */ 1831 lwz r9,GDrowchar(r31) /* Get the number of bytes per row of full leaded charactrers */ 1832 lwz r26,GDdepth(r31) /* Get the bit depth */ 1833 mullw r25,r25,r9 /* get offset to the row to write in bytes */ 1834 lwz r24,GDcollgn(r31) /* Get the size of columns in bytes */ 1835 add r25,r28,r25 /* Physical address of row */ 1836 mullw r3,r3,r24 /* Get byte offset to first output column */ 1837 1838 li r9,32 /* Get the initial shift calc */ 1839 1840 lis r20,HIGH_ADDR(hexfont) /* Point to the font */ 1841 1842 li r18,GDfontsize /* Get the number of rows in the font */ 1843 ori r20,r20,LOW_ADDR(hexfont) /* Point to the low part */ 1844 add r21,r25,r3 /* Physical address of top left output pixel */ 1845 sub r9,r9,r26 /* Get right shift justifier for pixel size */ 1846 li r7,32 /* Number of bits per word */ 1847 1848 startNybble: 1849 la r6,GDrowbuf1(r31) /* Point to the row buffer */ 1850 li r19,8 /* Get the number of characters in a row */ 1851 1852 getNybble: rlwinm r10,r4,9,23,26 /* Get the top nybble * 32 */ 1853 rlwinm r4,r4,4,0,31 /* Rotate a nybble */ 1854 add r10,r20,r10 /* Point to the character in the font */ 1855 1856 rlwinm r16,r26,4,0,27 /* Width of row in actual bits */ 1857 lhz r15,0(r10) /* Get the next row of the font */ 1858 1859 rendrow: rlwinm r17,r15,16,0,0 /* Get the next font pixel in the row */ 1860 rlwinm r15,r15,1,16,31 /* Move in the next font pixel */ 1861 srawi r17,r17,31 /* Fill with 1s if black and 0s if white (reversed) */ 1862 1863 slw r14,r14,r26 /* Make room for our pixel in a register */ 1864 srw r17,r17,r9 /* Isolate one pixels worth of black or white */ 1865 sub. r7,r7,r26 /* See how may bits are left */ 1866 sub r16,r16,r26 /* Count how many bits are left to store for this row */ 1867 or r14,r14,r17 /* Put in the pixel */ 1868 bne+ notfull /* Finish rendering this word */ 1869 1870 not r14,r14 /* Invert to black on white */ 1871 stw r14,0(r6) /* Write out the word */ 1872 li r7,32 /* Bit per word count */ 1873 addi r6,r6,4 /* Point to the next word */ 1874 1875 notfull: mr. r16,r16 /* Have we finished the whole character row? */ 1876 bne+ rendrow /* Finish rendering the row */ 1877 1878 addic. r19,r19,-1 /* Are we finished with a whole display row yet? */ 1879 bne+ getNybble /* Not yet... */ 1880 1881 la r6,GDrowbuf1(r31) /* Point to the row buffer */ 1882 rlwinm r19,r26,31,0,29 /* Number of cache lines (depth/2) */ 1883 mr r14,r21 /* Get the frame buffer address */ 1884 1885 // BREAKPOINT_TRAP 1886 1887 blitrow: lfd f0,0(r6) /* Load a line */ 1888 lfd f1,8(r6) 1889 lfd f2,16(r6) 1890 lfd f3,24(r6) 1891 1892 stfd f0,0(r14) /* Blit a line */ 1893 stfd f1,8(r14) 1894 stfd f2,16(r14) 1895 stfd f3,24(r14) 1896 1897 addi r6,r6,32 /* Next buffered line */ 1898 1899 dcbst 0,r14 /* Force the line to the screen */ 1900 sync /* Make sure the line is on it's way */ 1901 eieio /* Make sure we beat the invalidate */ 1902 dcbi 0,r14 /* Make sure we leave no paradox */ 1903 1904 addic. r19,r19,-1 /* Done all lines yet? */ 1905 addi r14,r14,32 /* Point to the next output */ 1906 bne+ blitrow /* Nope, do it some more... */ 1907 1908 addic. r18,r18,-1 /* Have we done all the rows in character yet? */ 1909 addi r20,r20,2 /* Offset the font to the next row */ 1910 add r21,r21,r27 /* Point to start of next row */ 1911 bne+ startNybble /* Nope, go through the word one more time... */ 1912 1913 GDbailout: mr r1,r31 /* Move the workarea base */ 1914 1915 lfd f0,GDfp0(r31) /* Restore FP */ 1916 lfd f1,GDfp1(r31) /* Restore FP */ 1917 lfd f2,GDfp2(r31) /* Restore FP */ 1918 lfd f3,GDfp3(r31) /* Restore FP */ 1919 1920 mtmsr r5 /* Disable floating point */ 1921 isync 1922 1923 lmw r3,GDsave+12(r1) /* Restore most registers */ 1924 lwz r0,GDsave(r1) /* Restore R0 */ 1925 lwz r1,GDsave+4(r1) /* Finally, R1 */ 1926 blr /* Leave... */ 1927 1928 1929 /* 1930 * void GratefulDebDisp(unsigned int coord, unsigned int data); 1931 */ 1932 1933 1934 .align 5 1935 .globl EXT(GratefulDebDisp) 1936 1937 LEXT(GratefulDebDisp) 1938 1939 mfmsr r9 /* Save the current MSR */ 1940 mflr r7 /* Save the return */ 1941 andi. r8,r9,0x7FCF /* Clear interrupt and translation */ 1942 mtmsr r8 /* Turn 'em really off */ 1943 isync /* Make sure about the translation part */ 1944 bl EXT(GratefulDeb) /* Display it */ 1945 mtmsr r9 /* Restore interrupt and translation */ 1946 mtlr r7 /* Restore return */ 1947 isync /* Make sure */ 1948 blr 1949 1950 1951 #endif 1952 1953 /* 1954 * void checkNMI(void); 1955 */ 1956 1957 1958 .align 5 1959 .globl EXT(checkNMI) 1960 1961 LEXT(checkNMI) 1962 1963 mfmsr r9 /* Save it */ 1964 andi. r8,r9,0x7FCF /* Clear it */ 1965 mtmsr r8 /* Disable it */ 1966 isync /* Fence it */ 1967 lis r7,0xF300 /* Find it */ 1968 lis r2,hi16(MASK(MSR_VEC)) ; Get the vector enable 1969 ori r7,r7,0x0020 /* Find it */ 1970 ori r2,r2,lo16(MASK(MSR_FP)) ; Get the FP enable 1971 dcbi 0,r7 /* Toss it */ 1972 sync /* Sync it */ 1973 andc r9,r9,r2 ; Clear VEC and FP enables 1974 eieio /* Get it */ 1975 lwz r6,0x000C(r7) /* Check it */ 1976 eieio /* Fence it */ 1977 dcbi 0,r7 /* Toss it */ 1978 rlwinm. r4,r6,0,19,19 /* Check it */ 1979 rlwinm r6,r6,0,20,18 /* Clear it */ 1980 sync /* Sync it */ 1981 eieio /* Fence it */ 1982 beq+ xnonmi /* Branch on it */ 1983 1984 stw r6,0x0008(r7) /* Reset it */ 1985 sync /* Sync it */ 1986 dcbi 0,r6 /* Toss it */ 1987 eieio /* Fence it */ 1988 1989 mtmsr r9 /* Restore it */ 1990 isync /* Hold it */ 1991 1992 BREAKPOINT_TRAP /* Kill it */ 1993 blr /* Return from it */ 1994 1995 xnonmi: /* Label it */ 1996 mtmsr r9 /* Restore it */ 1997 isync /* Hold it */ 1998 blr /* Return from it */ 1999 2000 ; 2001 ; Saves floating point registers 2002 ; 2003 2004 .align 5 2005 .globl EXT(stFloat) 2006 2007 LEXT(stFloat) 2008 2009 lis r2,hi16(MASK(MSR_VEC)) ; Get the vector enable 2010 li r4,0 2011 ori r2,r2,lo16(MASK(MSR_FP)) ; Get the FP enable 2012 ori r4,r4,lo16(MASK(MSR_EE)) ; Get the EE bit 2013 2014 mfmsr r0 ; Save the MSR 2015 2016 andc r4,r0,r4 ; Clear EE 2017 ori r4,r4,lo16(MASK(MSR_FP)) ; Enable floating point 2018 mtmsr r4 2019 isync 2020 2021 andc r0,r0,r2 ; Clear VEC and FP enables 2022 2023 stfd f0,0x00(r3) 2024 stfd f1,0x08(r3) 2025 stfd f2,0x10(r3) 2026 stfd f3,0x18(r3) 2027 stfd f4,0x20(r3) 2028 stfd f5,0x28(r3) 2029 stfd f6,0x30(r3) 2030 stfd f7,0x38(r3) 2031 stfd f8,0x40(r3) 2032 stfd f9,0x48(r3) 2033 stfd f10,0x50(r3) 2034 stfd f11,0x58(r3) 2035 stfd f12,0x60(r3) 2036 stfd f13,0x68(r3) 2037 stfd f14,0x70(r3) 2038 stfd f15,0x78(r3) 2039 stfd f16,0x80(r3) 2040 stfd f17,0x88(r3) 2041 stfd f18,0x90(r3) 2042 stfd f19,0x98(r3) 2043 stfd f20,0xA0(r3) 2044 stfd f21,0xA8(r3) 2045 stfd f22,0xB0(r3) 2046 stfd f23,0xB8(r3) 2047 stfd f24,0xC0(r3) 2048 stfd f25,0xC8(r3) 2049 stfd f26,0xD0(r3) 2050 stfd f27,0xD8(r3) 2051 stfd f28,0xE0(r3) 2052 stfd f29,0xE8(r3) 2053 stfd f30,0xF0(r3) 2054 stfd f31,0xF8(r3) 2055 mffs f0 2056 stfd f0,0x100(r3) 2057 lfd f0,0x00(r3) 2058 mtmsr r0 2059 isync 2060 blr 2061 2062 2063 ; 2064 ; Saves vector registers. Returns 0 if non-Altivec machine. 2065 ; 2066 2067 .align 5 2068 .globl EXT(stVectors) 2069 2070 LEXT(stVectors) 2071 2072 lis r2,hi16(MASK(MSR_VEC)) ; Get the vector enable 2073 li r4,0 2074 ori r2,r2,lo16(MASK(MSR_FP)) ; Get the FP enable 2075 ori r4,r4,lo16(MASK(MSR_EE)) ; Get the EE bit 2076 2077 mfsprg r6,2 ; Get features 2078 mr r5,r3 ; Save area address 2079 rlwinm. r6,r6,0,pfAltivecb,pfAltivecb ; Do we have Altivec? 2080 li r3,0 ; Assume failure 2081 beqlr- ; No... 2082 2083 mfmsr r0 ; Save the MSR 2084 2085 andc r4,r0,r4 ; Clear EE 2086 2087 oris r4,r4,hi16(MASK(MSR_VEC)) ; Enable vectors 2088 mtmsr r4 2089 isync 2090 2091 andc r0,r0,r2 ; Clear FP and VEC 2092 2093 stvxl v0,0,r5 2094 addi r5,r5,16 2095 stvxl v1,0,r5 2096 addi r5,r5,16 2097 stvxl v2,0,r5 2098 addi r5,r5,16 2099 stvxl v3,0,r5 2100 addi r5,r5,16 2101 stvxl v4,0,r5 2102 addi r5,r5,16 2103 stvxl v5,0,r5 2104 addi r5,r5,16 2105 stvxl v6,0,r5 2106 addi r5,r5,16 2107 stvxl v7,0,r5 2108 addi r5,r5,16 2109 stvxl v8,0,r5 2110 addi r5,r5,16 2111 stvxl v9,0,r5 2112 addi r5,r5,16 2113 stvxl v10,0,r5 2114 addi r5,r5,16 2115 stvxl v11,0,r5 2116 addi r5,r5,16 2117 stvxl v12,0,r5 2118 addi r5,r5,16 2119 stvxl v13,0,r5 2120 addi r5,r5,16 2121 stvxl v14,0,r5 2122 addi r5,r5,16 2123 stvxl v15,0,r5 2124 addi r5,r5,16 2125 stvxl v16,0,r5 2126 addi r5,r5,16 2127 stvxl v17,0,r5 2128 addi r5,r5,16 2129 stvxl v18,0,r5 2130 addi r5,r5,16 2131 stvxl v19,0,r5 2132 addi r5,r5,16 2133 stvxl v20,0,r5 2134 addi r5,r5,16 2135 stvxl v21,0,r5 2136 addi r5,r5,16 2137 stvxl v22,0,r5 2138 addi r5,r5,16 2139 stvxl v23,0,r5 2140 addi r5,r5,16 2141 stvxl v24,0,r5 2142 addi r5,r5,16 2143 stvxl v25,0,r5 2144 addi r5,r5,16 2145 stvxl v26,0,r5 2146 addi r5,r5,16 2147 stvxl v27,0,r5 2148 addi r5,r5,16 2149 stvxl v28,0,r5 2150 addi r5,r5,16 2151 stvxl v29,0,r5 2152 addi r5,r5,16 2153 stvxl v30,0,r5 2154 addi r5,r5,16 2155 stvxl v31,0,r5 2156 mfvscr v31 2157 addi r6,r5,16 2158 stvxl v31,0,r6 2159 li r3,1 2160 lvxl v31,0,r5 2161 mtmsr r0 2162 isync 2163 2164 blr 2165 2166 2167 ; 2168 ; Saves yet more registers 2169 ; 2170 2171 .align 5 2172 .globl EXT(stSpecrs) 2173 2174 LEXT(stSpecrs) 2175 2176 2177 lis r2,hi16(MASK(MSR_VEC)) ; Get the vector enable 2178 li r4,0 2179 ori r2,r2,lo16(MASK(MSR_FP)) ; Get the FP enable 2180 ori r4,r4,lo16(MASK(MSR_EE)) ; Get the EE bit 2181 2182 mfsprg r9,2 ; Get feature flags 2183 mtcrf 0x02,r9 ; move pf64Bit cr6 2184 2185 mfmsr r0 ; Save the MSR 2186 andc r0,r0,r2 ; Turn off VEC and FP 2187 andc r4,r0,r4 ; And EE 2188 mtmsr r4 2189 isync 2190 2191 mfpvr r12 2192 stw r12,4(r3) 2193 rlwinm r12,r12,16,16,31 2194 2195 bt++ pf64Bitb,stsSF1 ; skip if 64-bit (only they take the hint) 2196 2197 mfdbatu r4,0 2198 mfdbatl r5,0 2199 mfdbatu r6,1 2200 mfdbatl r7,1 2201 mfdbatu r8,2 2202 mfdbatl r9,2 2203 mfdbatu r10,3 2204 mfdbatl r11,3 2205 stw r4,8(r3) 2206 stw r5,12(r3) 2207 stw r6,16(r3) 2208 stw r7,20(r3) 2209 stw r8,24(r3) 2210 stw r9,28(r3) 2211 stw r10,32(r3) 2212 stw r11,36(r3) 2213 2214 mfibatu r4,0 2215 mfibatl r5,0 2216 mfibatu r6,1 2217 mfibatl r7,1 2218 mfibatu r8,2 2219 mfibatl r9,2 2220 mfibatu r10,3 2221 mfibatl r11,3 2222 stw r4,40(r3) 2223 stw r5,44(r3) 2224 stw r6,48(r3) 2225 stw r7,52(r3) 2226 stw r8,56(r3) 2227 stw r9,60(r3) 2228 stw r10,64(r3) 2229 stw r11,68(r3) 2230 2231 mfsprg r4,0 2232 mfsprg r5,1 2233 mfsprg r6,2 2234 mfsprg r7,3 2235 stw r4,72(r3) 2236 stw r5,76(r3) 2237 stw r6,80(r3) 2238 stw r7,84(r3) 2239 2240 mfsdr1 r4 2241 stw r4,88(r3) 2242 2243 la r4,92(r3) 2244 li r5,0 2245 2246 stSnsr: mfsrin r6,r5 2247 addis r5,r5,0x1000 2248 stw r6,0(r4) 2249 mr. r5,r5 2250 addi r4,r4,4 2251 bne+ stSnsr 2252 2253 cmplwi r12,PROCESSOR_VERSION_750 2254 mfspr r4,hid0 2255 stw r4,(39*4)(r3) 2256 2257 li r4,0 2258 li r5,0 2259 li r6,0 2260 li r7,0 2261 2262 mfspr r4,hid1 2263 mfspr r5,l2cr 2264 mfspr r6,msscr0 2265 mfspr r7,msscr1 2266 2267 stw r4,(40*4)(r3) 2268 stw r6,(42*4)(r3) 2269 stw r5,(41*4)(r3) 2270 stw r7,(43*4)(r3) 2271 2272 li r4,0 2273 beq isis750 2274 2275 mfspr r4,pir 2276 isis750: stw r4,0(r3) 2277 2278 li r4,0 2279 li r5,0 2280 li r6,0 2281 li r7,0 2282 blt- b4750 2283 2284 mfspr r4,thrm1 2285 mfspr r5,thrm2 2286 mfspr r6,thrm3 2287 mfspr r7,ictc 2288 2289 b4750: stw r4,(44*4)(r3) 2290 stw r5,(45*4)(r3) 2291 stw r6,(46*4)(r3) 2292 stw r7,(47*4)(r3) 2293 2294 li r4,0 2295 li r6,0 2296 cmplwi r12,PROCESSOR_VERSION_7400 2297 bne nnmax 2298 2299 mfspr r6,dabr 2300 mfpvr r5 2301 rlwinm r5,r5,0,16,31 2302 cmplwi r5,0x1101 2303 beq gnmax 2304 cmplwi r5,0x1102 2305 bne nnmax 2306 2307 gnmax: mfspr r4,1016 2308 2309 nnmax: stw r4,(48*4)(r3) 2310 stw r6,(49*4)(r3) 2311 2312 mtmsr r0 2313 isync 2314 2315 blr 2316 2317 stsSF1: mfsprg r4,0 2318 mfsprg r5,1 2319 mfsprg r6,2 2320 mfsprg r7,3 2321 std r4,(18*4)(r3) 2322 std r5,(20*4)(r3) 2323 std r6,(22*4)(r3) 2324 std r7,(24*4)(r3) 2325 2326 mfsdr1 r4 2327 std r4,(26*4)(r3) 2328 2329 mfspr r4,hid0 2330 std r4,(28*4)(r3) 2331 mfspr r4,hid1 2332 std r4,(30*4)(r3) 2333 mfspr r4,hid4 2334 std r4,(32*4)(r3) 2335 mfspr r4,hid5 2336 std r4,(34*4)(r3) 2337 2338 2339 stsSF2: li r5,0 2340 la r4,(80*4)(r3) 2341 2342 stsslbm: slbmfee r6,r5 2343 slbmfev r7,r5 2344 std r6,0(r4) 2345 std r7,8(r4) 2346 addi r5,r5,1 2347 cmplwi r5,64 2348 addi r4,r4,16 2349 blt stsslbm 2350 2351 mtmsr r0 2352 isync 2353 2354 blr 2355 2356 ; 2357 ; fwEmMck - this forces the hardware to emulate machine checks 2358 ; Only valid on 64-bit machines 2359 ; Note: we want interruptions disabled here 2360 ; 2361 2362 .globl EXT(fwEmMck) 2363 2364 .align 5 2365 2366 LEXT(fwEmMck) 2367 2368 2369 rlwinm r3,r3,0,1,0 ; Copy low of high high - scomd 2370 rlwinm r5,r5,0,1,0 ; Copy low of high high - hid1 2371 rlwinm r7,r7,0,1,0 ; Copy low of high high - hid4 2372 rlwimi r3,r4,0,0,31 ; Copy low of low low 2373 rlwimi r5,r6,0,0,31 ; Copy low of low low 2374 rlwimi r7,r8,0,0,31 ; Copy low of low low 2375 2376 lis r9,3 ; Start forming hid1 error inject mask 2377 lis r10,hi16(0x01084083) ; Start formaing hid4 error inject mask 2378 ori r9,r9,0xC000 ; Next bit 2379 ori r10,r10,lo16(0x01084083) ; Next part 2380 sldi r9,r9,32 ; Shift up high 2381 sldi r10,r10,8 ; Shift into position 2382 2383 mfspr r0,hid1 ; Get hid1 2384 mfspr r2,hid4 ; and hid4 2385 2386 and r5,r5,r9 ; Keep only error inject controls - hid1 2387 and r7,r7,r10 ; Keep only error inject controls - hid4 2388 2389 andc r0,r0,r9 ; Clear error inject controls hid1 2390 andc r2,r2,r10 ; Clear error inject controls hid4 2391 2392 or r0,r0,r5 ; Add in the new controls hid1 2393 or r2,r2,r7 ; Add in the new controls hid4 2394 2395 /* ? */ 2396 #if 0 2397 lis r12,CoreErrI ; Get the error inject controls 2398 sync 2399 2400 mtspr scomd,r3 ; Set the error inject controls 2401 mtspr scomc,r12 ; Request error inject 2402 mfspr r11,scomc ; Get back the status (we just ignore it) 2403 #endif 2404 sync 2405 isync 2406 2407 mtspr hid1,r0 ; Move in hid1 controls 2408 mtspr hid1,r0 ; We need to do it twice 2409 isync 2410 2411 sync 2412 mtspr hid4,r2 ; Move in hid4 controls 2413 isync 2414 2415 blr ; Leave... 2416 2417 ; 2418 ; fwSCOMrd - read/write SCOM 2419 ; 2420 .align 5 2421 .globl EXT(fwSCOM) 2422 2423 LEXT(fwSCOM) 2424 2425 lhz r12,scomfunc(r3) ; Get the function 2426 lwz r4,scomreg(r3) ; Get the register 2427 rldicr r4,r4,8,47 ; Position for SCOM 2428 2429 mr. r12,r12 ; See if read or write 2430 bne fwSCwrite ; Go do a write 2431 2432 mfsprg r0,2 ; Get the feature flags 2433 ori r4,r4,0x8000 ; Set to read data 2434 rlwinm. r0,r0,pfSCOMFixUpb+1,31,31 ; Set shift if we need a fix me up 2435 sync 2436 2437 mtspr scomc,r4 ; Request the register 2438 mfspr r11,scomd ; Get the register contents 2439 mfspr r10,scomc ; Get back the status 2440 sync 2441 isync 2442 2443 sld r11,r11,r0 ; Fix up if needed 2444 2445 std r11,scomdata(r3) ; Save result 2446 eieio 2447 std r10,scomstat(r3) ; Save status 2448 2449 blr 2450 2451 fwSCwrite: ld r5,scomdata(r3) ; Get the data 2452 2453 sync 2454 2455 mtspr scomd,r5 ; Set the data 2456 mtspr scomc,r4 ; Set it 2457 mfspr r10,scomc ; Get back the status 2458 sync 2459 isync 2460 2461 std r10,scomstat(r3) ; Save status 2462 2463 blr 2464 2465 ; 2466 ; diagTrap - this is used to trigger checks from user space 2467 ; any "twi 31,r31,0xFFFx" will come here (x = 0 to F). 2468 ; On entry R3 points to savearea. 2469 ; R4 is the "x" from instruction; 2470 ; Pass back 1 to no-op twi and return to user 2471 ; Pass back 0 to treat as normal twi. 2472 ; 2473 2474 .globl EXT(diagTrap) 2475 2476 .align 5 2477 2478 LEXT(diagTrap) 2479 2480 li r3,1 ; Ignore TWI 2481 blr ; Leave... 2482 2483 2484 2485 2486 ; 2487 ; setPmon - this is used to manipulate MMCR0 and MMCR1 2488 2489 .globl EXT(setPmon) 2490 2491 .align 5 2492 2493 LEXT(setPmon) 2494 2495 li r0,0 2496 isync 2497 mtspr mmcr0,r0 ; Clear MMCR0 2498 mtspr mmcr1,r0 ; Clear MMCR1 2499 mtspr pmc1,r0 2500 mtspr pmc2,r0 2501 mtspr pmc3,r0 2502 mtspr pmc4,r0 2503 2504 isync 2505 2506 mtspr mmcr0,r3 ; Set MMCR0 2507 mtspr mmcr1,r4 ; Set MMCR1 2508 isync 2509 blr ; Leave... 2510 2511
Cache object: 132130b78a0e78ed002fce4c92803e00
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