Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
[ source navigation ] [ diff markup ] [ identifier search ] [ freetext search ] [ file search ] [ list types ] [ track identifier ]
FreeBSD/Linux Kernel Cross Reference
sys/osfmk/ppc/hw_perfmon_mmcr.h
Version:
- FREEBSD - FREEBSD-13-STABLE - FREEBSD-13-0 - FREEBSD-12-STABLE - FREEBSD-12-0 - FREEBSD-11-STABLE - FREEBSD-11-0 - FREEBSD-10-STABLE - FREEBSD-10-0 - FREEBSD-9-STABLE - FREEBSD-9-0 - FREEBSD-8-STABLE - FREEBSD-8-0 - FREEBSD-7-STABLE - FREEBSD-7-0 - FREEBSD-6-STABLE - FREEBSD-6-0 - FREEBSD-5-STABLE - FREEBSD-5-0 - FREEBSD-4-STABLE - FREEBSD-3-STABLE - FREEBSD22 - l41 - OPENBSD - linux-2.6 - MK84 - PLAN9 - xnu-8792
SearchContext: - none - 3 - 10
SearchContext: - none - 3 - 10
1 /* 2 * Copyright (c) 2002 Apple Computer, Inc. All rights reserved. 3 * 4 * @APPLE_LICENSE_HEADER_START@ 5 * 6 * The contents of this file constitute Original Code as defined in and 7 * are subject to the Apple Public Source License Version 1.1 (the 8 * "License"). You may not use this file except in compliance with the 9 * License. Please obtain a copy of the License at 10 * http://www.apple.com/publicsource and read it before using this file. 11 * 12 * This Original Code and all software distributed under the License are 13 * distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, EITHER 14 * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES, 15 * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT. Please see the 17 * License for the specific language governing rights and limitations 18 * under the License. 19 * 20 * @APPLE_LICENSE_HEADER_END@ 21 */ 22 23 #ifndef _HW_PERFMON_MMCR_H_ 24 #define _HW_PERFMON_MMCR_H_ 25 26 #ifndef __ppc__ 27 #error This file is only useful on PowerPC. 28 #endif 29 30 typedef struct { 31 uint32_t disable_counters_always : 1; /* 0: disable counters */ 32 uint32_t disable_counters_supervisor : 1; /* 1: disable counters (supervisor) */ 33 uint32_t disable_counters_user : 1; /* 2: disable counters (user) */ 34 uint32_t disable_counters_marked : 1; /* 3: disable counters (marked bit == 1) */ 35 uint32_t disable_counters_unmarked : 1; /* 4: disable counters (marked bit == 0) */ 36 uint32_t enable_pmi : 1; /* 5: performance monitor interrupt enable */ 37 uint32_t on_pmi_stop_counting : 1; /* 6: disable counters (pmi) */ 38 uint32_t timebase_bit_selector : 2; /* 7-8: TBL bit for TB events */ 39 uint32_t enable_timebase_pmi : 1; /* 9: enable pmi on TBL bit transition */ 40 uint32_t threshold_value : 6; /* 10-15: threshold value */ 41 uint32_t enable_pmi_on_pmc1 : 1; /* 16: enable pmi on pmc1 overflow */ 42 uint32_t enable_pmi_on_pmcn : 1; /* 17: enable pmi on any pmc except pmc1 overflow */ 43 uint32_t enable_pmi_trigger : 1; /* 18: enable triggering of pmcn by pmc1 overflow */ 44 uint32_t pmc1_event : 7; /* 19-25: pmc1 event select */ 45 uint32_t pmc2_event : 6; /* 26-31: pmc2 event select */ 46 } ppc32_mmcr0_bits_t; 47 48 typedef union { 49 uint32_t value; 50 ppc32_mmcr0_bits_t field; 51 } ppc32_mmcr0_reg_t; 52 53 typedef struct { 54 uint32_t pmc3_event : 5; 55 uint32_t pmc4_event : 5; 56 uint32_t pmc5_event : 5; 57 uint32_t pmc6_event : 6; 58 uint32_t /*reserved*/ : 11; 59 } ppc32_mmcr1_bits_t; 60 61 typedef union { 62 uint32_t value; 63 ppc32_mmcr1_bits_t field; 64 } ppc32_mmcr1_reg_t; 65 66 typedef struct { 67 uint32_t threshold_multiplier : 1; 68 uint32_t /*reserved*/ : 31; 69 } ppc32_mmcr2_bits_t; 70 71 typedef union { 72 uint32_t value; 73 ppc32_mmcr2_bits_t field; 74 } ppc32_mmcr2_reg_t; 75 76 typedef struct { 77 uint32_t /* reserved */ : 32; /* 0-31: reserved */ 78 uint32_t disable_counters_always : 1; /* 32: disable counters */ 79 uint32_t disable_counters_supervisor : 1; /* 33: disable counters (supervisor) */ 80 uint32_t disable_counters_user : 1; /* 34: disable counters (user) */ 81 uint32_t disable_counters_marked : 1; /* 35: disable counters (marked bit == 1) */ 82 uint32_t disable_counters_unmarked : 1; /* 36: disable counters (marked bit == 0) */ 83 uint32_t enable_pmi : 1; /* 37: performance monitor interrupt enable */ 84 uint32_t on_pmi_stop_counting : 1; /* 38: disable counters (pmi) */ 85 uint32_t timebase_bit_selector : 2; /* 39-40: TBL bit for timebase events */ 86 uint32_t enable_timebase_pmi : 1; /* 41: enable pmi on TBL bit transition */ 87 uint32_t threshold_value : 6; /* 42-47: threshold value */ 88 uint32_t enable_pmi_on_pmc1 : 1; /* 48: enable pmi on pmc1 overflow */ 89 uint32_t enable_pmi_on_pmcn : 1; /* 49: enable pmi on any pmc except pmc1 overflow */ 90 uint32_t enable_pmi_trigger : 1; /* 50: enable triggering of pmcn by pmc1 overflow */ 91 uint32_t pmc1_event : 5; /* 51-55: pmc1 event select */ 92 uint32_t perfmon_event_occurred : 1; /* 56: performance monitor event has occurred */ 93 uint32_t /* reserved */ : 1; /* 57: reserved */ 94 uint32_t pmc2_event : 5; /* 58-62: pmc2 event select */ 95 uint32_t disable_counters_hypervisor : 1; /* 63: disable counters (hypervisor) */ 96 } ppc64_mmcr0_bits_t; 97 98 typedef union { 99 uint64_t value; 100 ppc64_mmcr0_bits_t field; 101 } ppc64_mmcr0_reg_t; 102 103 typedef struct { 104 uint32_t ttm0_select : 2; /* 0-1: FPU/ISU/IFU/VMX unit select */ 105 uint32_t /* reserved */ : 1; /* 2: reserved */ 106 uint32_t ttm1_select : 2; /* 3-4: IDU/ISU/ISU unit select */ 107 uint32_t /* reserved */ : 1; /* 5: reserved */ 108 uint32_t ttm2_select : 2; /* 6-7: IFU/LSU0 unit select */ 109 uint32_t /* reserved */ : 1; /* 8: reserved */ 110 uint32_t ttm3_select : 2; /* 9-10: LSU1 select */ 111 uint32_t /* reserved */ : 1; /* 11: reserved */ 112 uint32_t lane0_select : 2; /* 12-13: Byte lane 0 unit select (TD_CP_DBG0SEL) */ 113 uint32_t lane1_select : 2; /* 14-15: Byte lane 1 unit select (TD_CP_DBG1SEL) */ 114 uint32_t lane2_select : 2; /* 16-17: Byte lane 2 unit select (TD_CP_DBG2SEL) */ 115 uint32_t lane3_select : 2; /* 18-19: Byte lane 3 unit select (TD_CP_DBG3SEL) */ 116 uint32_t /* reserved */ : 4; /* 20-23: reserved */ 117 uint32_t pmc1_adder_lane_select : 1; /* 24: PMC1 Event Adder Lane Select (PMC1_ADDER_SELECT) */ 118 uint32_t pmc2_adder_lane_select : 1; /* 25: PMC2 Event Adder Lane Select (PMC2_ADDER_SELECT) */ 119 uint32_t pmc6_adder_lane_select : 1; /* 26: PMC6 Event Adder Lane Select (PMC6_ADDER_SELECT) */ 120 uint32_t pmc5_adder_lane_select : 1; /* 27: PMC5 Event Adder Lane Select (PMC5_ADDER_SELECT) */ 121 uint32_t pmc8_adder_lane_select : 1; /* 28: PMC8 Event Adder Lane Select (PMC8_ADDER_SELECT) */ 122 uint32_t pmc7_adder_lane_select : 1; /* 29: PMC7 Event Adder Lane Select (PMC7_ADDER_SELECT) */ 123 uint32_t pmc3_adder_lane_select : 1; /* 30: PMC3 Event Adder Lane Select (PMC3_ADDER_SELECT) */ 124 uint32_t pmc4_adder_lane_select : 1; /* 31: PMC4 Event Adder Lane Select (PMC4_ADDER_SELECT) */ 125 uint32_t pmc3_event : 5; /* 32-36: pmc3 event select */ 126 uint32_t pmc4_event : 5; /* 37-41: pmc4 event select */ 127 uint32_t pmc5_event : 5; /* 42-46: pmc5 event select */ 128 uint32_t pmc6_event : 5; /* 47-51: pmc6 event select */ 129 uint32_t pmc7_event : 5; /* 52-56: pmc7 event select */ 130 uint32_t pmc8_event : 5; /* 57-61: pmc8 event select */ 131 uint32_t speculative_event : 2; /* 62-63: SPeCulative count event SELector */ 132 } ppc64_mmcr1_bits_t; 133 134 typedef union { 135 uint64_t value; 136 ppc64_mmcr1_bits_t field; 137 } ppc64_mmcr1_reg_t; 138 139 typedef struct { 140 uint32_t /* reserved */ : 32; /* 0-31: reserved */ 141 uint32_t siar_sdar_same_instruction : 1; /* 32: SIAR and SDAR are from same instruction */ 142 uint32_t disable_counters_pmc1_pmc4 : 1; /* 33: disable counters PMC1-PMC4 */ 143 uint32_t disable_counters_pmc5_pmc8 : 1; /* 34: disable counters PMC5-PMC8 */ 144 uint32_t problem_state_siar : 1; /* 35: MSR[PR] bit when SIAR set */ 145 uint32_t hypervisor_state_siar : 1; /* 36: MSR[HV] bit when SIAR set */ 146 uint32_t /* reserved */ : 3; /* 37-39: reserved */ 147 uint32_t threshold_start_event : 3; /* 40-42: threshold start event */ 148 uint32_t threshold_end_event : 3; /* 43-45: threshold end event */ 149 uint32_t /* reserved */ : 3; /* 46-48: reserved */ 150 uint32_t imr_select : 1; /* 49: imr select */ 151 uint32_t imr_mark : 2; /* 50-51: imr mark */ 152 uint32_t imr_mask : 4; /* 52-55: imr mask */ 153 uint32_t imr_match : 4; /* 56-59: imr match */ 154 uint32_t disable_counters_tags_inactive : 1; /* 60: disable counters in tags inactive mode */ 155 uint32_t disable_counters_tags_active : 1; /* 61: disable counters in tags active mode */ 156 uint32_t disable_counters_wait_state : 1; /* 62: freeze counters in wait state (CNTL[31]=0) */ 157 uint32_t sample_enable : 1; /* 63: sampling enabled */ 158 } ppc64_mmcra_bits_t; 159 160 typedef union { 161 uint64_t value; 162 ppc64_mmcra_bits_t field; 163 } ppc64_mmcra_reg_t; 164 165 /* PPC_PERFMON_FUNC_* values are taken apart to fill in the appropriate configuration bitfields: */ 166 typedef struct { 167 uint32_t /* reserved */ : 22; 168 uint32_t SPECSEL : 2; 169 uint32_t TD_CP_DBGxSEL : 2; 170 uint32_t TTM3SEL : 2; 171 uint32_t TTM1SEL : 2; 172 uint32_t TTM0SEL : 2; 173 } ppc_func_bits_t; 174 175 typedef union { 176 uint32_t value; 177 ppc_func_bits_t field; 178 } ppc_func_unit_t; 179 180 #endif /* _HW_PERFMON_MMCR_H_ */
Cache object: 3c4a63e06e497a6d4e3269081c44f202
[ source navigation ] [ diff markup ] [ identifier search ] [ freetext search ] [ file search ] [ list types ] [ track identifier ]