Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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FreeBSD/Linux Kernel Cross Reference
sys/pc/io.h
Version:
- FREEBSD - FREEBSD-13-STABLE - FREEBSD-13-0 - FREEBSD-12-STABLE - FREEBSD-12-0 - FREEBSD-11-STABLE - FREEBSD-11-0 - FREEBSD-10-STABLE - FREEBSD-10-0 - FREEBSD-9-STABLE - FREEBSD-9-0 - FREEBSD-8-STABLE - FREEBSD-8-0 - FREEBSD-7-STABLE - FREEBSD-7-0 - FREEBSD-6-STABLE - FREEBSD-6-0 - FREEBSD-5-STABLE - FREEBSD-5-0 - FREEBSD-4-STABLE - FREEBSD-3-STABLE - FREEBSD22 - l41 - OPENBSD - linux-2.6 - MK84 - PLAN9 - xnu-8792
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1 #define X86STEPPING(x) ((x) & 0x0F) 2 /* incorporate extended-model bits */ 3 #define X86MODEL(x) ((((x)>>4) & 0x0F) | (((x)>>16) & 0x0F)<<4) 4 #define X86FAMILY(x) (((x)>>8) & 0x0F) 5 6 enum { 7 VectorNMI = 2, /* non-maskable interrupt */ 8 VectorBPT = 3, /* breakpoint */ 9 VectorUD = 6, /* invalid opcode exception */ 10 VectorCNA = 7, /* coprocessor not available */ 11 Vector2F = 8, /* double fault */ 12 VectorCSO = 9, /* coprocessor segment overrun */ 13 VectorPF = 14, /* page fault */ 14 Vector15 = 15, /* reserved */ 15 VectorCERR = 16, /* coprocessor error */ 16 17 VectorPIC = 32, /* external i8259 interrupts */ 18 IrqCLOCK = 0, 19 IrqKBD = 1, 20 IrqUART1 = 3, 21 IrqUART0 = 4, 22 IrqPCMCIA = 5, 23 IrqFLOPPY = 6, 24 IrqLPT = 7, 25 IrqIRQ7 = 7, 26 IrqAUX = 12, /* PS/2 port */ 27 IrqIRQ13 = 13, /* coprocessor on 386 */ 28 IrqATA0 = 14, 29 IrqATA1 = 15, 30 MaxIrqPIC = 15, 31 32 VectorLAPIC = VectorPIC+16, /* local APIC interrupts */ 33 IrqLINT0 = 16, /* LINT[01] must be offsets 0 and 1 */ 34 IrqLINT1 = 17, 35 IrqTIMER = 18, 36 IrqERROR = 19, 37 IrqPCINT = 20, 38 IrqSPURIOUS = 31, /* must have bits [3-0] == 0x0F */ 39 MaxIrqLAPIC = 31, 40 41 VectorSYSCALL = 64, 42 43 VectorAPIC = 65, /* external APIC interrupts */ 44 MaxVectorAPIC = 255, 45 }; 46 47 typedef struct Vctl { 48 Vctl* next; /* handlers on this vector */ 49 50 char name[KNAMELEN]; /* of driver */ 51 int isintr; /* interrupt or fault/trap */ 52 int irq; 53 int tbdf; 54 int (*isr)(int); /* get isr bit for this irq */ 55 int (*eoi)(int); /* eoi */ 56 57 void (*f)(Ureg*, void*); /* handler to call */ 58 void* a; /* argument to call it with */ 59 } Vctl; 60 61 enum { 62 BusCBUS = 0, /* Corollary CBUS */ 63 BusCBUSII, /* Corollary CBUS II */ 64 BusEISA, /* Extended ISA */ 65 BusFUTURE, /* IEEE Futurebus */ 66 BusINTERN, /* Internal bus */ 67 BusISA, /* Industry Standard Architecture */ 68 BusMBI, /* Multibus I */ 69 BusMBII, /* Multibus II */ 70 BusMCA, /* Micro Channel Architecture */ 71 BusMPI, /* MPI */ 72 BusMPSA, /* MPSA */ 73 BusNUBUS, /* Apple Macintosh NuBus */ 74 BusPCI, /* Peripheral Component Interconnect */ 75 BusPCMCIA, /* PC Memory Card International Association */ 76 BusTC, /* DEC TurboChannel */ 77 BusVL, /* VESA Local bus */ 78 BusVME, /* VMEbus */ 79 BusXPRESS, /* Express System Bus */ 80 }; 81 82 #define MKBUS(t,b,d,f) (((t)<<24)|(((b)&0xFF)<<16)|(((d)&0x1F)<<11)|(((f)&0x07)<<8)) 83 #define BUSFNO(tbdf) (((tbdf)>>8)&0x07) 84 #define BUSDNO(tbdf) (((tbdf)>>11)&0x1F) 85 #define BUSBNO(tbdf) (((tbdf)>>16)&0xFF) 86 #define BUSTYPE(tbdf) ((tbdf)>>24) 87 #define BUSBDF(tbdf) ((tbdf)&0x00FFFF00) 88 #define BUSUNKNOWN (-1) 89 90 enum { 91 MaxEISA = 16, 92 CfgEISA = 0xC80, 93 }; 94 95 /* 96 * PCI support code. 97 */ 98 enum { /* type 0 & type 1 pre-defined header */ 99 PciVID = 0x00, /* vendor ID */ 100 PciDID = 0x02, /* device ID */ 101 PciPCR = 0x04, /* command */ 102 PciPSR = 0x06, /* status */ 103 PciRID = 0x08, /* revision ID */ 104 PciCCRp = 0x09, /* programming interface class code */ 105 PciCCRu = 0x0A, /* sub-class code */ 106 PciCCRb = 0x0B, /* base class code */ 107 PciCLS = 0x0C, /* cache line size */ 108 PciLTR = 0x0D, /* latency timer */ 109 PciHDT = 0x0E, /* header type */ 110 PciBST = 0x0F, /* BIST */ 111 112 PciBAR0 = 0x10, /* base address */ 113 PciBAR1 = 0x14, 114 115 PciINTL = 0x3C, /* interrupt line */ 116 PciINTP = 0x3D, /* interrupt pin */ 117 }; 118 119 /* ccrb (base class code) values; controller types */ 120 enum { 121 Pcibcpci1 = 0, /* pci 1.0; no class codes defined */ 122 Pcibcstore = 1, /* mass storage */ 123 Pcibcnet = 2, /* network */ 124 Pcibcdisp = 3, /* display */ 125 Pcibcmmedia = 4, /* multimedia */ 126 Pcibcmem = 5, /* memory */ 127 Pcibcbridge = 6, /* bridge */ 128 Pcibccomm = 7, /* simple comms (e.g., serial) */ 129 Pcibcbasesys = 8, /* base system */ 130 Pcibcinput = 9, /* input */ 131 Pcibcdock = 0xa, /* docking stations */ 132 Pcibcproc = 0xb, /* processors */ 133 Pcibcserial = 0xc, /* serial bus (e.g., USB) */ 134 Pcibcwireless = 0xd, /* wireless */ 135 Pcibcintell = 0xe, /* intelligent i/o */ 136 Pcibcsatcom = 0xf, /* satellite comms */ 137 Pcibccrypto = 0x10, /* encryption/decryption */ 138 Pcibcdacq = 0x11, /* data acquisition & signal proc. */ 139 }; 140 141 /* ccru (sub-class code) values; common cases only */ 142 enum { 143 /* mass storage */ 144 Pciscscsi = 0, /* SCSI */ 145 Pciscide = 1, /* IDE (ATA) */ 146 147 /* network */ 148 Pciscether = 0, /* Ethernet */ 149 150 /* display */ 151 Pciscvga = 0, /* VGA */ 152 Pciscxga = 1, /* XGA */ 153 Pcisc3d = 2, /* 3D */ 154 155 /* bridges */ 156 Pcischostpci = 0, /* host/pci */ 157 Pciscpcicpci = 1, /* pci/pci */ 158 159 /* simple comms */ 160 Pciscserial = 0, /* 16450, etc. */ 161 Pciscmultiser = 1, /* multiport serial */ 162 163 /* serial bus */ 164 Pciscusb = 3, /* USB */ 165 }; 166 167 enum { /* type 0 pre-defined header */ 168 PciCIS = 0x28, /* cardbus CIS pointer */ 169 PciSVID = 0x2C, /* subsystem vendor ID */ 170 PciSID = 0x2E, /* cardbus CIS pointer */ 171 PciEBAR0 = 0x30, /* expansion ROM base address */ 172 PciMGNT = 0x3E, /* burst period length */ 173 PciMLT = 0x3F, /* maximum latency between bursts */ 174 }; 175 176 enum { /* type 1 pre-defined header */ 177 PciPBN = 0x18, /* primary bus number */ 178 PciSBN = 0x19, /* secondary bus number */ 179 PciUBN = 0x1A, /* subordinate bus number */ 180 PciSLTR = 0x1B, /* secondary latency timer */ 181 PciIBR = 0x1C, /* I/O base */ 182 PciILR = 0x1D, /* I/O limit */ 183 PciSPSR = 0x1E, /* secondary status */ 184 PciMBR = 0x20, /* memory base */ 185 PciMLR = 0x22, /* memory limit */ 186 PciPMBR = 0x24, /* prefetchable memory base */ 187 PciPMLR = 0x26, /* prefetchable memory limit */ 188 PciPUBR = 0x28, /* prefetchable base upper 32 bits */ 189 PciPULR = 0x2C, /* prefetchable limit upper 32 bits */ 190 PciIUBR = 0x30, /* I/O base upper 16 bits */ 191 PciIULR = 0x32, /* I/O limit upper 16 bits */ 192 PciEBAR1 = 0x28, /* expansion ROM base address */ 193 PciBCR = 0x3E, /* bridge control register */ 194 }; 195 196 enum { /* type 2 pre-defined header */ 197 PciCBExCA = 0x10, 198 PciCBSPSR = 0x16, 199 PciCBPBN = 0x18, /* primary bus number */ 200 PciCBSBN = 0x19, /* secondary bus number */ 201 PciCBUBN = 0x1A, /* subordinate bus number */ 202 PciCBSLTR = 0x1B, /* secondary latency timer */ 203 PciCBMBR0 = 0x1C, 204 PciCBMLR0 = 0x20, 205 PciCBMBR1 = 0x24, 206 PciCBMLR1 = 0x28, 207 PciCBIBR0 = 0x2C, /* I/O base */ 208 PciCBILR0 = 0x30, /* I/O limit */ 209 PciCBIBR1 = 0x34, /* I/O base */ 210 PciCBILR1 = 0x38, /* I/O limit */ 211 PciCBSVID = 0x40, /* subsystem vendor ID */ 212 PciCBSID = 0x42, /* subsystem ID */ 213 PciCBLMBAR = 0x44, /* legacy mode base address */ 214 }; 215 216 typedef struct Pcisiz Pcisiz; 217 struct Pcisiz 218 { 219 Pcidev* dev; 220 int siz; 221 int bar; 222 }; 223 224 typedef struct Pcidev Pcidev; 225 struct Pcidev 226 { 227 int tbdf; /* type+bus+device+function */ 228 ushort vid; /* vendor ID */ 229 ushort did; /* device ID */ 230 231 ushort pcr; 232 233 uchar rid; 234 uchar ccrp; 235 uchar ccru; 236 uchar ccrb; 237 uchar cls; 238 uchar ltr; 239 240 struct { 241 ulong bar; /* base address */ 242 int size; 243 } mem[6]; 244 245 struct { 246 ulong bar; 247 int size; 248 } rom; 249 uchar intl; /* interrupt line */ 250 251 Pcidev* list; 252 Pcidev* link; /* next device on this bno */ 253 254 Pcidev* bridge; /* down a bus */ 255 struct { 256 ulong bar; 257 int size; 258 } ioa, mema; 259 260 int pmrb; /* power management register block */ 261 }; 262 263 #define PCIWINDOW 0 264 #define PCIWADDR(va) (PADDR(va)+PCIWINDOW) 265 #define ISAWINDOW 0 266 #define ISAWADDR(va) (PADDR(va)+ISAWINDOW) 267 268 /* SMBus transactions */ 269 enum 270 { 271 SMBquick, /* sends address only */ 272 273 /* write */ 274 SMBsend, /* sends address and cmd */ 275 SMBbytewrite, /* sends address and cmd and 1 byte */ 276 SMBwordwrite, /* sends address and cmd and 2 bytes */ 277 278 /* read */ 279 SMBrecv, /* sends address, recvs 1 byte */ 280 SMBbyteread, /* sends address and cmd, recv's byte */ 281 SMBwordread, /* sends address and cmd, recv's 2 bytes */ 282 }; 283 284 typedef struct SMBus SMBus; 285 struct SMBus { 286 QLock; /* mutex */ 287 Rendez r; /* rendezvous point for completion interrupts */ 288 void *arg; /* implementation dependent */ 289 ulong base; /* port or memory base of smbus */ 290 int busy; 291 void (*transact)(SMBus*, int, int, int, uchar*); 292 }; 293 294 /* 295 * PCMCIA support code. 296 */ 297 298 typedef struct PCMslot PCMslot; 299 typedef struct PCMconftab PCMconftab; 300 301 /* 302 * Map between ISA memory space and PCMCIA card memory space. 303 */ 304 struct PCMmap { 305 ulong ca; /* card address */ 306 ulong cea; /* card end address */ 307 ulong isa; /* ISA address */ 308 int len; /* length of the ISA area */ 309 int attr; /* attribute memory */ 310 int ref; 311 }; 312 313 /* configuration table entry */ 314 struct PCMconftab 315 { 316 int index; 317 ushort irqs; /* legal irqs */ 318 uchar irqtype; 319 uchar bit16; /* true for 16 bit access */ 320 struct { 321 ulong start; 322 ulong len; 323 } io[16]; 324 int nio; 325 uchar vpp1; 326 uchar vpp2; 327 uchar memwait; 328 ulong maxwait; 329 ulong readywait; 330 ulong otherwait; 331 }; 332 333 /* a card slot */ 334 struct PCMslot 335 { 336 Lock; 337 int ref; 338 339 void *cp; /* controller for this slot */ 340 long memlen; /* memory length */ 341 uchar base; /* index register base */ 342 uchar slotno; /* slot number */ 343 344 /* status */ 345 uchar special; /* in use for a special device */ 346 uchar already; /* already inited */ 347 uchar occupied; 348 uchar battery; 349 uchar wrprot; 350 uchar powered; 351 uchar configed; 352 uchar enabled; 353 uchar busy; 354 355 /* cis info */ 356 ulong msec; /* time of last slotinfo call */ 357 char verstr[512]; /* version string */ 358 int ncfg; /* number of configurations */ 359 struct { 360 ushort cpresent; /* config registers present */ 361 ulong caddr; /* relative address of config registers */ 362 } cfg[8]; 363 int nctab; /* number of config table entries */ 364 PCMconftab ctab[8]; 365 PCMconftab *def; /* default conftab */ 366 367 /* memory maps */ 368 Lock mlock; /* lock down the maps */ 369 int time; 370 PCMmap mmap[4]; /* maps, last is always for the kernel */ 371 };
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