The Design and Implementation of the FreeBSD Operating System, Second Edition
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FreeBSD/Linux Kernel Cross Reference
sys/pc/sd53c8xx.c

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    1 /*
    2  * NCR/Symbios/LSI Logic 53c8xx driver for Plan 9
    3  * Nigel Roles (nigel@9fs.org)
    4  *
    5  * 27/5/02      Fixed problems with transfers >= 256 * 512
    6  *
    7  * 13/3/01      Fixed microcode to support targets > 7
    8  *
    9  * 01/12/00     Removed previous comments. Fixed a small problem in
   10  *                      mismatch recovery for targets with synchronous offsets of >=16
   11  *                      connected to >=875s. Thanks, Jean.
   12  *
   13  * Known problems
   14  *
   15  * Read/write mismatch recovery may fail on 53c1010s. Really need to get a manual.
   16  */
   17 
   18 #define MAXTARGET       16              /* can be 8 or 16 */
   19 
   20 #include "u.h"
   21 #include "../port/lib.h"
   22 #include "mem.h"
   23 #include "dat.h"
   24 #include "fns.h"
   25 #include "io.h"
   26 
   27 #include "../port/sd.h"
   28 extern SDifc sd53c8xxifc;
   29 
   30 /**********************************/
   31 /* Portable configuration macros  */
   32 /**********************************/
   33 
   34 //#define BOOTDEBUG
   35 //#define ASYNC_ONLY
   36 //#define       INTERNAL_SCLK
   37 //#define ALWAYS_DO_WDTR
   38 #define WMR_DEBUG
   39 
   40 /**********************************/
   41 /* CPU specific macros            */
   42 /**********************************/
   43 
   44 #define PRINTPREFIX "sd53c8xx: "
   45 
   46 #ifdef BOOTDEBUG
   47 
   48 #define KPRINT oprint
   49 #define IPRINT intrprint
   50 #define DEBUG(n) 1
   51 #define IFLUSH() iflush()
   52 
   53 #else
   54 
   55 static int idebug = 1;
   56 #define KPRINT  if(0) iprint
   57 #define IPRINT  if(idebug) iprint
   58 #define DEBUG(n)        (0)
   59 #define IFLUSH()
   60 
   61 #endif /* BOOTDEBUG */
   62 
   63 /*******************************/
   64 /* General                     */
   65 /*******************************/
   66 
   67 #ifndef DMASEG
   68 #define DMASEG(x) PCIWADDR(x)
   69 #define legetl(x) (*(ulong*)(x))
   70 #define lesetl(x,v) (*(ulong*)(x) = (v))
   71 #define swabl(a,b,c)
   72 #else
   73 #endif /*DMASEG */
   74 #define DMASEG_TO_KADDR(x) KADDR((x)-PCIWINDOW)
   75 #define KPTR(x) ((x) == 0 ? 0 : DMASEG_TO_KADDR(x))
   76 
   77 #define MEGA 1000000L
   78 #ifdef INTERNAL_SCLK
   79 #define SCLK (33 * MEGA)
   80 #else
   81 #define SCLK (40 * MEGA)
   82 #endif /* INTERNAL_SCLK */
   83 #define ULTRA_NOCLOCKDOUBLE_SCLK (80 * MEGA)
   84 
   85 #define MAXSYNCSCSIRATE (5 * MEGA)
   86 #define MAXFASTSYNCSCSIRATE (10 * MEGA)
   87 #define MAXULTRASYNCSCSIRATE (20 * MEGA)
   88 #define MAXULTRA2SYNCSCSIRATE (40 * MEGA)
   89 #define MAXASYNCCORERATE (25 * MEGA)
   90 #define MAXSYNCCORERATE (25 * MEGA)
   91 #define MAXFASTSYNCCORERATE (50 * MEGA)
   92 #define MAXULTRASYNCCORERATE (80 * MEGA)
   93 #define MAXULTRA2SYNCCORERATE (160 * MEGA)
   94 
   95 
   96 #define X_MSG   1
   97 #define X_MSG_SDTR 1
   98 #define X_MSG_WDTR 3
   99 
  100 struct na_patch {
  101         unsigned lwoff;
  102         unsigned char type;
  103 };
  104 
  105 typedef struct Ncr {
  106         uchar scntl0;   /* 00 */
  107         uchar scntl1;
  108         uchar scntl2;
  109         uchar scntl3;
  110 
  111         uchar scid;     /* 04 */
  112         uchar sxfer;
  113         uchar sdid;
  114         uchar gpreg;
  115 
  116         uchar sfbr;     /* 08 */
  117         uchar socl;
  118         uchar ssid;
  119         uchar sbcl;
  120 
  121         uchar dstat;    /* 0c */
  122         uchar sstat0;
  123         uchar sstat1;
  124         uchar sstat2;
  125 
  126         uchar dsa[4];   /* 10 */
  127 
  128         uchar istat;    /* 14 */
  129         uchar istatpad[3];
  130 
  131         uchar ctest0;   /* 18 */
  132         uchar ctest1;
  133         uchar ctest2;
  134         uchar ctest3;
  135 
  136         uchar temp[4];  /* 1c */
  137 
  138         uchar dfifo;    /* 20 */
  139         uchar ctest4;
  140         uchar ctest5;
  141         uchar ctest6;
  142 
  143         uchar dbc[3];   /* 24 */
  144         uchar dcmd;     /* 27 */
  145 
  146         uchar dnad[4];  /* 28 */
  147         uchar dsp[4];   /* 2c */
  148         uchar dsps[4];  /* 30 */
  149 
  150         uchar scratcha[4];      /* 34 */
  151 
  152         uchar dmode;    /* 38 */
  153         uchar dien;
  154         uchar dwt;
  155         uchar dcntl;
  156 
  157         uchar adder[4]; /* 3c */
  158 
  159         uchar sien0;    /* 40 */
  160         uchar sien1;
  161         uchar sist0;
  162         uchar sist1;
  163 
  164         uchar slpar;    /* 44 */
  165         uchar slparpad0;
  166         uchar macntl;
  167         uchar gpcntl;
  168 
  169         uchar stime0;   /* 48 */
  170         uchar stime1;
  171         uchar respid;
  172         uchar respidpad0;
  173 
  174         uchar stest0;   /* 4c */
  175         uchar stest1;
  176         uchar stest2;
  177         uchar stest3;
  178 
  179         uchar sidl;     /* 50 */
  180         uchar sidlpad[3];
  181 
  182         uchar sodl;     /* 54 */
  183         uchar sodlpad[3];
  184 
  185         uchar sbdl;     /* 58 */
  186         uchar sbdlpad[3];
  187 
  188         uchar scratchb[4];      /* 5c */
  189 } Ncr;
  190 
  191 typedef struct Movedata {
  192         uchar dbc[4];
  193         uchar pa[4];
  194 } Movedata;
  195 
  196 typedef enum NegoState {
  197         NeitherDone, WideInit, WideResponse, WideDone,
  198         SyncInit, SyncResponse, BothDone
  199 } NegoState;
  200 
  201 typedef enum State {
  202         Allocated, Queued, Active, Done
  203 } State;
  204 
  205 typedef struct Dsa Dsa;
  206 struct Dsa {
  207         uchar stateb;
  208         uchar result;
  209         uchar dmablks;
  210         uchar flag;     /* setbyte(state,3,...) */
  211 
  212         union {
  213                 ulong dmancr;           /* For block transfer: NCR order (little-endian) */
  214                 uchar dmaaddr[4];
  215         };
  216 
  217         uchar target;                   /* Target */
  218         uchar pad0[3];
  219 
  220         uchar lun;                      /* Logical Unit Number */
  221         uchar pad1[3];
  222 
  223         uchar scntl3;
  224         uchar sxfer;
  225         uchar pad2[2];
  226 
  227         uchar next[4];                  /* chaining for SCRIPT (NCR byte order) */
  228         Dsa     *freechain;             /* chaining for freelist */
  229         Rendez;
  230         uchar scsi_id_buf[4];
  231         Movedata msg_out_buf;
  232         Movedata cmd_buf;
  233         Movedata data_buf;
  234         Movedata status_buf;
  235         uchar msg_out[10];              /* enough to include SDTR */
  236         uchar status;
  237         int p9status;
  238         uchar parityerror;
  239 };
  240 
  241 typedef enum Feature {
  242         BigFifo = 1,                    /* 536 byte fifo */
  243         BurstOpCodeFetch = 2,           /* burst fetch opcodes */
  244         Prefetch = 4,                   /* prefetch 8 longwords */
  245         LocalRAM = 8,                   /* 4K longwords of local RAM */
  246         Differential = 16,              /* Differential support */
  247         Wide = 32,                      /* Wide capable */
  248         Ultra = 64,                     /* Ultra capable */
  249         ClockDouble = 128,              /* Has clock doubler */
  250         ClockQuad = 256,                /* Has clock quadrupler (same as Ultra2) */
  251         Ultra2 = 256,
  252 } Feature;
  253 
  254 typedef enum Burst {
  255         Burst2 = 0,
  256         Burst4 = 1,
  257         Burst8 = 2,
  258         Burst16 = 3,
  259         Burst32 = 4,
  260         Burst64 = 5,
  261         Burst128 = 6
  262 } Burst;
  263 
  264 typedef struct Variant {
  265         ushort did;
  266         uchar maxrid;                   /* maximum allowed revision ID */
  267         char *name;
  268         Burst burst;                    /* codings for max burst */
  269         uchar maxsyncoff;               /* max synchronous offset */
  270         uchar registers;                /* number of 32 bit registers */
  271         unsigned feature;
  272 } Variant;
  273 
  274 static unsigned char cf2[] = { 6, 2, 3, 4, 6, 8, 12, 16 };
  275 #define NULTRA2SCF (sizeof(cf2)/sizeof(cf2[0]))
  276 #define NULTRASCF (NULTRA2SCF - 2)
  277 #define NSCF (NULTRASCF - 1)
  278 
  279 typedef struct Controller {
  280         Lock;
  281         struct {
  282                 uchar scntl3;
  283                 uchar stest2;
  284         } bios;
  285         uchar synctab[NULTRA2SCF - 1][8];/* table of legal tpfs */
  286         NegoState s[MAXTARGET];
  287         uchar scntl3[MAXTARGET];
  288         uchar sxfer[MAXTARGET];
  289         uchar cap[MAXTARGET];           /* capabilities byte from Identify */
  290         ushort capvalid;                /* bit per target for validity of cap[] */
  291         ushort wide;                    /* bit per target set if wide negotiated */
  292         ulong sclk;                     /* clock speed of controller */
  293         uchar clockmult;                /* set by synctabinit */
  294         uchar ccf;                      /* CCF bits */
  295         uchar tpf;                      /* best tpf value for this controller */
  296         uchar feature;                  /* requested features */
  297         int running;                    /* is the script processor running? */
  298         int ssm;                        /* single step mode */
  299         Ncr *n;                         /* pointer to registers */
  300         Variant *v;                     /* pointer to variant type */
  301         ulong *script;                  /* where the real script is */
  302         ulong scriptpa;                 /* where the real script is */
  303         Pcidev* pcidev;
  304         SDev*   sdev;
  305 
  306         struct {
  307                 Lock;
  308                 uchar head[4];          /* head of free list (NCR byte order) */
  309                 Dsa     *freechain;
  310         } dsalist;
  311 
  312         QLock q[MAXTARGET];             /* queues for each target */
  313 } Controller;
  314 
  315 #define SYNCOFFMASK(c)          (((c)->v->maxsyncoff * 2) - 1)
  316 #define SSIDMASK(c)             (((c)->v->feature & Wide) ? 15 : 7)
  317 
  318 /* ISTAT */
  319 enum { Abrt = 0x80, Srst = 0x40, Sigp = 0x20, Sem = 0x10, Con = 0x08, Intf = 0x04, Sip = 0x02, Dip = 0x01 };
  320 
  321 /* DSTAT */
  322 enum { Dfe = 0x80, Mdpe = 0x40, Bf = 0x20, Abrted = 0x10, Ssi = 0x08, Sir = 0x04, Iid = 0x01 };
  323 
  324 /* SSTAT */
  325 enum { DataOut, DataIn, Cmd, Status, ReservedOut, ReservedIn, MessageOut, MessageIn };
  326 
  327 static void setmovedata(Movedata*, ulong, ulong);
  328 static void advancedata(Movedata*, long);
  329 static int bios_set_differential(Controller *c);
  330 
  331 static char *phase[] = {
  332         "data out", "data in", "command", "status",
  333         "reserved out", "reserved in", "message out", "message in"
  334 };
  335 
  336 #ifdef BOOTDEBUG
  337 #define DEBUGSIZE 10240
  338 char debugbuf[DEBUGSIZE];
  339 char *debuglast;
  340 
  341 static void
  342 intrprint(char *format, ...)
  343 {
  344         if (debuglast == 0)
  345                 debuglast = debugbuf;
  346         debuglast = vseprint(debuglast, debugbuf + (DEBUGSIZE - 1), format, (&format + 1));
  347 }
  348 
  349 static void
  350 iflush()
  351 {
  352         int s;
  353         char *endp;
  354         s = splhi();
  355         if (debuglast == 0)
  356                 debuglast = debugbuf;
  357         if (debuglast == debugbuf) {
  358                 splx(s);
  359                 return;
  360         }
  361         endp = debuglast;
  362         splx(s);
  363         screenputs(debugbuf, endp - debugbuf);
  364         s = splhi();
  365         memmove(debugbuf, endp, debuglast - endp);
  366         debuglast -= endp - debugbuf;
  367         splx(s);
  368 }
  369 
  370 static void
  371 oprint(char *format, ...)
  372 {
  373         int s;
  374 
  375         iflush();
  376         s = splhi();
  377         if (debuglast == 0)
  378                 debuglast = debugbuf;
  379         debuglast = vseprint(debuglast, debugbuf + (DEBUGSIZE - 1), format, (&format + 1));
  380         splx(s);
  381         iflush();       
  382 }
  383 #endif
  384 
  385 #include "sd53c8xx.i"
  386 
  387 /*
  388  * We used to use a linked list of Dsas with nil as the terminator,
  389  * but occasionally the 896 card seems not to notice that the 0
  390  * is really a 0, and then it tries to reference the Dsa at address 0.
  391  * To address this, we use a sentinel dsa that links back to itself
  392  * and has state A_STATE_END.  If the card takes an iteration or
  393  * two to notice that the state says A_STATE_END, that's no big 
  394  * deal.  Clearly this isn't the right approach, but I'm just
  395  * stumped.  Even with this, we occasionally get prints about
  396  * "WSR set", usually with about the same frequency that the
  397  * card used to walk past 0. 
  398  */
  399 static Dsa *dsaend;
  400 
  401 static Dsa*
  402 dsaallocnew(Controller *c)
  403 {
  404         Dsa *d;
  405         
  406         /* c->dsalist must be ilocked */
  407         d = xalloc(sizeof *d);
  408         if (d == nil)
  409                 panic("sd53c8xx dsaallocnew: no memory");
  410         lesetl(d->next, legetl(c->dsalist.head));
  411         lesetl(&d->stateb, A_STATE_FREE);
  412         coherence();
  413         lesetl(c->dsalist.head, DMASEG(d));
  414         coherence();
  415         return d;
  416 }
  417 
  418 static Dsa *
  419 dsaalloc(Controller *c, int target, int lun)
  420 {
  421         Dsa *d;
  422 
  423         ilock(&c->dsalist);
  424         if ((d = c->dsalist.freechain) != 0) {
  425                 if (DEBUG(1))
  426                         IPRINT(PRINTPREFIX "%d/%d: reused dsa %lux\n", target, lun, (ulong)d);
  427         } else {        
  428                 d = dsaallocnew(c);
  429                 if (DEBUG(1))
  430                         IPRINT(PRINTPREFIX "%d/%d: allocated dsa %lux\n", target, lun, (ulong)d);
  431         }
  432         c->dsalist.freechain = d->freechain;
  433         lesetl(&d->stateb, A_STATE_ALLOCATED);
  434         iunlock(&c->dsalist);
  435         d->target = target;
  436         d->lun = lun;
  437         return d;
  438 }
  439 
  440 static void
  441 dsafree(Controller *c, Dsa *d)
  442 {
  443         ilock(&c->dsalist);
  444         d->freechain = c->dsalist.freechain;
  445         c->dsalist.freechain = d;
  446         lesetl(&d->stateb, A_STATE_FREE);
  447         iunlock(&c->dsalist);
  448 }
  449 
  450 static void
  451 dsadump(Controller *c)
  452 {
  453         Dsa *d;
  454         u32int *a;
  455         
  456         iprint("dsa controller list: c=%p head=%.8lux\n", c, legetl(c->dsalist.head));
  457         for(d=KPTR(legetl(c->dsalist.head)); d != dsaend; d=KPTR(legetl(d->next))){
  458                 if(d == (void*)-1){
  459                         iprint("\t dsa %p\n", d);
  460                         break;
  461                 }
  462                 a = (u32int*)d;
  463                 iprint("\tdsa %p %.8ux %.8ux %.8ux %.8ux %.8ux %.8ux\n", a, a[0], a[1], a[2], a[3], a[4], a[5]);
  464         }
  465 
  466 /*
  467         a = KPTR(c->scriptpa+E_dsa_addr);
  468         iprint("dsa_addr: %.8ux %.8ux %.8ux %.8ux %.8ux\n",
  469                 a[0], a[1], a[2], a[3], a[4]);
  470         a = KPTR(c->scriptpa+E_issue_addr);
  471         iprint("issue_addr: %.8ux %.8ux %.8ux %.8ux %.8ux\n",
  472                 a[0], a[1], a[2], a[3], a[4]);
  473 
  474         a = KPTR(c->scriptpa+E_issue_test_begin);
  475         e = KPTR(c->scriptpa+E_issue_test_end);
  476         iprint("issue_test code (at offset %.8ux):\n", E_issue_test_begin);
  477         
  478         i = 0;
  479         for(; a<e; a++){
  480                 iprint(" %.8ux", *a);
  481                 if(++i%8 == 0)
  482                         iprint("\n");
  483         }
  484         if(i%8)
  485                 iprint("\n");
  486 */
  487 }
  488 
  489 static Dsa *
  490 dsafind(Controller *c, uchar target, uchar lun, uchar state)
  491 {
  492         Dsa *d;
  493         for (d = KPTR(legetl(c->dsalist.head)); d != dsaend; d = KPTR(legetl(d->next))) {
  494                 if (d->target != 0xff && d->target != target)
  495                         continue;
  496                 if (lun != 0xff && d->lun != lun)
  497                         continue;
  498                 if (state != 0xff && d->stateb != state)
  499                         continue;
  500                 break;
  501         }
  502         return d;
  503 }
  504 
  505 static void
  506 dumpncrregs(Controller *c, int intr)
  507 {
  508         int i;
  509         Ncr *n = c->n;
  510         int depth = c->v->registers / 4;
  511 
  512         if (intr) {
  513                 IPRINT("sa = %.8lux\n", c->scriptpa);
  514         }
  515         else {
  516                 KPRINT("sa = %.8lux\n", c->scriptpa);
  517         }
  518         for (i = 0; i < depth; i++) {
  519                 int j;
  520                 for (j = 0; j < 4; j++) {
  521                         int k = j * depth + i;
  522                         uchar *p;
  523 
  524                         /* display little-endian to make 32-bit values readable */
  525                         p = (uchar*)n+k*4;
  526                         if (intr) {
  527                                 IPRINT(" %.2x%.2x%.2x%.2x %.2x %.2x", p[3], p[2], p[1], p[0], k * 4, (k * 4) + 0x80);
  528                         }
  529                         else {
  530                                 KPRINT(" %.2x%.2x%.2x%.2x %.2x %.2x", p[3], p[2], p[1], p[0], k * 4, (k * 4) + 0x80);
  531                         }
  532                         USED(p);
  533                 }
  534                 if (intr) {
  535                         IPRINT("\n");
  536                 }
  537                 else {
  538                         KPRINT("\n");
  539                 }
  540         }
  541 }       
  542 
  543 static int
  544 chooserate(Controller *c, int tpf, int *scfp, int *xferpp)
  545 {
  546         /* find lowest entry >= tpf */
  547         int besttpf = 1000;
  548         int bestscfi = 0;
  549         int bestxferp = 0;
  550         int scf, xferp;
  551         int maxscf;
  552 
  553         if (c->v->feature & Ultra2)
  554                 maxscf = NULTRA2SCF;
  555         else if (c->v->feature & Ultra)
  556                 maxscf = NULTRASCF;
  557         else
  558                 maxscf = NSCF;
  559 
  560         /*
  561          * search large clock factors first since this should
  562          * result in more reliable transfers
  563          */
  564         for (scf = maxscf; scf >= 1; scf--) {
  565                 for (xferp = 0; xferp < 8; xferp++) {
  566                         unsigned char v = c->synctab[scf - 1][xferp];
  567                         if (v == 0)
  568                                 continue;
  569                         if (v >= tpf && v < besttpf) {
  570                                 besttpf = v;
  571                                 bestscfi = scf;
  572                                 bestxferp = xferp;
  573                         }
  574                 }
  575         }
  576         if (besttpf == 1000)
  577                 return 0;
  578         if (scfp)
  579                 *scfp = bestscfi;
  580         if (xferpp)
  581                 *xferpp = bestxferp;
  582         return besttpf;
  583 }
  584 
  585 static void
  586 synctabinit(Controller *c)
  587 {
  588         int scf;
  589         unsigned long scsilimit;
  590         int xferp;
  591         unsigned long cr, sr;
  592         int tpf;
  593         int fast;
  594         int maxscf;
  595 
  596         if (c->v->feature & Ultra2)
  597                 maxscf = NULTRA2SCF;
  598         else if (c->v->feature & Ultra)
  599                 maxscf = NULTRASCF;
  600         else
  601                 maxscf = NSCF;
  602 
  603         /*
  604          * for chips with no clock doubler, but Ultra capable (e.g. 860, or interestingly the
  605          * first spin of the 875), assume 80MHz
  606          * otherwise use the internal (33 Mhz) or external (40MHz) default
  607          */
  608 
  609         if ((c->v->feature & Ultra) != 0 && (c->v->feature & (ClockDouble | ClockQuad)) == 0)
  610                 c->sclk = ULTRA_NOCLOCKDOUBLE_SCLK;
  611         else
  612                 c->sclk = SCLK;
  613 
  614         /*
  615          * otherwise, if the chip is Ultra capable, but has a slow(ish) clock,
  616          * invoke the doubler
  617          */
  618 
  619         if (SCLK <= 40000000) {
  620                 if (c->v->feature & ClockDouble) {
  621                         c->sclk *= 2;
  622                         c->clockmult = 1;
  623                 }
  624                 else if (c->v->feature & ClockQuad) {
  625                         c->sclk *= 4;
  626                         c->clockmult = 1;
  627                 }
  628                 else
  629                         c->clockmult = 0;
  630         }
  631         else
  632                 c->clockmult = 0;
  633 
  634         /* derive CCF from sclk */
  635         /* woebetide anyone with SCLK < 16.7 or > 80MHz */
  636         if (c->sclk <= 25 * MEGA)
  637                 c->ccf = 1;
  638         else if (c->sclk <= 3750000)
  639                 c->ccf = 2;
  640         else if (c->sclk <= 50 * MEGA)
  641                 c->ccf = 3;
  642         else if (c->sclk <= 75 * MEGA)
  643                 c->ccf = 4;
  644         else if ((c->v->feature & ClockDouble) && c->sclk <= 80 * MEGA)
  645                 c->ccf = 5;
  646         else if ((c->v->feature & ClockQuad) && c->sclk <= 120 * MEGA)
  647                 c->ccf = 6;
  648         else if ((c->v->feature & ClockQuad) && c->sclk <= 160 * MEGA)
  649                 c->ccf = 7;
  650 
  651         for (scf = 1; scf < maxscf; scf++) {
  652                 /* check for legal core rate */
  653                 /* round up so we run slower for safety */
  654                 cr = (c->sclk * 2 + cf2[scf] - 1) / cf2[scf];
  655                 if (cr <= MAXSYNCCORERATE) {
  656                         scsilimit = MAXSYNCSCSIRATE;
  657                         fast = 0;
  658                 }
  659                 else if (cr <= MAXFASTSYNCCORERATE) {
  660                         scsilimit = MAXFASTSYNCSCSIRATE;
  661                         fast = 1;
  662                 }
  663                 else if ((c->v->feature & Ultra) && cr <= MAXULTRASYNCCORERATE) {
  664                         scsilimit = MAXULTRASYNCSCSIRATE;
  665                         fast = 2;
  666                 }
  667                 else if ((c->v->feature & Ultra2) && cr <= MAXULTRA2SYNCCORERATE) {
  668                         scsilimit = MAXULTRA2SYNCSCSIRATE;
  669                         fast = 3;
  670                 }
  671                 else
  672                         continue;
  673                 for (xferp = 11; xferp >= 4; xferp--) {
  674                         int ok;
  675                         int tp;
  676                         /* calculate scsi rate - round up again */
  677                         /* start from sclk for accuracy */
  678                         int totaldivide = xferp * cf2[scf];
  679                         sr = (c->sclk * 2 + totaldivide - 1) / totaldivide;
  680                         if (sr > scsilimit)
  681                                 break;
  682                         /*
  683                          * now work out transfer period
  684                          * round down now so that period is pessimistic
  685                          */
  686                         tp = (MEGA * 1000) / sr;
  687                         /*
  688                          * bounds check it
  689                          */
  690                         if (tp < 25 || tp > 255 * 4)
  691                                 continue;
  692                         /*
  693                          * spot stupid special case for Ultra or Ultra2
  694                          * while working out factor
  695                          */
  696                         if (tp == 25)
  697                                 tpf = 10;
  698                         else if (tp == 50)
  699                                 tpf = 12;
  700                         else if (tp < 52)
  701                                 continue;
  702                         else
  703                                 tpf = tp / 4;
  704                         /*
  705                          * now check tpf looks sensible
  706                          * given core rate
  707                          */
  708                         switch (fast) {
  709                         case 0:
  710                                 /* scf must be ccf for SCSI 1 */
  711                                 ok = tpf >= 50 && scf == c->ccf;
  712                                 break;
  713                         case 1:
  714                                 ok = tpf >= 25 && tpf < 50;
  715                                 break;
  716                         case 2:
  717                                 /*
  718                                  * must use xferp of 4, or 5 at a pinch
  719                                  * for an Ultra transfer
  720                                  */
  721                                 ok = xferp <= 5 && tpf >= 12 && tpf < 25;
  722                                 break;
  723                         case 3:
  724                                 ok = xferp == 4 && (tpf == 10 || tpf == 11);
  725                                 break;
  726                         default:
  727                                 ok = 0;
  728                         }
  729                         if (!ok)
  730                                 continue;
  731                         c->synctab[scf - 1][xferp - 4] = tpf;
  732                 }
  733         }
  734 
  735 #ifndef NO_ULTRA2
  736         if (c->v->feature & Ultra2)
  737                 tpf = 10;
  738         else
  739 #endif
  740         if (c->v->feature & Ultra)
  741                 tpf = 12;
  742         else
  743                 tpf = 25;
  744         for (; tpf < 256; tpf++) {
  745                 if (chooserate(c, tpf, &scf, &xferp) == tpf) {
  746                         unsigned tp = tpf == 10 ? 25 : (tpf == 12 ? 50 : tpf * 4);
  747                         unsigned long khz = (MEGA + tp - 1) / (tp);
  748                         KPRINT(PRINTPREFIX "tpf=%d scf=%d.%.1d xferp=%d mhz=%ld.%.3ld\n",
  749                             tpf, cf2[scf] / 2, (cf2[scf] & 1) ? 5 : 0,
  750                             xferp + 4, khz / 1000, khz % 1000);
  751                         USED(khz);
  752                         if (c->tpf == 0)
  753                                 c->tpf = tpf;   /* note lowest value for controller */
  754                 }
  755         }
  756 }
  757 
  758 static void
  759 synctodsa(Dsa *dsa, Controller *c)
  760 {
  761 /*
  762         KPRINT("synctodsa(dsa=%lux, target=%d, scntl3=%.2lx sxfer=%.2x)\n",
  763             dsa, dsa->target, c->scntl3[dsa->target], c->sxfer[dsa->target]);
  764 */
  765         dsa->scntl3 = c->scntl3[dsa->target];
  766         dsa->sxfer = c->sxfer[dsa->target];
  767 }
  768 
  769 static void
  770 setsync(Dsa *dsa, Controller *c, int target, uchar ultra, uchar scf, uchar xferp, uchar reqack)
  771 {
  772         c->scntl3[target] =
  773             (c->scntl3[target] & 0x08) | (((scf << 4) | c->ccf | (ultra << 7)) & ~0x08);
  774         c->sxfer[target] = (xferp << 5) | reqack;
  775         c->s[target] = BothDone;
  776         if (dsa) {
  777                 synctodsa(dsa, c);
  778                 c->n->scntl3 = c->scntl3[target];
  779                 c->n->sxfer = c->sxfer[target];
  780         }
  781 }
  782 
  783 static void
  784 setasync(Dsa *dsa, Controller *c, int target)
  785 {
  786         setsync(dsa, c, target, 0, c->ccf, 0, 0);
  787 }
  788 
  789 static void
  790 setwide(Dsa *dsa, Controller *c, int target, uchar wide)
  791 {
  792         c->scntl3[target] = wide ? (1 << 3) : 0;
  793         setasync(dsa, c, target);
  794         c->s[target] = WideDone;
  795 }
  796 
  797 static int
  798 buildsdtrmsg(uchar *buf, uchar tpf, uchar offset)
  799 {
  800         *buf++ = X_MSG;
  801         *buf++ = 3;
  802         *buf++ = X_MSG_SDTR;
  803         *buf++ = tpf;
  804         *buf = offset;
  805         return 5;
  806 }
  807 
  808 static int
  809 buildwdtrmsg(uchar *buf, uchar expo)
  810 {
  811         *buf++ = X_MSG;
  812         *buf++ = 2;
  813         *buf++ = X_MSG_WDTR;
  814         *buf = expo;
  815         return 4;
  816 }
  817 
  818 static void
  819 start(Controller *c, long entry)
  820 {
  821         ulong p;
  822 
  823         if (c->running)
  824                 panic(PRINTPREFIX "start called while running");
  825         c->running = 1;
  826         p = c->scriptpa + entry;
  827         lesetl(c->n->dsp, p);
  828         coherence();
  829         if (c->ssm)
  830                 c->n->dcntl |= 0x4;             /* start DMA in SSI mode */
  831 }
  832 
  833 static void
  834 ncrcontinue(Controller *c)
  835 {
  836         if (c->running)
  837                 panic(PRINTPREFIX "ncrcontinue called while running");
  838         /* set the start DMA bit to continue execution */
  839         c->running = 1;
  840         coherence();
  841         c->n->dcntl |= 0x4;
  842 }
  843 
  844 static void
  845 softreset(Controller *c)
  846 {
  847         Ncr *n = c->n;
  848 
  849         n->istat = Srst;                /* software reset */
  850         n->istat = 0;
  851         /* general initialisation */
  852         n->scid = (1 << 6) | 7;         /* respond to reselect, ID 7 */
  853         n->respid = 1 << 7;             /* response ID = 7 */
  854 
  855 #ifdef INTERNAL_SCLK
  856         n->stest1 = 0x80;               /* disable external scsi clock */
  857 #else
  858         n->stest1 = 0x00;
  859 #endif
  860 
  861         n->stime0 = 0xdd;               /* about 0.5 second timeout on each device */
  862         n->scntl0 |= 0x8;               /* Enable parity checking */
  863 
  864         /* continued setup */
  865         n->sien0 = 0x8f;
  866         n->sien1 = 0x04;
  867         n->dien = 0x7d;
  868         n->stest3 = 0x80;               /* TolerANT enable */
  869         c->running = 0;
  870 
  871         if (c->v->feature & BigFifo)
  872                 n->ctest5 = (1 << 5);
  873         n->dmode = c->v->burst << 6;    /* set burst length bits */
  874         if (c->v->burst & 4)
  875                 n->ctest5 |= (1 << 2);  /* including overflow into ctest5 bit 2 */
  876         if (c->v->feature & Prefetch)
  877                 n->dcntl |= (1 << 5);   /* prefetch enable */
  878         else if (c->v->feature & BurstOpCodeFetch)
  879                 n->dmode |= (1 << 1);   /* burst opcode fetch */
  880         if (c->v->feature & Differential) {
  881                 /* chip capable */
  882                 if ((c->feature & Differential) || bios_set_differential(c)) {
  883                         /* user enabled, or some evidence bios set differential */
  884                         if (n->sstat2 & (1 << 2))
  885                                 print(PRINTPREFIX "can't go differential; wrong cable\n");
  886                         else {
  887                                 n->stest2 = (1 << 5);
  888                                 print(PRINTPREFIX "differential mode set\n");
  889                         }
  890                 }
  891         }
  892         if (c->clockmult) {
  893                 n->stest1 |= (1 << 3);  /* power up doubler */
  894                 delay(2);
  895                 n->stest3 |= (1 << 5);  /* stop clock */
  896                 n->stest1 |= (1 << 2);  /* enable doubler */
  897                 n->stest3 &= ~(1 << 5); /* start clock */
  898                 /* pray */
  899         }
  900 }
  901 
  902 static void
  903 msgsm(Dsa *dsa, Controller *c, int msg, int *cont, int *wakeme)
  904 {
  905         uchar histpf, hisreqack;
  906         int tpf;
  907         int scf, xferp;
  908         int len;
  909 
  910         Ncr *n = c->n;
  911 
  912         switch (c->s[dsa->target]) {
  913         case SyncInit:
  914                 switch (msg) {
  915                 case A_SIR_MSG_SDTR:
  916                         /* reply to my SDTR */
  917                         histpf = n->scratcha[2];
  918                         hisreqack = n->scratcha[3];
  919                         KPRINT(PRINTPREFIX "%d: SDTN response %d %d\n",
  920                             dsa->target, histpf, hisreqack);
  921 
  922                         if (hisreqack == 0)
  923                                 setasync(dsa, c, dsa->target);
  924                         else {
  925                                 /* hisreqack should be <= c->v->maxsyncoff */
  926                                 tpf = chooserate(c, histpf, &scf, &xferp);
  927                                 KPRINT(PRINTPREFIX "%d: SDTN: using %d %d\n",
  928                                     dsa->target, tpf, hisreqack);
  929                                 setsync(dsa, c, dsa->target, tpf < 25, scf, xferp, hisreqack);
  930                         }
  931                         *cont = -2;
  932                         return;
  933                 case A_SIR_EV_PHASE_SWITCH_AFTER_ID:
  934                         /* target ignored ATN for message after IDENTIFY - not SCSI-II */
  935                         KPRINT(PRINTPREFIX "%d: illegal phase switch after ID message - SCSI-1 device?\n", dsa->target);
  936                         KPRINT(PRINTPREFIX "%d: SDTN: async\n", dsa->target);
  937                         setasync(dsa, c, dsa->target);
  938                         *cont = E_to_decisions;
  939                         return;
  940                 case A_SIR_MSG_REJECT:
  941                         /* rejection of my SDTR */
  942                         KPRINT(PRINTPREFIX "%d: SDTN: rejected SDTR\n", dsa->target);
  943                 //async:
  944                         KPRINT(PRINTPREFIX "%d: SDTN: async\n", dsa->target);
  945                         setasync(dsa, c, dsa->target);
  946                         *cont = -2;
  947                         return;
  948                 }
  949                 break;
  950         case WideInit:
  951                 switch (msg) {
  952                 case A_SIR_MSG_WDTR:
  953                         /* reply to my WDTR */
  954                         KPRINT(PRINTPREFIX "%d: WDTN: response %d\n",
  955                             dsa->target, n->scratcha[2]);
  956                         setwide(dsa, c, dsa->target, n->scratcha[2]);
  957                         *cont = -2;
  958                         return;
  959                 case A_SIR_EV_PHASE_SWITCH_AFTER_ID:
  960                         /* target ignored ATN for message after IDENTIFY - not SCSI-II */
  961                         KPRINT(PRINTPREFIX "%d: illegal phase switch after ID message - SCSI-1 device?\n", dsa->target);
  962                         setwide(dsa, c, dsa->target, 0);
  963                         *cont = E_to_decisions;
  964                         return;
  965                 case A_SIR_MSG_REJECT:
  966                         /* rejection of my SDTR */
  967                         KPRINT(PRINTPREFIX "%d: WDTN: rejected WDTR\n", dsa->target);
  968                         setwide(dsa, c, dsa->target, 0);
  969                         *cont = -2;
  970                         return;
  971                 }
  972                 break;
  973 
  974         case NeitherDone:
  975         case WideDone:
  976         case BothDone:
  977                 switch (msg) {
  978                 case A_SIR_MSG_WDTR: {
  979                         uchar hiswide, mywide;
  980                         hiswide = n->scratcha[2];
  981                         mywide = (c->v->feature & Wide) != 0;
  982                         KPRINT(PRINTPREFIX "%d: WDTN: target init %d\n",
  983                             dsa->target, hiswide);
  984                         if (hiswide < mywide)
  985                                 mywide = hiswide;
  986                         KPRINT(PRINTPREFIX "%d: WDTN: responding %d\n",
  987                             dsa->target, mywide);
  988                         setwide(dsa, c, dsa->target, mywide);
  989                         len = buildwdtrmsg(dsa->msg_out, mywide);
  990                         setmovedata(&dsa->msg_out_buf, DMASEG(dsa->msg_out), len);
  991                         *cont = E_response;
  992                         c->s[dsa->target] = WideResponse;
  993                         return;
  994                 }
  995                 case A_SIR_MSG_SDTR:
  996 #ifdef ASYNC_ONLY
  997                         *cont = E_reject;
  998                         return;
  999 #else
 1000                         /* target decides to renegotiate */
 1001                         histpf = n->scratcha[2];
 1002                         hisreqack = n->scratcha[3];
 1003                         KPRINT(PRINTPREFIX "%d: SDTN: target init %d %d\n",
 1004                             dsa->target, histpf, hisreqack);
 1005                         if (hisreqack == 0) {
 1006                                 /* he wants asynchronous */
 1007                                 setasync(dsa, c, dsa->target);
 1008                                 tpf = 0;
 1009                         }
 1010                         else {
 1011                                 /* he wants synchronous */
 1012                                 tpf = chooserate(c, histpf, &scf, &xferp);
 1013                                 if (hisreqack > c->v->maxsyncoff)
 1014                                         hisreqack = c->v->maxsyncoff;
 1015                                 KPRINT(PRINTPREFIX "%d: using %d %d\n",
 1016                                     dsa->target, tpf, hisreqack);
 1017                                 setsync(dsa, c, dsa->target, tpf < 25, scf, xferp, hisreqack);
 1018                         }
 1019                         /* build my SDTR message */
 1020                         len = buildsdtrmsg(dsa->msg_out, tpf, hisreqack);
 1021                         setmovedata(&dsa->msg_out_buf, DMASEG(dsa->msg_out), len);
 1022                         *cont = E_response;
 1023                         c->s[dsa->target] = SyncResponse;
 1024                         return;
 1025 #endif
 1026                 }
 1027                 break;
 1028         case WideResponse:
 1029                 switch (msg) {
 1030                 case A_SIR_EV_RESPONSE_OK:
 1031                         c->s[dsa->target] = WideDone;
 1032                         KPRINT(PRINTPREFIX "%d: WDTN: response accepted\n", dsa->target);
 1033                         *cont = -2;
 1034                         return;
 1035                 case A_SIR_MSG_REJECT:
 1036                         setwide(dsa, c, dsa->target, 0);
 1037                         KPRINT(PRINTPREFIX "%d: WDTN: response REJECTed\n", dsa->target);
 1038                         *cont = -2;
 1039                         return;
 1040                 }
 1041                 break;
 1042         case SyncResponse:
 1043                 switch (msg) {
 1044                 case A_SIR_EV_RESPONSE_OK:
 1045                         c->s[dsa->target] = BothDone;
 1046                         KPRINT(PRINTPREFIX "%d: SDTN: response accepted (%s)\n",
 1047                             dsa->target, phase[n->sstat1 & 7]);
 1048                         *cont = -2;
 1049                         return; /* chf */
 1050                 case A_SIR_MSG_REJECT:
 1051                         setasync(dsa, c, dsa->target);
 1052                         KPRINT(PRINTPREFIX "%d: SDTN: response REJECTed\n", dsa->target);
 1053                         *cont = -2;
 1054                         return;
 1055                 }
 1056                 break;
 1057         }
 1058         KPRINT(PRINTPREFIX "%d: msgsm: state %d msg %d\n",
 1059             dsa->target, c->s[dsa->target], msg);
 1060         *wakeme = 1;
 1061         return;
 1062 }
 1063 
 1064 static void
 1065 calcblockdma(Dsa *d, ulong base, ulong count)
 1066 {
 1067         ulong blocks;
 1068         if (DEBUG(3))
 1069                 blocks = 0;
 1070         else {
 1071                 blocks = count / A_BSIZE;
 1072                 if (blocks > 255)
 1073                         blocks = 255;
 1074         }
 1075         d->dmablks = blocks;
 1076         d->dmaaddr[0] = base;
 1077         d->dmaaddr[1] = base >> 8;
 1078         d->dmaaddr[2] = base >> 16;
 1079         d->dmaaddr[3] = base >> 24;
 1080         setmovedata(&d->data_buf, base + blocks * A_BSIZE, count - blocks * A_BSIZE);
 1081         d->flag = legetl(d->data_buf.dbc) == 0;
 1082 }
 1083 
 1084 static ulong
 1085 read_mismatch_recover(Controller *c, Ncr *n, Dsa *dsa)
 1086 {
 1087         ulong dbc;
 1088         uchar dfifo = n->dfifo;
 1089         int inchip;
 1090 
 1091         dbc = (n->dbc[2]<<16)|(n->dbc[1]<<8)|n->dbc[0];
 1092         if (n->ctest5 & (1 << 5))
 1093                 inchip = ((dfifo | ((n->ctest5 & 3) << 8)) - (dbc & 0x3ff)) & 0x3ff;
 1094         else
 1095                 inchip = ((dfifo & 0x7f) - (dbc & 0x7f)) & 0x7f;
 1096         if (inchip) {
 1097                 IPRINT(PRINTPREFIX "%d/%d: read_mismatch_recover: DMA FIFO = %d\n",
 1098                     dsa->target, dsa->lun, inchip);
 1099         }
 1100         if (n->sxfer & SYNCOFFMASK(c)) {
 1101                 /* SCSI FIFO */
 1102                 uchar fifo = n->sstat1 >> 4;
 1103                 if (c->v->maxsyncoff > 8)
 1104                         fifo |= (n->sstat2 & (1 << 4));
 1105                 if (fifo) {
 1106                         inchip += fifo;
 1107                         IPRINT(PRINTPREFIX "%d/%d: read_mismatch_recover: SCSI FIFO = %d\n",
 1108                             dsa->target, dsa->lun, fifo);
 1109                 }
 1110         }
 1111         else {
 1112                 if (n->sstat0 & (1 << 7)) {
 1113                         inchip++;
 1114                         IPRINT(PRINTPREFIX "%d/%d: read_mismatch_recover: SIDL full\n",
 1115                             dsa->target, dsa->lun);
 1116                 }
 1117                 if (n->sstat2 & (1 << 7)) {
 1118                         inchip++;
 1119                         IPRINT(PRINTPREFIX "%d/%d: read_mismatch_recover: SIDL msb full\n",
 1120                             dsa->target, dsa->lun);
 1121                 }
 1122         }
 1123         USED(inchip);
 1124         return dbc;
 1125 }
 1126 
 1127 static ulong
 1128 write_mismatch_recover(Controller *c, Ncr *n, Dsa *dsa)
 1129 {
 1130         ulong dbc;
 1131         uchar dfifo = n->dfifo;
 1132         int inchip;
 1133 
 1134         dbc = (n->dbc[2]<<16)|(n->dbc[1]<<8)|n->dbc[0];
 1135         USED(dsa);
 1136         if (n->ctest5 & (1 << 5))
 1137                 inchip = ((dfifo | ((n->ctest5 & 3) << 8)) - (dbc & 0x3ff)) & 0x3ff;
 1138         else
 1139                 inchip = ((dfifo & 0x7f) - (dbc & 0x7f)) & 0x7f;
 1140 #ifdef WMR_DEBUG
 1141         if (inchip) {
 1142                 IPRINT(PRINTPREFIX "%d/%d: write_mismatch_recover: DMA FIFO = %d\n",
 1143                     dsa->target, dsa->lun, inchip);
 1144         }
 1145 #endif
 1146         if (n->sstat0 & (1 << 5)) {
 1147                 inchip++;
 1148 #ifdef WMR_DEBUG
 1149                 IPRINT(PRINTPREFIX "%d/%d: write_mismatch_recover: SODL full\n", dsa->target, dsa->lun);
 1150 #endif
 1151         }
 1152         if (n->sstat2 & (1 << 5)) {
 1153                 inchip++;
 1154 #ifdef WMR_DEBUG
 1155                 IPRINT(PRINTPREFIX "%d/%d: write_mismatch_recover: SODL msb full\n", dsa->target, dsa->lun);
 1156 #endif
 1157         }
 1158         if (n->sxfer & SYNCOFFMASK(c)) {
 1159                 /* synchronous SODR */
 1160                 if (n->sstat0 & (1 << 6)) {
 1161                         inchip++;
 1162 #ifdef WMR_DEBUG
 1163                         IPRINT(PRINTPREFIX "%d/%d: write_mismatch_recover: SODR full\n",
 1164                             dsa->target, dsa->lun);
 1165 #endif
 1166                 }
 1167                 if (n->sstat2 & (1 << 6)) {
 1168                         inchip++;
 1169 #ifdef WMR_DEBUG
 1170                         IPRINT(PRINTPREFIX "%d/%d: write_mismatch_recover: SODR msb full\n",
 1171                             dsa->target, dsa->lun);
 1172 #endif
 1173                 }
 1174         }
 1175         /* clear the dma fifo */
 1176         n->ctest3 |= (1 << 2);
 1177         /* wait till done */
 1178         while ((n->dstat & Dfe) == 0)
 1179                 ;
 1180         return dbc + inchip;
 1181 }
 1182 
 1183 static void
 1184 sd53c8xxinterrupt(Ureg *ur, void *a)
 1185 {
 1186         uchar istat, dstat;
 1187         ushort sist;
 1188         int wakeme = 0;
 1189         int cont = -1;
 1190         Dsa *dsa;
 1191         ulong dsapa;
 1192         Controller *c = a;
 1193         Ncr *n = c->n;
 1194 
 1195         USED(ur);
 1196         if (DEBUG(1)) {
 1197                 IPRINT(PRINTPREFIX "int\n");
 1198         }
 1199         ilock(c);
 1200         istat = n->istat;
 1201         if (istat & Intf) {
 1202                 Dsa *d;
 1203                 int wokesomething = 0;
 1204                 if (DEBUG(1)) {
 1205                         IPRINT(PRINTPREFIX "Intfly\n");
 1206                 }
 1207                 n->istat = Intf;
 1208                 /* search for structures in A_STATE_DONE */
 1209                 for (d = KPTR(legetl(c->dsalist.head)); d != dsaend; d = KPTR(legetl(d->next))) {
 1210                         if (d->stateb == A_STATE_DONE) {
 1211                                 d->p9status = d->status;
 1212                                 if (DEBUG(1)) {
 1213                                         IPRINT(PRINTPREFIX "waking up dsa %lux\n", (ulong)d);
 1214                                 }
 1215                                 wakeup(d);
 1216                                 wokesomething = 1;
 1217                         }
 1218                 }
 1219                 if (!wokesomething) {
 1220                         IPRINT(PRINTPREFIX "nothing to wake up\n");
 1221                 }
 1222         }
 1223 
 1224         if ((istat & (Sip | Dip)) == 0) {
 1225                 if (DEBUG(1)) {
 1226                         IPRINT(PRINTPREFIX "int end %x\n", istat);
 1227                 }
 1228                 iunlock(c);
 1229                 return;
 1230         }
 1231 
 1232         sist = (n->sist1<<8)|n->sist0;  /* BUG? can two-byte read be inconsistent? */
 1233         dstat = n->dstat;
 1234         dsapa = legetl(n->dsa);
 1235 
 1236         /*
 1237          * Can't compute dsa until we know that dsapa is valid.
 1238          */
 1239         if(dsapa < -KZERO)
 1240                 dsa = (Dsa*)DMASEG_TO_KADDR(dsapa);
 1241         else{
 1242                 dsa = nil;
 1243                 /*
 1244                  * happens at startup on some cards but we 
 1245                  * don't actually deref dsa because none of the
 1246                  * flags we are about are set.
 1247                  * still, print in case that changes and we're
 1248                  * about to dereference nil.
 1249                  */
 1250                 iprint("sd53c8xxinterrupt: dsa=%.8lux istat=%ux sist=%ux dstat=%ux\n", dsapa, istat, sist, dstat);
 1251         }
 1252 
 1253         c->running = 0;
 1254         if (istat & Sip) {
 1255                 if (DEBUG(1)) {
 1256                         IPRINT("sist = %.4x\n", sist);
 1257                 }
 1258                 if (sist & 0x80) {
 1259                         ulong addr;
 1260                         ulong sa;
 1261                         ulong dbc;
 1262                         ulong tbc;
 1263                         int dmablks;
 1264                         ulong dmaaddr;
 1265 
 1266                         addr = legetl(n->dsp);
 1267                         sa = addr - c->scriptpa;
 1268                         if (DEBUG(1) || DEBUG(2)) {
 1269                                 IPRINT(PRINTPREFIX "%d/%d: Phase Mismatch sa=%.8lux\n",
 1270                                     dsa->target, dsa->lun, sa);
 1271                         }
 1272                         /*
 1273                          * now recover
 1274                          */
 1275                         if (sa == E_data_in_mismatch) {
 1276                                 /*
 1277                                  * though this is a failure in the residue, there may have been blocks
 1278                                  * as well. if so, dmablks will not have been zeroed, since the state
 1279                                  * was not saved by the microcode. 
 1280                                  */
 1281                                 dbc = read_mismatch_recover(c, n, dsa);
 1282                                 tbc = legetl(dsa->data_buf.dbc) - dbc;
 1283                                 dsa->dmablks = 0;
 1284                                 n->scratcha[2] = 0;
 1285                                 advancedata(&dsa->data_buf, tbc);
 1286                                 if (DEBUG(1) || DEBUG(2)) {
 1287                                         IPRINT(PRINTPREFIX "%d/%d: transferred = %ld residue = %ld\n",
 1288                                             dsa->target, dsa->lun, tbc, legetl(dsa->data_buf.dbc));
 1289                                 }
 1290                                 cont = E_data_mismatch_recover;
 1291                         }
 1292                         else if (sa == E_data_in_block_mismatch) {
 1293                                 dbc = read_mismatch_recover(c, n, dsa);
 1294                                 tbc = A_BSIZE - dbc;
 1295                                 /* recover current state from registers */
 1296                                 dmablks = n->scratcha[2];
 1297                                 dmaaddr = legetl(n->scratchb);
 1298                                 /* we have got to dmaaddr + tbc */
 1299                                 /* we have dmablks * A_BSIZE - tbc + residue left to do */
 1300                                 /* so remaining transfer is */
 1301                                 IPRINT("in_block_mismatch: dmaaddr = 0x%lux tbc=%lud dmablks=%d\n",
 1302                                     dmaaddr, tbc, dmablks);
 1303                                 calcblockdma(dsa, dmaaddr + tbc,
 1304                                     dmablks * A_BSIZE - tbc + legetl(dsa->data_buf.dbc));
 1305                                 /* copy changes into scratch registers */
 1306                                 IPRINT("recalc: dmablks %d dmaaddr 0x%lx pa 0x%lx dbc %ld\n",
 1307                                     dsa->dmablks, legetl(dsa->dmaaddr),
 1308                                     legetl(dsa->data_buf.pa), legetl(dsa->data_buf.dbc));
 1309                                 n->scratcha[2] = dsa->dmablks;
 1310                                 lesetl(n->scratchb, dsa->dmancr);
 1311                                 cont = E_data_block_mismatch_recover;
 1312                         }
 1313                         else if (sa == E_data_out_mismatch) {
 1314                                 dbc = write_mismatch_recover(c, n, dsa);
 1315                                 tbc = legetl(dsa->data_buf.dbc) - dbc;
 1316                                 dsa->dmablks = 0;
 1317                                 n->scratcha[2] = 0;
 1318                                 advancedata(&dsa->data_buf, tbc);
 1319                                 if (DEBUG(1) || DEBUG(2)) {
 1320                                         IPRINT(PRINTPREFIX "%d/%d: transferred = %ld residue = %ld\n",
 1321                                             dsa->target, dsa->lun, tbc, legetl(dsa->data_buf.dbc));
 1322                                 }
 1323                                 cont = E_data_mismatch_recover;
 1324                         }
 1325                         else if (sa == E_data_out_block_mismatch) {
 1326                                 dbc = write_mismatch_recover(c, n, dsa);
 1327                                 tbc = legetl(dsa->data_buf.dbc) - dbc;
 1328                                 /* recover current state from registers */
 1329                                 dmablks = n->scratcha[2];
 1330                                 dmaaddr = legetl(n->scratchb);
 1331                                 /* we have got to dmaaddr + tbc */
 1332                                 /* we have dmablks blocks - tbc + residue left to do */
 1333                                 /* so remaining transfer is */
 1334                                 IPRINT("out_block_mismatch: dmaaddr = %lux tbc=%lud dmablks=%d\n",
 1335                                     dmaaddr, tbc, dmablks);
 1336                                 calcblockdma(dsa, dmaaddr + tbc,
 1337                                     dmablks * A_BSIZE - tbc + legetl(dsa->data_buf.dbc));
 1338                                 /* copy changes into scratch registers */
 1339                                 n->scratcha[2] = dsa->dmablks;
 1340                                 lesetl(n->scratchb, dsa->dmancr);
 1341                                 cont = E_data_block_mismatch_recover;
 1342                         }
 1343                         else if (sa == E_id_out_mismatch) {
 1344                                 /*
 1345                                  * target switched phases while attention held during
 1346                                  * message out. The possibilities are:
 1347                                  * 1. It didn't like the last message. This is indicated
 1348                                  *    by the new phase being message_in. Use script to recover
 1349                                  *
 1350                                  * 2. It's not SCSI-II compliant. The new phase will be other
 1351                                  *    than message_in. We should also indicate that the device
 1352                                  *    is asynchronous, if it's the SDTR that got ignored
 1353                                  * 
 1354                                  * For now, if the phase switch is not to message_in, and
 1355                                  * and it happens after IDENTIFY and before SDTR, we
 1356                                  * notify the negotiation state machine.
 1357                                  */
 1358                                 ulong lim = legetl(dsa->msg_out_buf.dbc);
 1359                                 uchar p = n->sstat1 & 7;
 1360                                 dbc = write_mismatch_recover(c, n, dsa);
 1361                                 tbc = lim - dbc;
 1362                                 IPRINT(PRINTPREFIX "%d/%d: msg_out_mismatch: %lud/%lud sent, phase %s\n",
 1363                                     dsa->target, dsa->lun, tbc, lim, phase[p]);
 1364                                 if (p != MessageIn && tbc == 1) {
 1365                                         msgsm(dsa, c, A_SIR_EV_PHASE_SWITCH_AFTER_ID, &cont, &wakeme);
 1366                                 }
 1367                                 else
 1368                                         cont = E_id_out_mismatch_recover;
 1369                         }
 1370                         else if (sa == E_cmd_out_mismatch) {
 1371                                 /*
 1372                                  * probably the command count is longer than the device wants ...
 1373                                  */
 1374                                 ulong lim = legetl(dsa->cmd_buf.dbc);
 1375                                 uchar p = n->sstat1 & 7;
 1376                                 dbc = write_mismatch_recover(c, n, dsa);
 1377                                 tbc = lim - dbc;
 1378                                 IPRINT(PRINTPREFIX "%d/%d: cmd_out_mismatch: %lud/%lud sent, phase %s\n",
 1379                                     dsa->target, dsa->lun, tbc, lim, phase[p]);
 1380                                 USED(p, tbc);
 1381                                 cont = E_to_decisions;
 1382                         }
 1383                         else {
 1384                                 IPRINT(PRINTPREFIX "%d/%d: ma sa=%.8lux wanted=%s got=%s\n",
 1385                                     dsa->target, dsa->lun, sa,
 1386                                     phase[n->dcmd & 7],
 1387                                     phase[n->sstat1 & 7]);
 1388                                 dumpncrregs(c, 1);
 1389                                 dsa->p9status = SDeio;  /* chf */
 1390                                 wakeme = 1;
 1391                         }
 1392                 }
 1393                 /*else*/ if (sist & 0x400) {
 1394                         if (DEBUG(0)) {
 1395                                 IPRINT(PRINTPREFIX "%d/%d Sto\n", dsa->target, dsa->lun);
 1396                         }
 1397                         dsa->p9status = SDtimeout;
 1398                         dsa->stateb = A_STATE_DONE;
 1399                         coherence();
 1400                         softreset(c);
 1401                         cont = E_issue_check;
 1402                         wakeme = 1;
 1403                 }
 1404                 if (sist & 0x1) {
 1405                         IPRINT(PRINTPREFIX "%d/%d: parity error\n", dsa->target, dsa->lun);
 1406                         dsa->parityerror = 1;
 1407                 }
 1408                 if (sist & 0x4) {
 1409                         IPRINT(PRINTPREFIX "%s%d lun %d: unexpected disconnect\n",
 1410                                 c->sdev->name, dsa->target, dsa->lun);
 1411                         dumpncrregs(c, 1);
 1412                         //wakeme = 1;
 1413                         dsa->p9status = SDeio;
 1414                 }
 1415         }
 1416         if (istat & Dip) {
 1417                 if (DEBUG(1)) {
 1418                         IPRINT("dstat = %.2x\n", dstat);
 1419                 }
 1420                 /*else*/ if (dstat & Ssi) {
 1421                         ulong w = legetl(n->dsp) - c->scriptpa;
 1422                         IPRINT("[%lux]", w);
 1423                         USED(w);
 1424                         cont = -2;      /* restart */
 1425                 }
 1426                 if (dstat & Sir) {
 1427                         switch (legetl(n->dsps)) {
 1428                         case A_SIR_MSG_IO_COMPLETE:
 1429                                 dsa->p9status = dsa->status;
 1430                                 wakeme = 1;
 1431                                 break;
 1432                         case A_SIR_MSG_SDTR:
 1433                         case A_SIR_MSG_WDTR:
 1434                         case A_SIR_MSG_REJECT:
 1435                         case A_SIR_EV_RESPONSE_OK:
 1436                                 msgsm(dsa, c, legetl(n->dsps), &cont, &wakeme);
 1437                                 break;
 1438                         case A_SIR_MSG_IGNORE_WIDE_RESIDUE:
 1439                                 /* back up one in the data transfer */
 1440                                 IPRINT(PRINTPREFIX "%d/%d: ignore wide residue %d, WSR = %d\n",
 1441                                     dsa->target, dsa->lun, n->scratcha[1], n->scntl2 & 1);
 1442                                 if (dsa->flag == 2) {
 1443                                         IPRINT(PRINTPREFIX "%d/%d: transfer over; residue ignored\n",
 1444                                             dsa->target, dsa->lun);
 1445                                 }
 1446                                 else {
 1447                                         calcblockdma(dsa, legetl(dsa->dmaaddr) - 1,
 1448                                             dsa->dmablks * A_BSIZE + legetl(dsa->data_buf.dbc) + 1);
 1449                                 }
 1450                                 cont = -2;
 1451                                 break;
 1452                         case A_SIR_ERROR_NOT_MSG_IN_AFTER_RESELECT:
 1453                                 IPRINT(PRINTPREFIX "%d: not msg_in after reselect (%s)",
 1454                                     n->ssid & SSIDMASK(c), phase[n->sstat1 & 7]);
 1455                                 dsa = dsafind(c, n->ssid & SSIDMASK(c), -1, A_STATE_DISCONNECTED);
 1456                                 dumpncrregs(c, 1);
 1457                                 wakeme = 1;
 1458                                 break;
 1459                         case A_SIR_NOTIFY_LOAD_STATE:
 1460                                 IPRINT(PRINTPREFIX ": load_state dsa=%p\n", dsa);
 1461                                 if (dsa == (void*)KZERO || dsa == (void*)-1) {
 1462                                         dsadump(c);
 1463                                         dumpncrregs(c, 1);
 1464                                         panic("bad dsa in load_state");
 1465                                 }
 1466                                 cont = -2;
 1467                                 break;
 1468                         case A_SIR_NOTIFY_MSG_IN:
 1469                                 IPRINT(PRINTPREFIX "%d/%d: msg_in %d\n",
 1470                                     dsa->target, dsa->lun, n->sfbr);
 1471                                 cont = -2;
 1472                                 break;
 1473                         case A_SIR_NOTIFY_DISC:
 1474                                 IPRINT(PRINTPREFIX "%d/%d: disconnect:", dsa->target, dsa->lun);
 1475                                 goto dsadump;
 1476                         case A_SIR_NOTIFY_STATUS:
 1477                                 IPRINT(PRINTPREFIX "%d/%d: status\n", dsa->target, dsa->lun);
 1478                                 cont = -2;
 1479                                 break;
 1480                         case A_SIR_NOTIFY_COMMAND:
 1481                                 IPRINT(PRINTPREFIX "%d/%d: commands\n", dsa->target, dsa->lun);
 1482                                 cont = -2;
 1483                                 break;
 1484                         case A_SIR_NOTIFY_DATA_IN:
 1485                                 IPRINT(PRINTPREFIX "%d/%d: data in a %lx b %lx\n",
 1486                                     dsa->target, dsa->lun, legetl(n->scratcha), legetl(n->scratchb));
 1487                                 cont = -2;
 1488                                 break;
 1489                         case A_SIR_NOTIFY_BLOCK_DATA_IN:
 1490                                 IPRINT(PRINTPREFIX "%d/%d: block data in: a2 %x b %lx\n",
 1491                                     dsa->target, dsa->lun, n->scratcha[2], legetl(n->scratchb));
 1492                                 cont = -2;
 1493                                 break;
 1494                         case A_SIR_NOTIFY_DATA_OUT:
 1495                                 IPRINT(PRINTPREFIX "%d/%d: data out\n", dsa->target, dsa->lun);
 1496                                 cont = -2;
 1497                                 break;
 1498                         case A_SIR_NOTIFY_DUMP:
 1499                                 IPRINT(PRINTPREFIX "%d/%d: dump\n", dsa->target, dsa->lun);
 1500                                 dumpncrregs(c, 1);
 1501                                 cont = -2;
 1502                                 break;
 1503                         case A_SIR_NOTIFY_DUMP2:
 1504                                 IPRINT(PRINTPREFIX "%d/%d: dump2:", dsa->target, dsa->lun);
 1505                                 IPRINT(" sa %lux", legetl(n->dsp) - c->scriptpa);
 1506                                 IPRINT(" dsa %lux", legetl(n->dsa));
 1507                                 IPRINT(" sfbr %ux", n->sfbr);
 1508                                 IPRINT(" a %lux", legetl(n->scratcha));
 1509                                 IPRINT(" b %lux", legetl(n->scratchb));
 1510                                 IPRINT(" ssid %ux", n->ssid);
 1511                                 IPRINT("\n");
 1512                                 cont = -2;
 1513                                 break;
 1514                         case A_SIR_NOTIFY_WAIT_RESELECT:
 1515                                 IPRINT(PRINTPREFIX "wait reselect\n");
 1516                                 cont = -2;
 1517                                 break;
 1518                         case A_SIR_NOTIFY_RESELECT:
 1519                                 IPRINT(PRINTPREFIX "reselect: ssid %.2x sfbr %.2x at %ld\n",
 1520                                     n->ssid, n->sfbr, TK2MS(m->ticks));
 1521                                 cont = -2;
 1522                                 break;
 1523                         case A_SIR_NOTIFY_ISSUE:
 1524                                 IPRINT(PRINTPREFIX "%d/%d: issue dsa=%p end=%p:", dsa->target, dsa->lun, dsa, dsaend);
 1525                         dsadump:
 1526                                 IPRINT(" tgt=%d", dsa->target);
 1527                                 IPRINT(" time=%ld", TK2MS(m->ticks));
 1528                                 IPRINT("\n");
 1529                                 cont = -2;
 1530                                 break;
 1531                         case A_SIR_NOTIFY_ISSUE_CHECK:
 1532                                 IPRINT(PRINTPREFIX "issue check\n");
 1533                                 cont = -2;
 1534                                 break;
 1535                         case A_SIR_NOTIFY_SIGP:
 1536                                 IPRINT(PRINTPREFIX "responded to SIGP\n");
 1537                                 cont = -2;
 1538                                 break;
 1539                         case A_SIR_NOTIFY_DUMP_NEXT_CODE: {
 1540                                 ulong *dsp = c->script + (legetl(n->dsp)-c->scriptpa)/4;
 1541                                 int x;
 1542                                 IPRINT(PRINTPREFIX "code at %lux", dsp - c->script);
 1543                                 for (x = 0; x < 6; x++) {
 1544                                         IPRINT(" %.8lux", dsp[x]);
 1545                                 }
 1546                                 IPRINT("\n");
 1547                                 USED(dsp);
 1548                                 cont = -2;
 1549                                 break;
 1550                         }
 1551                         case A_SIR_NOTIFY_WSR:
 1552                                 IPRINT(PRINTPREFIX "%d/%d: WSR set\n", dsa->target, dsa->lun);
 1553                                 cont = -2;
 1554                                 break;
 1555                         case A_SIR_NOTIFY_LOAD_SYNC:
 1556                                 IPRINT(PRINTPREFIX "%d/%d: scntl=%.2x sxfer=%.2x\n",
 1557                                     dsa->target, dsa->lun, n->scntl3, n->sxfer);
 1558                                 cont = -2;
 1559                                 break;
 1560                         case A_SIR_NOTIFY_RESELECTED_ON_SELECT:
 1561                                 if (DEBUG(2)) {
 1562                                         IPRINT(PRINTPREFIX "%d/%d: reselected during select\n",
 1563                                             dsa->target, dsa->lun);
 1564                                 }
 1565                                 cont = -2;
 1566                                 break;
 1567                         case A_error_reselected:                /* dsa isn't valid here */
 1568                                 iprint(PRINTPREFIX "reselection error\n");
 1569                                 dumpncrregs(c, 1);
 1570                                 for (dsa = KPTR(legetl(c->dsalist.head)); dsa != dsaend; dsa = KPTR(legetl(dsa->next))) {
 1571                                         IPRINT(PRINTPREFIX "dsa target %d lun %d state %d\n", dsa->target, dsa->lun, dsa->stateb);
 1572                                 }
 1573                                 break;
 1574                         default:
 1575                                 IPRINT(PRINTPREFIX "%d/%d: script error %ld\n",
 1576                                         dsa->target, dsa->lun, legetl(n->dsps));
 1577                                 dumpncrregs(c, 1);
 1578                                 wakeme = 1;
 1579                         }
 1580                 }
 1581                 /*else*/ if (dstat & Iid) {
 1582                         int i, target, lun;
 1583                         ulong addr, dbc, *v;
 1584                         
 1585                         addr = legetl(n->dsp);
 1586                         if(dsa){
 1587                                 target = dsa->target;
 1588                                 lun = dsa->lun;
 1589                         }else{
 1590                                 target = -1;
 1591                                 lun = -1;
 1592                         }
 1593                         dbc = (n->dbc[2]<<16)|(n->dbc[1]<<8)|n->dbc[0];
 1594 
 1595                 //      if(dsa == nil)
 1596                                 idebug++;
 1597                         IPRINT(PRINTPREFIX "%d/%d: Iid pa=%.8lux sa=%.8lux dbc=%lux\n",
 1598                             target, lun,
 1599                             addr, addr - c->scriptpa, dbc);
 1600                         addr = (ulong)c->script + addr - c->scriptpa;
 1601                         addr -= 64;
 1602                         addr &= ~63;
 1603                         v = (ulong*)addr;
 1604                         for(i=0; i<8; i++){
 1605                                 IPRINT("%.8lux: %.8lux %.8lux %.8lux %.8lux\n", 
 1606                                         addr, v[0], v[1], v[2], v[3]);
 1607                                 addr += 4*4;
 1608                                 v += 4;
 1609                         }
 1610                         USED(addr, dbc);
 1611                         if(dsa == nil){
 1612                                 dsadump(c);
 1613                                 dumpncrregs(c, 1);
 1614                                 panic("bad dsa");
 1615                         }
 1616                         dsa->p9status = SDeio;
 1617                         wakeme = 1;
 1618                 }
 1619                 /*else*/ if (dstat & Bf) {
 1620                         IPRINT(PRINTPREFIX "%d/%d: Bus Fault\n", dsa->target, dsa->lun);
 1621                         dumpncrregs(c, 1);
 1622                         dsa->p9status = SDeio;
 1623                         wakeme = 1;
 1624                 }
 1625         }
 1626         if (cont == -2)
 1627                 ncrcontinue(c);
 1628         else if (cont >= 0)
 1629                 start(c, cont);
 1630         if (wakeme){
 1631                 if(dsa->p9status == SDnostatus)
 1632                         dsa->p9status = SDeio;
 1633                 wakeup(dsa);
 1634         }
 1635         iunlock(c);
 1636         if (DEBUG(1)) {
 1637                 IPRINT(PRINTPREFIX "int end 1\n");
 1638         }
 1639 }
 1640 
 1641 static int
 1642 done(void *arg)
 1643 {
 1644         return ((Dsa *)arg)->p9status != SDnostatus;
 1645 }
 1646 
 1647 static void
 1648 setmovedata(Movedata *d, ulong pa, ulong bc)
 1649 {
 1650         d->pa[0] = pa;
 1651         d->pa[1] = pa>>8;
 1652         d->pa[2] = pa>>16;
 1653         d->pa[3] = pa>>24;
 1654         d->dbc[0] = bc;
 1655         d->dbc[1] = bc>>8;
 1656         d->dbc[2] = bc>>16;
 1657         d->dbc[3] = bc>>24;
 1658 }
 1659 
 1660 static void
 1661 advancedata(Movedata *d, long v)
 1662 {
 1663         lesetl(d->pa, legetl(d->pa) + v);
 1664         lesetl(d->dbc, legetl(d->dbc) - v);
 1665 }
 1666 
 1667 static void
 1668 dumpwritedata(uchar *data, int datalen)
 1669 {
 1670         int i;
 1671         uchar *bp;
 1672         if (!DEBUG(0)){
 1673                 USED(data, datalen);
 1674                 return;
 1675         }
 1676 
 1677         if (datalen) {
 1678                 KPRINT(PRINTPREFIX "write:");
 1679                 for (i = 0, bp = data; i < 50 && i < datalen; i++, bp++) {
 1680                         KPRINT("%.2ux", *bp);
 1681                 }
 1682                 if (i < datalen) {
 1683                         KPRINT("...");
 1684                 }
 1685                 KPRINT("\n");
 1686         }
 1687 }
 1688 
 1689 static void
 1690 dumpreaddata(uchar *data, int datalen)
 1691 {
 1692         int i;
 1693         uchar *bp;
 1694         if (!DEBUG(0)){
 1695                 USED(data, datalen);
 1696                 return;
 1697         }
 1698 
 1699         if (datalen) {
 1700                 KPRINT(PRINTPREFIX "read:");
 1701                 for (i = 0, bp = data; i < 50 && i < datalen; i++, bp++) {
 1702                         KPRINT("%.2ux", *bp);
 1703                 }
 1704                 if (i < datalen) {
 1705                         KPRINT("...");
 1706                 }
 1707                 KPRINT("\n");
 1708         }
 1709 }
 1710 
 1711 static void
 1712 busreset(Controller *c)
 1713 {
 1714         int x, ntarget;
 1715 
 1716         /* bus reset */
 1717         c->n->scntl1 |= (1 << 3);
 1718         delay(500);
 1719         c->n->scntl1 &= ~(1 << 3);
 1720         if(!(c->v->feature & Wide))
 1721                 ntarget = 8;
 1722         else
 1723                 ntarget = MAXTARGET;
 1724         for (x = 0; x < ntarget; x++) {
 1725                 setwide(0, c, x, 0);
 1726 #ifndef ASYNC_ONLY
 1727                 c->s[x] = NeitherDone;
 1728 #endif
 1729         }
 1730         c->capvalid = 0;
 1731 }
 1732 
 1733 static void
 1734 reset(Controller *c)
 1735 {
 1736         /* should wakeup all pending tasks */
 1737         softreset(c);
 1738         busreset(c);
 1739 }
 1740 
 1741 static int
 1742 sd53c8xxrio(SDreq* r)
 1743 {
 1744         Dsa *d;
 1745         uchar *bp;
 1746         Controller *c;
 1747         uchar target_expo, my_expo;
 1748         int bc, check, i, status, target;
 1749 
 1750         if((target = r->unit->subno) == 0x07)
 1751                 return r->status = SDtimeout;   /* assign */
 1752 
 1753         c = r->unit->dev->ctlr;
 1754 
 1755         check = 0;
 1756         d = dsaalloc(c, target, r->lun);
 1757 
 1758         qlock(&c->q[target]);                   /* obtain access to target */
 1759 docheck:
 1760         /* load the transfer control stuff */
 1761         d->scsi_id_buf[0] = 0;
 1762         d->scsi_id_buf[1] = c->sxfer[target];
 1763         d->scsi_id_buf[2] = target;
 1764         d->scsi_id_buf[3] = c->scntl3[target];
 1765         synctodsa(d, c);
 1766 
 1767         bc = 0;
 1768 
 1769         d->msg_out[bc] = 0x80 | r->lun;
 1770 
 1771 #ifndef NO_DISCONNECT
 1772         d->msg_out[bc] |= (1 << 6);
 1773 #endif
 1774         bc++;
 1775 
 1776         /* work out what to do about negotiation */
 1777         switch (c->s[target]) {
 1778         default:
 1779                 KPRINT(PRINTPREFIX "%d: strange nego state %d\n", target, c->s[target]);
 1780                 c->s[target] = NeitherDone;
 1781                 /* fall through */
 1782         case NeitherDone:
 1783                 if ((c->capvalid & (1 << target)) == 0)
 1784                         break;
 1785                 target_expo = (c->cap[target] >> 5) & 3;
 1786                 my_expo = (c->v->feature & Wide) != 0;
 1787                 if (target_expo < my_expo)
 1788                         my_expo = target_expo;
 1789 #ifdef ALWAYS_DO_WDTR
 1790                 bc += buildwdtrmsg(d->msg_out + bc, my_expo);
 1791                 KPRINT(PRINTPREFIX "%d: WDTN: initiating expo %d\n", target, my_expo);
 1792                 c->s[target] = WideInit;
 1793                 break;
 1794 #else
 1795                 if (my_expo) {
 1796                         bc += buildwdtrmsg(d->msg_out + bc, (c->v->feature & Wide) ? 1 : 0);
 1797                         KPRINT(PRINTPREFIX "%d: WDTN: initiating expo %d\n", target, my_expo);
 1798                         c->s[target] = WideInit;
 1799                         break;
 1800                 }
 1801                 KPRINT(PRINTPREFIX "%d: WDTN: narrow\n", target);
 1802                 /* fall through */
 1803 #endif
 1804         case WideDone:
 1805                 if (c->cap[target] & (1 << 4)) {
 1806                         KPRINT(PRINTPREFIX "%d: SDTN: initiating %d %d\n", target, c->tpf, c->v->maxsyncoff);
 1807                         bc += buildsdtrmsg(d->msg_out + bc, c->tpf, c->v->maxsyncoff);
 1808                         c->s[target] = SyncInit;
 1809                         break;
 1810                 }
 1811                 KPRINT(PRINTPREFIX "%d: SDTN: async only\n", target);
 1812                 c->s[target] = BothDone;
 1813                 break;
 1814 
 1815         case BothDone:
 1816                 break;
 1817         }
 1818 
 1819         setmovedata(&d->msg_out_buf, DMASEG(d->msg_out), bc);
 1820         setmovedata(&d->cmd_buf, DMASEG(r->cmd), r->clen);
 1821         calcblockdma(d, r->data ? DMASEG(r->data) : 0, r->dlen);
 1822 
 1823         if (DEBUG(0)) {
 1824                 KPRINT(PRINTPREFIX "%d/%d: exec: ", target, r->lun);
 1825                 for (bp = r->cmd; bp < &r->cmd[r->clen]; bp++) {
 1826                         KPRINT("%.2ux", *bp);
 1827                 }
 1828                 KPRINT("\n");
 1829                 if (!r->write) {
 1830                         KPRINT(PRINTPREFIX "%d/%d: exec: limit=(%d)%ld\n",
 1831                           target, r->lun, d->dmablks, legetl(d->data_buf.dbc));
 1832                 }
 1833                 else
 1834                         dumpwritedata(r->data, r->dlen);
 1835         }
 1836 
 1837         setmovedata(&d->status_buf, DMASEG(&d->status), 1);     
 1838 
 1839         d->p9status = SDnostatus;
 1840         d->parityerror = 0;
 1841         coherence();
 1842         d->stateb = A_STATE_ISSUE;              /* start operation */
 1843         coherence();
 1844 
 1845         ilock(c);
 1846         if (c->ssm)
 1847                 c->n->dcntl |= 0x10;            /* single step */
 1848         if (c->running) {
 1849                 c->n->istat = Sigp;
 1850         }
 1851         else {
 1852                 start(c, E_issue_check);
 1853         }
 1854         iunlock(c);
 1855 
 1856         while(waserror())
 1857                 ;
 1858         tsleep(d, done, d, 600 * 1000);
 1859         poperror();
 1860 
 1861         if (!done(d)) {
 1862                 KPRINT(PRINTPREFIX "%d/%d: exec: Timed out\n", target, r->lun);
 1863                 dumpncrregs(c, 0);
 1864                 dsafree(c, d);
 1865                 reset(c);
 1866                 qunlock(&c->q[target]);
 1867                 r->status = SDtimeout;
 1868                 return r->status = SDtimeout;   /* assign */
 1869         }
 1870 
 1871         if((status = d->p9status) == SDeio)
 1872                 c->s[target] = NeitherDone;
 1873         if (d->parityerror) {
 1874                 status = SDeio;
 1875         }
 1876 
 1877         /*
 1878          * adjust datalen
 1879          */
 1880         r->rlen = r->dlen;
 1881         if (DEBUG(0)) {
 1882                 KPRINT(PRINTPREFIX "%d/%d: exec: before rlen adjust: dmablks %d flag %d dbc %lud\n",
 1883                     target, r->lun, d->dmablks, d->flag, legetl(d->data_buf.dbc));
 1884         }
 1885         r->rlen = r->dlen;
 1886         if (d->flag != 2) {
 1887                 r->rlen -= d->dmablks * A_BSIZE;
 1888                 r->rlen -= legetl(d->data_buf.dbc);
 1889         }
 1890         if(!r->write)
 1891                 dumpreaddata(r->data, r->rlen);
 1892         if (DEBUG(0)) {
 1893                 KPRINT(PRINTPREFIX "%d/%d: exec: p9status=%d status %d rlen %ld\n",
 1894                     target, r->lun, d->p9status, status, r->rlen);
 1895         }
 1896         /*
 1897          * spot the identify
 1898          */
 1899         if ((c->capvalid & (1 << target)) == 0
 1900          && (status == SDok || status == SDcheck)
 1901          && r->cmd[0] == 0x12 && r->dlen >= 8) {
 1902                 c->capvalid |= 1 << target;
 1903                 bp = r->data;
 1904                 c->cap[target] = bp[7];
 1905                 KPRINT(PRINTPREFIX "%d: capabilities %.2x\n", target, bp[7]);
 1906         }
 1907         if(!check && status == SDcheck && !(r->flags & SDnosense)){
 1908                 check = 1;
 1909                 r->write = 0;
 1910                 memset(r->cmd, 0, sizeof(r->cmd));
 1911                 r->cmd[0] = 0x03;
 1912                 r->cmd[1] = r->lun<<5;
 1913                 r->cmd[4] = sizeof(r->sense)-1;
 1914                 r->clen = 6;
 1915                 r->data = r->sense;
 1916                 r->dlen = sizeof(r->sense)-1;
 1917                 /*
 1918                  * Clear out the microcode state
 1919                  * so the Dsa can be re-used.
 1920                  */
 1921                 lesetl(&d->stateb, A_STATE_ALLOCATED);
 1922                 coherence();
 1923                 goto docheck;
 1924         }
 1925         qunlock(&c->q[target]);
 1926         dsafree(c, d);
 1927 
 1928         if(status == SDok && check){
 1929                 status = SDcheck;
 1930                 r->flags |= SDvalidsense;
 1931         }
 1932         if(DEBUG(0))
 1933                 KPRINT(PRINTPREFIX "%d: r flags %8.8uX status %d rlen %ld\n",
 1934                         target, r->flags, status, r->rlen);
 1935         if(r->flags & SDvalidsense){
 1936                 if(!DEBUG(0))
 1937                         KPRINT(PRINTPREFIX "%d: r flags %8.8uX status %d rlen %ld\n",
 1938                                 target, r->flags, status, r->rlen);
 1939                 for(i = 0; i < r->rlen; i++)
 1940                         KPRINT(" %2.2uX", r->sense[i]);
 1941                 KPRINT("\n");
 1942         }
 1943         return r->status = status;
 1944 }
 1945 
 1946 static void
 1947 cribbios(Controller *c)
 1948 {
 1949         c->bios.scntl3 = c->n->scntl3;
 1950         c->bios.stest2 = c->n->stest2;
 1951         print(PRINTPREFIX "%s: bios scntl3(%.2x) stest2(%.2x)\n",
 1952                 c->sdev->name, c->bios.scntl3, c->bios.stest2);
 1953 }
 1954 
 1955 static int
 1956 bios_set_differential(Controller *c)
 1957 {
 1958         /* Concept lifted from FreeBSD - thanks Gerard */
 1959         /* basically, if clock conversion factors are set, then there is
 1960          * evidence the bios had a go at the chip, and if so, it would
 1961          * have set the differential enable bit in stest2
 1962          */
 1963         return (c->bios.scntl3 & 7) != 0 && (c->bios.stest2 & 0x20) != 0;
 1964 }
 1965 
 1966 #define NCR_VID         0x1000
 1967 #define NCR_810_DID     0x0001
 1968 #define NCR_820_DID     0x0002  /* don't know enough about this one to support it */
 1969 #define NCR_825_DID     0x0003
 1970 #define NCR_815_DID     0x0004
 1971 #define SYM_810AP_DID   0x0005
 1972 #define SYM_860_DID     0x0006
 1973 #define SYM_896_DID     0x000b
 1974 #define SYM_895_DID     0x000c
 1975 #define SYM_885_DID     0x000d  /* ditto */
 1976 #define SYM_875_DID     0x000f  /* ditto */
 1977 #define SYM_1010_DID    0x0020
 1978 #define SYM_1011_DID    0x0021
 1979 #define SYM_875J_DID    0x008f
 1980 
 1981 static Variant variant[] = {
 1982 { NCR_810_DID,   0x0f, "NCR53C810",     Burst16,   8, 24, 0 },
 1983 { NCR_810_DID,   0x1f, "SYM53C810ALV",  Burst16,   8, 24, Prefetch },
 1984 { NCR_810_DID,   0xff, "SYM53C810A",    Burst16,   8, 24, Prefetch },
 1985 { SYM_810AP_DID, 0xff, "SYM53C810AP",   Burst16,   8, 24, Prefetch },
 1986 { NCR_815_DID,   0xff, "NCR53C815",     Burst16,   8, 24, BurstOpCodeFetch },
 1987 { NCR_825_DID,   0x0f, "NCR53C825",     Burst16,   8, 24, Wide|BurstOpCodeFetch|Differential },
 1988 { NCR_825_DID,   0xff, "SYM53C825A",    Burst128, 16, 24, Prefetch|LocalRAM|BigFifo|Differential|Wide },
 1989 { SYM_860_DID,   0x0f, "SYM53C860",     Burst16,   8, 24, Prefetch|Ultra },
 1990 { SYM_860_DID,   0xff, "SYM53C860LV",   Burst16,   8, 24, Prefetch|Ultra },
 1991 { SYM_875_DID,   0x01, "SYM53C875r1",   Burst128, 16, 24, Prefetch|LocalRAM|BigFifo|Differential|Wide|Ultra },
 1992 { SYM_875_DID,   0xff, "SYM53C875",     Burst128, 16, 24, Prefetch|LocalRAM|BigFifo|Differential|Wide|Ultra|ClockDouble },
 1993 { SYM_875J_DID,   0xff, "SYM53C875j",   Burst128, 16, 24, Prefetch|LocalRAM|BigFifo|Differential|Wide|Ultra|ClockDouble },
 1994 { SYM_885_DID,   0xff, "SYM53C885",     Burst128, 16, 24, Prefetch|LocalRAM|BigFifo|Wide|Ultra|ClockDouble },
 1995 { SYM_895_DID,   0xff, "SYM53C895",     Burst128, 16, 24, Prefetch|LocalRAM|BigFifo|Wide|Ultra|Ultra2 },
 1996 { SYM_896_DID,   0xff, "SYM53C896",     Burst128, 16, 64, Prefetch|LocalRAM|BigFifo|Wide|Ultra|Ultra2 },
 1997 { SYM_1010_DID,  0xff, "SYM53C1010",    Burst128, 16, 64, Prefetch|LocalRAM|BigFifo|Wide|Ultra|Ultra2 },
 1998 { SYM_1011_DID,   0xff, "SYM53C1010",   Burst128, 16, 64, Prefetch|LocalRAM|BigFifo|Wide|Ultra|Ultra2 },
 1999 };
 2000 
 2001 static int
 2002 xfunc(Controller *c, enum na_external x, unsigned long *v)
 2003 {
 2004         switch (x) {
 2005         default:
 2006                 print("xfunc: can't find external %d\n", x);
 2007                 return 0;
 2008         case X_scsi_id_buf:
 2009                 *v = offsetof(Dsa, scsi_id_buf[0]);
 2010                 break;
 2011         case X_msg_out_buf:
 2012                 *v = offsetof(Dsa, msg_out_buf);
 2013                 break;
 2014         case X_cmd_buf:
 2015                 *v = offsetof(Dsa, cmd_buf);
 2016                 break;
 2017         case X_data_buf:
 2018                 *v = offsetof(Dsa, data_buf);
 2019                 break;
 2020         case X_status_buf:
 2021                 *v = offsetof(Dsa, status_buf);
 2022                 break;
 2023         case X_dsa_head:
 2024                 *v = DMASEG(&c->dsalist.head[0]);
 2025                 break;
 2026         case X_ssid_mask:
 2027                 *v = SSIDMASK(c);
 2028                 break;
 2029         }
 2030         return 1;
 2031 }
 2032 
 2033 static int
 2034 na_fixup(Controller *c, ulong pa_reg,
 2035     struct na_patch *patch, int patches,
 2036     int (*externval)(Controller*, int, ulong*))
 2037 {
 2038         int p;
 2039         int v;
 2040         ulong *script, pa_script;
 2041         unsigned long lw, lv;
 2042 
 2043         script = c->script;
 2044         pa_script = c->scriptpa;
 2045         for (p = 0; p < patches; p++) {
 2046                 switch (patch[p].type) {
 2047                 case 1:
 2048                         /* script relative */
 2049                         script[patch[p].lwoff] += pa_script;
 2050                         break;
 2051                 case 2:
 2052                         /* register i/o relative */
 2053                         script[patch[p].lwoff] += pa_reg;
 2054                         break;
 2055                 case 3:
 2056                         /* data external */
 2057                         lw = script[patch[p].lwoff];
 2058                         v = (lw >> 8) & 0xff;
 2059                         if (!(*externval)(c, v, &lv))
 2060                                 return 0;
 2061                         v = lv & 0xff;
 2062                         script[patch[p].lwoff] = (lw & 0xffff00ffL) | (v << 8);
 2063                         break;
 2064                 case 4:
 2065                         /* 32 bit external */
 2066                         lw = script[patch[p].lwoff];
 2067                         if (!(*externval)(c, lw, &lv))
 2068                                 return 0;
 2069                         script[patch[p].lwoff] = lv;
 2070                         break;
 2071                 case 5:
 2072                         /* 24 bit external */
 2073                         lw = script[patch[p].lwoff];
 2074                         if (!(*externval)(c, lw & 0xffffff, &lv))
 2075                                 return 0;
 2076                         script[patch[p].lwoff] = (lw & 0xff000000L) | (lv & 0xffffffL);
 2077                         break;
 2078                 }
 2079         }
 2080         return 1;
 2081 }
 2082 
 2083 static SDev*
 2084 sd53c8xxpnp(void)
 2085 {
 2086         char *cp;
 2087         Pcidev *p;
 2088         Variant *v;
 2089         int ba, nctlr;
 2090         void *scriptma;
 2091         Controller *ctlr;
 2092         SDev *sdev, *head, *tail;
 2093         ulong regpa, *script, scriptpa;
 2094         void *regva, *scriptva;
 2095 
 2096         if(cp = getconf("*maxsd53c8xx"))
 2097                 nctlr = strtoul(cp, 0, 0);
 2098         else
 2099                 nctlr = 32;
 2100 
 2101         p = nil;
 2102         head = tail = nil;
 2103         while((p = pcimatch(p, NCR_VID, 0)) != nil && nctlr > 0){
 2104                 for(v = variant; v < &variant[nelem(variant)]; v++){
 2105                         if(p->did == v->did && p->rid <= v->maxrid)
 2106                                 break;
 2107                 }
 2108                 if(v >= &variant[nelem(variant)]) {
 2109                         print("no match\n");
 2110                         continue;
 2111                 }
 2112                 print(PRINTPREFIX "%s rev. 0x%2.2x intr=%d command=%4.4uX\n",
 2113                         v->name, p->rid, p->intl, p->pcr);
 2114 
 2115                 regpa = p->mem[1].bar;
 2116                 ba = 2;
 2117                 if(regpa & 0x04){
 2118                         if(p->mem[2].bar)
 2119                                 continue;
 2120                         ba++;
 2121                 }
 2122                 if(regpa == 0)
 2123                         print("regpa 0\n");
 2124                 regpa &= ~0xF;
 2125                 regva = vmap(regpa, p->mem[1].size);
 2126                 if(regva == 0)
 2127                         continue;
 2128 
 2129                 script = nil;
 2130                 scriptpa = 0;
 2131                 scriptva = nil;
 2132                 scriptma = nil;
 2133                 if((v->feature & LocalRAM) && sizeof(na_script) <= 4096){
 2134                         scriptpa = p->mem[ba].bar;
 2135                         if((scriptpa & 0x04) && p->mem[ba+1].bar){
 2136                                 vunmap(regva, p->mem[1].size);
 2137                                 continue;
 2138                         }
 2139                         scriptpa &= ~0x0F;
 2140                         scriptva = vmap(scriptpa, p->mem[ba].size);
 2141                         if(scriptva)
 2142                                 script = scriptva;
 2143                 }
 2144                 if(scriptpa == 0){
 2145                         /*
 2146                          * Either the map failed, or this chip does not have
 2147                          * local RAM. It will need a copy of the microcode.
 2148                          */
 2149                         scriptma = malloc(sizeof(na_script));
 2150                         if(scriptma == nil){
 2151                                 vunmap(regva, p->mem[1].size);
 2152                                 continue;
 2153                         }
 2154                         scriptpa = DMASEG(scriptma);
 2155                         script = scriptma;
 2156                 }
 2157 
 2158                 ctlr = malloc(sizeof(Controller));
 2159                 sdev = malloc(sizeof(SDev));
 2160                 if(ctlr == nil || sdev == nil){
 2161 buggery:
 2162                         if(ctlr)
 2163                                 free(ctlr);
 2164                         if(sdev)
 2165                                 free(sdev);
 2166                         if(scriptma)
 2167                                 free(scriptma);
 2168                         else if(scriptva)
 2169                                 vunmap(scriptva, p->mem[ba].size);
 2170                         if(regva)
 2171                                 vunmap(regva, p->mem[1].size);
 2172                         continue;
 2173                 }
 2174 
 2175                 if(dsaend == nil)
 2176                         dsaend = xalloc(sizeof *dsaend);
 2177                 if(dsaend == nil)
 2178                         panic("sd53c8xxpnp: no memory");
 2179                 lesetl(&dsaend->stateb, A_STATE_END);
 2180         //      lesetl(dsaend->next, DMASEG(dsaend));
 2181                 coherence();
 2182                 lesetl(ctlr->dsalist.head, DMASEG(dsaend));
 2183                 coherence();
 2184                 ctlr->dsalist.freechain = 0;
 2185 
 2186                 ctlr->n = regva;
 2187                 ctlr->v = v;
 2188                 ctlr->script = script;
 2189                 memmove(ctlr->script, na_script, sizeof(na_script));
 2190 
 2191                 /*
 2192                  * Because we don't yet have an abstraction for the
 2193                  * addresses as seen from the controller side (and on
 2194                  * the 386 it doesn't matter), the following two lines
 2195                  * are different between the 386 and alpha copies of
 2196                  * this driver.
 2197                  */
 2198                 ctlr->scriptpa = scriptpa;
 2199                 if(!na_fixup(ctlr, regpa, na_patches, NA_PATCHES, xfunc)){
 2200                         print("script fixup failed\n");
 2201                         goto buggery;
 2202                 }
 2203                 swabl(ctlr->script, ctlr->script, sizeof(na_script));
 2204 
 2205                 ctlr->pcidev = p;
 2206 
 2207                 sdev->ifc = &sd53c8xxifc;
 2208                 sdev->ctlr = ctlr;
 2209                 sdev->idno = '';
 2210                 if(!(v->feature & Wide))
 2211                         sdev->nunit = 8;
 2212                 else
 2213                         sdev->nunit = MAXTARGET;
 2214                 ctlr->sdev = sdev;
 2215                 
 2216                 if(head != nil)
 2217                         tail->next = sdev;
 2218                 else
 2219                         head = sdev;
 2220                 tail = sdev;
 2221 
 2222                 nctlr--;
 2223         }
 2224 
 2225         return head;
 2226 }
 2227 
 2228 static int
 2229 sd53c8xxenable(SDev* sdev)
 2230 {
 2231         Pcidev *pcidev;
 2232         Controller *ctlr;
 2233         char name[32];
 2234 
 2235         ctlr = sdev->ctlr;
 2236         pcidev = ctlr->pcidev;
 2237 
 2238         pcisetbme(pcidev);
 2239 
 2240         ilock(ctlr);
 2241         synctabinit(ctlr);
 2242         cribbios(ctlr);
 2243         reset(ctlr);
 2244         snprint(name, sizeof(name), "%s (%s)", sdev->name, sdev->ifc->name);
 2245         intrenable(pcidev->intl, sd53c8xxinterrupt, ctlr, pcidev->tbdf, name);
 2246         iunlock(ctlr);
 2247 
 2248         return 1;
 2249 }
 2250 
 2251 SDifc sd53c8xxifc = {
 2252         "53c8xx",                       /* name */
 2253 
 2254         sd53c8xxpnp,                    /* pnp */
 2255         nil,                            /* legacy */
 2256         sd53c8xxenable,                 /* enable */
 2257         nil,                            /* disable */
 2258 
 2259         scsiverify,                     /* verify */
 2260         scsionline,                     /* online */
 2261         sd53c8xxrio,                    /* rio */
 2262         nil,                            /* rctl */
 2263         nil,                            /* wctl */
 2264 
 2265         scsibio,                        /* bio */
 2266         nil,                            /* probe */
 2267         nil,                            /* clear */
 2268         nil,                            /* rtopctl */
 2269         nil,                            /* wtopctl */
 2270 };

Cache object: 7dd519662851aef69101907441178661


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