Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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FreeBSD/Linux Kernel Cross Reference
sys/pc/usbehci.h
Version:
- FREEBSD - FREEBSD-13-STABLE - FREEBSD-13-0 - FREEBSD-12-STABLE - FREEBSD-12-0 - FREEBSD-11-STABLE - FREEBSD-11-0 - FREEBSD-10-STABLE - FREEBSD-10-0 - FREEBSD-9-STABLE - FREEBSD-9-0 - FREEBSD-8-STABLE - FREEBSD-8-0 - FREEBSD-7-STABLE - FREEBSD-7-0 - FREEBSD-6-STABLE - FREEBSD-6-0 - FREEBSD-5-STABLE - FREEBSD-5-0 - FREEBSD-4-STABLE - FREEBSD-3-STABLE - FREEBSD22 - l41 - OPENBSD - linux-2.6 - MK84 - PLAN9 - xnu-8792
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1 typedef struct Ecapio Ecapio; 2 typedef struct Eopio Eopio; 3 typedef struct Edbgio Edbgio; 4 5 /* 6 * EHCI interface registers and bits 7 */ 8 enum 9 { 10 Cnports = 0xF, /* nport bits in Ecapio parms. */ 11 Cdbgportshift = 20,, /* debug port in Ecapio parms. */ 12 Cdbgportmask = 0xF, 13 C64 = 1, /* 64-bits, in Ecapio capparms. */ 14 15 /* typed links */ 16 Lterm = 1, 17 Litd = 0<<1, 18 Lqh = 1<<1, 19 Lsitd = 2<<1, 20 Lfstn = 3<<1, /* we don't use these */ 21 22 /* Cmd reg. */ 23 Cstop = 0x00000, /* stop running */ 24 Crun = 0x00001, /* start operation */ 25 Chcreset = 0x00002, /* host controller reset */ 26 Cflsmask = 0x0000C, /* frame list size bits */ 27 Cfls1024 = 0x00000, /* frame list size 1024 */ 28 Cfls512 = 0x00004, /* frame list size 512 frames */ 29 Cfls256 = 0x00008, /* frame list size 256 frames */ 30 Cpse = 0x00010, /* periodic sched. enable */ 31 Case = 0x00020, /* async sched. enable */ 32 Ciasync = 0x00040, /* interrupt on async advance doorbell */ 33 Citc1 = 0x10000, /* interrupt threshold ctl. 1 µframe */ 34 Citc4 = 0x40000, /* same. 2 µframes */ 35 /* ... */ 36 Citc8 = 0x80000, /* same. 8 µframes (can go up to 64) */ 37 38 /* Sts reg. */ 39 Sasyncss = 0x08000, /* aync schedule status */ 40 Speriodss = 0x04000, /* periodic schedule status */ 41 Srecl = 0x02000, /* reclamnation (empty async sched.) */ 42 Shalted = 0x01000, /* h.c. is halted */ 43 Sasync = 0x00020, /* interrupt on async advance */ 44 Sherr = 0x00010, /* host system error */ 45 Sfrroll = 0x00008, /* frame list roll over */ 46 Sportchg = 0x00004, /* port change detect */ 47 Serrintr = 0x00002, /* error interrupt */ 48 Sintr = 0x00001, /* interrupt */ 49 Sintrs = 0x0003F, /* interrupts status */ 50 51 /* Intr reg. */ 52 Iusb = 0x01, /* intr. on usb */ 53 Ierr = 0x02, /* intr. on usb error */ 54 Iportchg = 0x04, /* intr. on port change */ 55 Ifrroll = 0x08, /* intr. on frlist roll over */ 56 Ihcerr = 0x10, /* intr. on host error */ 57 Iasync = 0x20, /* intr. on async advance enable */ 58 Iall = 0x3F, /* all interrupts */ 59 60 /* Config reg. */ 61 Callmine = 1, /* route all ports to us */ 62 63 /* Portsc reg. */ 64 Pspresent = 0x00000001, /* device present */ 65 Psstatuschg = 0x00000002, /* Pspresent changed */ 66 Psenable = 0x00000004, /* device enabled */ 67 Pschange = 0x00000008, /* Psenable changed */ 68 Psresume = 0x00000040, /* resume detected */ 69 Pssuspend = 0x00000080, /* port suspended */ 70 Psreset = 0x00000100, /* port reset */ 71 Pspower = 0x00001000, /* port power on */ 72 Psowner = 0x00002000, /* port owned by companion */ 73 Pslinemask = 0x00000C00, /* line status bits */ 74 Pslow = 0x00000400, /* low speed device */ 75 76 /* Debug port csw reg. */ 77 Cowner = 0x40000000, /* port owned by ehci */ 78 Cenable = 0x20000000, /* debug port enabled */ 79 Cdone = 0x00010000, /* request is done */ 80 Cbusy = 0x00000400, /* port in use by a driver */ 81 Cerrmask= 0x00000380, /* error code bits */ 82 Chwerr = 0x00000100, /* hardware error */ 83 Cterr = 0x00000080, /* transaction error */ 84 Cfailed = 0x00000040, /* transaction did fail */ 85 Cgo = 0x00000020, /* execute the transaction */ 86 Cwrite = 0x00000010, /* request is a write */ 87 Clen = 0x0000000F, /* data len */ 88 89 /* Debug port pid reg. */ 90 Prpidshift = 16, /* received pid */ 91 Prpidmask = 0xFF, 92 Pspidshift = 8, /* sent pid */ 93 Pspidmask = 0xFF, 94 Ptokshift = 0, /* token pid */ 95 Ptokmask = 0xFF, 96 97 Ptoggle = 0x00008800, /* to update toggles */ 98 Ptogglemask = 0x00FFFF00, 99 100 /* Debug port addr reg. */ 101 Adevshift = 8, /* device address */ 102 Adevmask = 0x7F, 103 Aepshift = 0, /* endpoint number */ 104 Aepmask = 0xF, 105 }; 106 107 /* 108 * Capability registers (hw) 109 */ 110 struct Ecapio 111 { 112 ulong cap; /* 00 controller capability register */ 113 ulong parms; /* 04 structural parameters register */ 114 ulong capparms; /* 08 capability parameters */ 115 ulong portroute; /* 0c not on the CS5536 */ 116 }; 117 118 /* 119 * Operational registers (hw) 120 */ 121 struct Eopio 122 { 123 ulong cmd; /* 00 command */ 124 ulong sts; /* 04 status */ 125 ulong intr; /* 08 interrupt enable */ 126 ulong frno; /* 0c frame index */ 127 ulong seg; /* 10 bits 63:32 of EHCI datastructs (unused) */ 128 ulong frbase; /* 14 frame list base addr, 4096-byte boundary */ 129 ulong link; /* 18 link for async list */ 130 uchar d2c[0x40-0x1c]; /* 1c dummy */ 131 ulong config; /* 40 1: all ports default-routed to this HC */ 132 ulong portsc[1]; /* 44 Port status and control, one per port */ 133 }; 134 135 /* 136 * Debug port registers (hw) 137 */ 138 struct Edbgio 139 { 140 ulong csw; /* control and status */ 141 ulong pid; /* USB pid */ 142 uchar data[8]; /* data buffer */ 143 ulong addr; /* device and endpoint addresses */ 144 }; 145
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