Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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FreeBSD/Linux Kernel Cross Reference
sys/pc98/cbus/sio.c
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1 /*- 2 * Copyright (c) 1991 The Regents of the University of California. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 4. Neither the name of the University nor the names of its contributors 14 * may be used to endorse or promote products derived from this software 15 * without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 * 29 * $FreeBSD$ 30 * from: @(#)com.c 7.5 (Berkeley) 5/16/91 31 * from: i386/isa sio.c,v 1.234 32 */ 33 34 #include "opt_comconsole.h" 35 #include "opt_compat.h" 36 #include "opt_gdb.h" 37 #include "opt_kdb.h" 38 #include "opt_sio.h" 39 40 /* 41 * Serial driver, based on 386BSD-0.1 com driver. 42 * Mostly rewritten to use pseudo-DMA. 43 * Works for National Semiconductor NS8250-NS16550AF UARTs. 44 * COM driver, based on HP dca driver. 45 * 46 * Changes for PC Card integration: 47 * - Added PC Card driver table and handlers 48 */ 49 /*=============================================================== 50 * 386BSD(98),FreeBSD-1.1x(98) com driver. 51 * ----- 52 * modified for PC9801 by M.Ishii 53 * Kyoto University Microcomputer Club (KMC) 54 * Chou "TEFUTEFU" Hirotomi 55 * Kyoto Univ. the faculty of medicine 56 *=============================================================== 57 * FreeBSD-2.0.1(98) sio driver. 58 * ----- 59 * modified for pc98 Internal i8251 and MICRO CORE MC16550II 60 * T.Koike(hfc01340@niftyserve.or.jp) 61 * implement kernel device configuration 62 * aizu@orient.center.nitech.ac.jp 63 * 64 * Notes. 65 * ----- 66 * PC98 localization based on 386BSD(98) com driver. Using its PC98 local 67 * functions. 68 * This driver is under debugging,has bugs. 69 */ 70 /* 71 * modified for AIWA B98-01 72 * by T.Hatanou <hatanou@yasuda.comm.waseda.ac.jp> last update: 15 Sep.1995 73 */ 74 /* 75 * Modified by Y.Takahashi of Kogakuin University. 76 */ 77 /* 78 * modified for 8251(FIFO) by Seigo TANIMURA <tanimura@FreeBSD.org> 79 */ 80 81 #include <sys/param.h> 82 #include <sys/systm.h> 83 #include <sys/bus.h> 84 #include <sys/conf.h> 85 #include <sys/fcntl.h> 86 #include <sys/interrupt.h> 87 #include <sys/kdb.h> 88 #include <sys/kernel.h> 89 #include <sys/limits.h> 90 #include <sys/lock.h> 91 #include <sys/malloc.h> 92 #include <sys/module.h> 93 #include <sys/mutex.h> 94 #include <sys/proc.h> 95 #include <sys/reboot.h> 96 #include <sys/serial.h> 97 #include <sys/sysctl.h> 98 #include <sys/syslog.h> 99 #include <sys/tty.h> 100 #include <machine/bus.h> 101 #include <sys/rman.h> 102 #include <sys/timepps.h> 103 #include <sys/uio.h> 104 #include <sys/cons.h> 105 106 #include <isa/isavar.h> 107 108 #include <machine/resource.h> 109 110 #include <dev/sio/sioreg.h> 111 #include <dev/sio/siovar.h> 112 113 #ifdef PC98 114 #include <pc98/cbus/cbus.h> 115 #include <pc98/pc98/pc98_machdep.h> 116 #endif 117 118 #ifdef COM_ESP 119 #include <dev/ic/esp.h> 120 #endif 121 #include <dev/ic/ns16550.h> 122 #ifdef PC98 123 #include <dev/ic/i8251.h> 124 #include <dev/ic/rsa.h> 125 #endif 126 127 #define LOTS_OF_EVENTS 64 /* helps separate urgent events from input */ 128 129 /* 130 * Meaning of flags: 131 * 132 * 0x00000001 shared IRQs 133 * 0x00000002 disable FIFO 134 * 0x00000008 recover sooner from lost output interrupts 135 * 0x00000010 device is potential system console 136 * 0x00000020 device is forced to become system console 137 * 0x00000040 device is reserved for low-level IO 138 * 0x00000080 use this port for remote kernel debugging 139 * 0x0000??00 minor number of master port 140 * 0x00010000 PPS timestamping on CTS instead of DCD 141 * 0x00080000 IIR_TXRDY bug 142 * 0x00400000 If no comconsole found then mark as a comconsole 143 * 0x1?000000 interface type 144 */ 145 146 #ifdef COM_MULTIPORT 147 /* checks in flags for multiport and which is multiport "master chip" 148 * for a given card 149 */ 150 #define COM_ISMULTIPORT(flags) ((flags) & 0x01) 151 #define COM_MPMASTER(flags) (((flags) >> 8) & 0x0ff) 152 #ifndef PC98 153 #define COM_NOTAST4(flags) ((flags) & 0x04) 154 #endif 155 #else 156 #define COM_ISMULTIPORT(flags) (0) 157 #endif /* COM_MULTIPORT */ 158 159 #define COM_C_IIR_TXRDYBUG 0x80000 160 #define COM_CONSOLE(flags) ((flags) & 0x10) 161 #define COM_DEBUGGER(flags) ((flags) & 0x80) 162 #ifndef PC98 163 #define COM_FIFOSIZE(flags) (((flags) & 0xff000000) >> 24) 164 #endif 165 #define COM_FORCECONSOLE(flags) ((flags) & 0x20) 166 #define COM_IIR_TXRDYBUG(flags) ((flags) & COM_C_IIR_TXRDYBUG) 167 #define COM_LLCONSOLE(flags) ((flags) & 0x40) 168 #define COM_LOSESOUTINTS(flags) ((flags) & 0x08) 169 #define COM_NOFIFO(flags) ((flags) & 0x02) 170 #ifndef PC98 171 #define COM_NOSCR(flags) ((flags) & 0x100000) 172 #endif 173 #define COM_PPSCTS(flags) ((flags) & 0x10000) 174 #ifndef PC98 175 #define COM_ST16650A(flags) ((flags) & 0x20000) 176 #define COM_TI16754(flags) ((flags) & 0x200000) 177 #endif 178 179 #define sio_getreg(com, off) \ 180 (bus_space_read_1((com)->bst, (com)->bsh, (off))) 181 #define sio_setreg(com, off, value) \ 182 (bus_space_write_1((com)->bst, (com)->bsh, (off), (value))) 183 184 /* 185 * com state bits. 186 * (CS_BUSY | CS_TTGO) and (CS_BUSY | CS_TTGO | CS_ODEVREADY) must be higher 187 * than the other bits so that they can be tested as a group without masking 188 * off the low bits. 189 * 190 * The following com and tty flags correspond closely: 191 * CS_BUSY = TS_BUSY (maintained by comstart(), siopoll() and 192 * comstop()) 193 * CS_TTGO = ~TS_TTSTOP (maintained by comparam() and comstart()) 194 * CS_CTS_OFLOW = CCTS_OFLOW (maintained by comparam()) 195 * CS_RTS_IFLOW = CRTS_IFLOW (maintained by comparam()) 196 * TS_FLUSH is not used. 197 * XXX I think TIOCSETA doesn't clear TS_TTSTOP when it clears IXON. 198 * XXX CS_*FLOW should be CF_*FLOW in com->flags (control flags not state). 199 */ 200 #define CS_BUSY 0x80 /* output in progress */ 201 #define CS_TTGO 0x40 /* output not stopped by XOFF */ 202 #define CS_ODEVREADY 0x20 /* external device h/w ready (CTS) */ 203 #define CS_CHECKMSR 1 /* check of MSR scheduled */ 204 #define CS_CTS_OFLOW 2 /* use CTS output flow control */ 205 #define CS_ODONE 4 /* output completed */ 206 #define CS_RTS_IFLOW 8 /* use RTS input flow control */ 207 #define CSE_BUSYCHECK 1 /* siobusycheck() scheduled */ 208 209 static char const * const error_desc[] = { 210 #define CE_OVERRUN 0 211 "silo overflow", 212 #define CE_INTERRUPT_BUF_OVERFLOW 1 213 "interrupt-level buffer overflow", 214 #define CE_TTY_BUF_OVERFLOW 2 215 "tty-level buffer overflow", 216 }; 217 218 #define CE_NTYPES 3 219 #define CE_RECORD(com, errnum) (++(com)->delta_error_counts[errnum]) 220 221 /* types. XXX - should be elsewhere */ 222 typedef u_int Port_t; /* hardware port */ 223 typedef u_char bool_t; /* boolean */ 224 225 /* queue of linear buffers */ 226 struct lbq { 227 u_char *l_head; /* next char to process */ 228 u_char *l_tail; /* one past the last char to process */ 229 struct lbq *l_next; /* next in queue */ 230 bool_t l_queued; /* nonzero if queued */ 231 }; 232 233 /* com device structure */ 234 struct com_s { 235 u_char state; /* miscellaneous flag bits */ 236 u_char cfcr_image; /* copy of value written to CFCR */ 237 #ifdef COM_ESP 238 bool_t esp; /* is this unit a hayes esp board? */ 239 #endif 240 u_char extra_state; /* more flag bits, separate for order trick */ 241 u_char fifo_image; /* copy of value written to FIFO */ 242 bool_t hasfifo; /* nonzero for 16550 UARTs */ 243 bool_t loses_outints; /* nonzero if device loses output interrupts */ 244 u_char mcr_image; /* copy of value written to MCR */ 245 #ifdef COM_MULTIPORT 246 bool_t multiport; /* is this unit part of a multiport device? */ 247 #endif /* COM_MULTIPORT */ 248 bool_t no_irq; /* nonzero if irq is not attached */ 249 bool_t gone; /* hardware disappeared */ 250 bool_t poll; /* nonzero if polling is required */ 251 bool_t poll_output; /* nonzero if polling for output is required */ 252 bool_t st16650a; /* nonzero if Startech 16650A compatible */ 253 int unit; /* unit number */ 254 u_int flags; /* copy of device flags */ 255 u_int tx_fifo_size; 256 257 /* 258 * The high level of the driver never reads status registers directly 259 * because there would be too many side effects to handle conveniently. 260 * Instead, it reads copies of the registers stored here by the 261 * interrupt handler. 262 */ 263 u_char last_modem_status; /* last MSR read by intr handler */ 264 u_char prev_modem_status; /* last MSR handled by high level */ 265 266 u_char *ibuf; /* start of input buffer */ 267 u_char *ibufend; /* end of input buffer */ 268 u_char *ibufold; /* old input buffer, to be freed */ 269 u_char *ihighwater; /* threshold in input buffer */ 270 u_char *iptr; /* next free spot in input buffer */ 271 int ibufsize; /* size of ibuf (not include error bytes) */ 272 int ierroff; /* offset of error bytes in ibuf */ 273 274 struct lbq obufq; /* head of queue of output buffers */ 275 struct lbq obufs[2]; /* output buffers */ 276 277 bus_space_tag_t bst; 278 bus_space_handle_t bsh; 279 280 #ifdef PC98 281 Port_t cmd_port; 282 Port_t sts_port; 283 Port_t in_modem_port; 284 Port_t intr_ctrl_port; 285 Port_t rsabase; /* Iobase address of an I/O-DATA RSA board. */ 286 int intr_enable; 287 int pc98_prev_modem_status; 288 int pc98_modem_delta; 289 int modem_car_chg_timer; 290 int pc98_prev_siocmd; 291 int pc98_prev_siomod; 292 int modem_checking; 293 int pc98_if_type; 294 295 bool_t pc98_8251fifo; 296 bool_t pc98_8251fifo_enable; 297 #endif /* PC98 */ 298 Port_t data_port; /* i/o ports */ 299 #ifdef COM_ESP 300 Port_t esp_port; 301 #endif 302 Port_t int_ctl_port; 303 Port_t int_id_port; 304 Port_t modem_ctl_port; 305 Port_t line_status_port; 306 Port_t modem_status_port; 307 308 struct tty *tp; /* cross reference */ 309 310 struct pps_state pps; 311 int pps_bit; 312 #ifdef ALT_BREAK_TO_DEBUGGER 313 int alt_brk_state; 314 #endif 315 316 u_long bytes_in; /* statistics */ 317 u_long bytes_out; 318 u_int delta_error_counts[CE_NTYPES]; 319 u_long error_counts[CE_NTYPES]; 320 321 u_long rclk; 322 323 struct resource *irqres; 324 struct resource *ioportres; 325 int ioportrid; 326 void *cookie; 327 328 /* 329 * Data area for output buffers. Someday we should build the output 330 * buffer queue without copying data. 331 */ 332 #ifdef PC98 333 int obufsize; 334 u_char *obuf1; 335 u_char *obuf2; 336 #else 337 u_char obuf1[256]; 338 u_char obuf2[256]; 339 #endif 340 }; 341 342 #ifdef COM_ESP 343 static int espattach(struct com_s *com, Port_t esp_port); 344 #endif 345 346 static void combreak(struct tty *tp, int sig); 347 static timeout_t siobusycheck; 348 static u_int siodivisor(u_long rclk, speed_t speed); 349 static void comclose(struct tty *tp); 350 static int comopen(struct tty *tp, struct cdev *dev); 351 static void sioinput(struct com_s *com); 352 static void siointr1(struct com_s *com); 353 static int siointr(void *arg); 354 static int commodem(struct tty *tp, int sigon, int sigoff); 355 static int comparam(struct tty *tp, struct termios *t); 356 static void siopoll(void *); 357 static void siosettimeout(void); 358 static int siosetwater(struct com_s *com, speed_t speed); 359 static void comstart(struct tty *tp); 360 static void comstop(struct tty *tp, int rw); 361 static timeout_t comwakeup; 362 363 char sio_driver_name[] = "sio"; 364 static struct mtx sio_lock; 365 static int sio_inited; 366 367 /* table and macro for fast conversion from a unit number to its com struct */ 368 devclass_t sio_devclass; 369 #define com_addr(unit) ((struct com_s *) \ 370 devclass_get_softc(sio_devclass, unit)) /* XXX */ 371 372 int comconsole = -1; 373 static volatile speed_t comdefaultrate = CONSPEED; 374 static u_long comdefaultrclk = DEFAULT_RCLK; 375 SYSCTL_ULONG(_machdep, OID_AUTO, conrclk, CTLFLAG_RW, &comdefaultrclk, 0, ""); 376 static speed_t gdbdefaultrate = GDBSPEED; 377 SYSCTL_UINT(_machdep, OID_AUTO, gdbspeed, CTLFLAG_RW, 378 &gdbdefaultrate, GDBSPEED, ""); 379 static u_int com_events; /* input chars + weighted output completions */ 380 static Port_t siocniobase; 381 static int siocnunit = -1; 382 static void *sio_slow_ih; 383 static void *sio_fast_ih; 384 static int sio_timeout; 385 static int sio_timeouts_until_log; 386 static struct callout_handle sio_timeout_handle 387 = CALLOUT_HANDLE_INITIALIZER(&sio_timeout_handle); 388 static int sio_numunits; 389 390 #ifdef PC98 391 struct siodev { 392 short if_type; 393 short irq; 394 Port_t cmd, sts, ctrl, mod; 395 }; 396 static int sysclock; 397 398 #define COM_INT_DISABLE {int previpri; previpri=spltty(); 399 #define COM_INT_ENABLE splx(previpri);} 400 #define IEN_TxFLAG IEN_Tx 401 402 #define COM_CARRIER_DETECT_EMULATE 0 403 #define PC98_CHECK_MODEM_INTERVAL (hz/10) 404 #define DCD_OFF_TOLERANCE 2 405 #define DCD_ON_RECOGNITION 2 406 #define IS_8251(if_type) (!(if_type & 0x10)) 407 #define COM1_EXT_CLOCK 0x40000 408 409 static void commint(struct cdev *dev); 410 static void com_tiocm_bis(struct com_s *com, int msr); 411 static void com_tiocm_bic(struct com_s *com, int msr); 412 static int com_tiocm_get(struct com_s *com); 413 static int com_tiocm_get_delta(struct com_s *com); 414 static void pc98_msrint_start(struct cdev *dev); 415 static void com_cflag_and_speed_set(struct com_s *com, int cflag, int speed); 416 static int pc98_ttspeedtab(struct com_s *com, int speed, u_int *divisor); 417 static int pc98_get_modem_status(struct com_s *com); 418 static timeout_t pc98_check_msr; 419 static void pc98_set_baud_rate(struct com_s *com, u_int count); 420 static void pc98_i8251_reset(struct com_s *com, int mode, int command); 421 static void pc98_disable_i8251_interrupt(struct com_s *com, int mod); 422 static void pc98_enable_i8251_interrupt(struct com_s *com, int mod); 423 static int pc98_check_i8251_interrupt(struct com_s *com); 424 static int pc98_i8251_get_cmd(struct com_s *com); 425 static int pc98_i8251_get_mod(struct com_s *com); 426 static void pc98_i8251_set_cmd(struct com_s *com, int x); 427 static void pc98_i8251_or_cmd(struct com_s *com, int x); 428 static void pc98_i8251_clear_cmd(struct com_s *com, int x); 429 static void pc98_i8251_clear_or_cmd(struct com_s *com, int clr, int x); 430 static int pc98_check_if_type(device_t dev, struct siodev *iod); 431 static int pc98_check_8251vfast(void); 432 static int pc98_check_8251fifo(void); 433 static void pc98_check_sysclock(void); 434 static void pc98_set_ioport(struct com_s *com); 435 436 #define com_int_Tx_disable(com) \ 437 pc98_disable_i8251_interrupt(com,IEN_Tx|IEN_TxEMP) 438 #define com_int_Tx_enable(com) \ 439 pc98_enable_i8251_interrupt(com,IEN_TxFLAG) 440 #define com_int_Rx_disable(com) \ 441 pc98_disable_i8251_interrupt(com,IEN_Rx) 442 #define com_int_Rx_enable(com) \ 443 pc98_enable_i8251_interrupt(com,IEN_Rx) 444 #define com_int_TxRx_disable(com) \ 445 pc98_disable_i8251_interrupt(com,IEN_Tx|IEN_TxEMP|IEN_Rx) 446 #define com_int_TxRx_enable(com) \ 447 pc98_enable_i8251_interrupt(com,IEN_TxFLAG|IEN_Rx) 448 #define com_send_break_on(com) \ 449 (IS_8251((com)->pc98_if_type) ? \ 450 pc98_i8251_or_cmd((com), CMD8251_SBRK) : \ 451 sio_setreg((com), com_cfcr, (com)->cfcr_image |= CFCR_SBREAK)) 452 #define com_send_break_off(com) \ 453 (IS_8251((com)->pc98_if_type) ? \ 454 pc98_i8251_clear_cmd((com), CMD8251_SBRK) : \ 455 sio_setreg((com), com_cfcr, (com)->cfcr_image &= ~CFCR_SBREAK)) 456 457 static struct speedtab pc98speedtab[] = { /* internal RS232C interface */ 458 { 0, 0, }, 459 { 50, 50, }, 460 { 75, 75, }, 461 { 150, 150, }, 462 { 200, 200, }, 463 { 300, 300, }, 464 { 600, 600, }, 465 { 1200, 1200, }, 466 { 2400, 2400, }, 467 { 4800, 4800, }, 468 { 9600, 9600, }, 469 { 19200, 19200, }, 470 { 38400, 38400, }, 471 { 51200, 51200, }, 472 { 76800, 76800, }, 473 { 20800, 20800, }, 474 { 31200, 31200, }, 475 { 41600, 41600, }, 476 { 62400, 62400, }, 477 { -1, -1 } 478 }; 479 static struct speedtab pc98fast_speedtab[] = { 480 { 9600, 0x80 | (DEFAULT_RCLK / (16 * (9600))), }, 481 { 19200, 0x80 | (DEFAULT_RCLK / (16 * (19200))), }, 482 { 38400, 0x80 | (DEFAULT_RCLK / (16 * (38400))), }, 483 { 57600, 0x80 | (DEFAULT_RCLK / (16 * (57600))), }, 484 { 115200, 0x80 | (DEFAULT_RCLK / (16 * (115200))), }, 485 { -1, -1 } 486 }; 487 static struct speedtab comspeedtab_pio9032b[] = { 488 { 300, 6, }, 489 { 600, 5, }, 490 { 1200, 4, }, 491 { 2400, 3, }, 492 { 4800, 2, }, 493 { 9600, 1, }, 494 { 19200, 0, }, 495 { 38400, 7, }, 496 { -1, -1 } 497 }; 498 static struct speedtab comspeedtab_b98_01[] = { 499 { 75, 11, }, 500 { 150, 10, }, 501 { 300, 9, }, 502 { 600, 8, }, 503 { 1200, 7, }, 504 { 2400, 6, }, 505 { 4800, 5, }, 506 { 9600, 4, }, 507 { 19200, 3, }, 508 { 38400, 2, }, 509 { 76800, 1, }, 510 { 153600, 0, }, 511 { -1, -1 } 512 }; 513 static struct speedtab comspeedtab_ind[] = { 514 { 300, 1536, }, 515 { 600, 768, }, 516 { 1200, 384, }, 517 { 2400, 192, }, 518 { 4800, 96, }, 519 { 9600, 48, }, 520 { 19200, 24, }, 521 { 38400, 12, }, 522 { 57600, 8, }, 523 { 115200, 4, }, 524 { 153600, 3, }, 525 { 230400, 2, }, 526 { 460800, 1, }, 527 { -1, -1 } 528 }; 529 530 struct { 531 char *name; 532 short port_table[7]; 533 short irr_mask; 534 struct speedtab *speedtab; 535 short check_irq; 536 } if_8251_type[] = { 537 /* COM_IF_INTERNAL */ 538 { " (internal)", {0x30, 0x32, 0x32, 0x33, 0x35, -1, -1}, 539 -1, pc98speedtab, 1 }, 540 /* COM_IF_PC9861K_1 */ 541 { " (PC9861K)", {0xb1, 0xb3, 0xb3, 0xb0, 0xb0, -1, -1}, 542 3, NULL, 1 }, 543 /* COM_IF_PC9861K_2 */ 544 { " (PC9861K)", {0xb9, 0xbb, 0xbb, 0xb2, 0xb2, -1, -1}, 545 3, NULL, 1 }, 546 /* COM_IF_IND_SS_1 */ 547 { " (IND-SS)", {0xb1, 0xb3, 0xb3, 0xb0, 0xb0, 0xb3, -1}, 548 3, comspeedtab_ind, 1 }, 549 /* COM_IF_IND_SS_2 */ 550 { " (IND-SS)", {0xb9, 0xbb, 0xbb, 0xb2, 0xb2, 0xbb, -1}, 551 3, comspeedtab_ind, 1 }, 552 /* COM_IF_PIO9032B_1 */ 553 { " (PIO9032B)", {0xb1, 0xb3, 0xb3, 0xb0, 0xb0, 0xb8, -1}, 554 7, comspeedtab_pio9032b, 1 }, 555 /* COM_IF_PIO9032B_2 */ 556 { " (PIO9032B)", {0xb9, 0xbb, 0xbb, 0xb2, 0xb2, 0xba, -1}, 557 7, comspeedtab_pio9032b, 1 }, 558 /* COM_IF_B98_01_1 */ 559 { " (B98-01)", {0xb1, 0xb3, 0xb3, 0xb0, 0xb0, 0xd1, 0xd3}, 560 7, comspeedtab_b98_01, 0 }, 561 /* COM_IF_B98_01_2 */ 562 { " (B98-01)", {0xb9, 0xbb, 0xbb, 0xb2, 0xb2, 0xd5, 0xd7}, 563 7, comspeedtab_b98_01, 0 }, 564 }; 565 #define PC98SIO_data_port(type) (if_8251_type[type].port_table[0]) 566 #define PC98SIO_cmd_port(type) (if_8251_type[type].port_table[1]) 567 #define PC98SIO_sts_port(type) (if_8251_type[type].port_table[2]) 568 #define PC98SIO_in_modem_port(type) (if_8251_type[type].port_table[3]) 569 #define PC98SIO_intr_ctrl_port(type) (if_8251_type[type].port_table[4]) 570 #define PC98SIO_baud_rate_port(type) (if_8251_type[type].port_table[5]) 571 #define PC98SIO_func_port(type) (if_8251_type[type].port_table[6]) 572 573 #define I8251F_data 0x130 574 #define I8251F_lsr 0x132 575 #define I8251F_msr 0x134 576 #define I8251F_iir 0x136 577 #define I8251F_fcr 0x138 578 #define I8251F_div 0x13a 579 580 581 static bus_addr_t port_table_0[] = 582 {0x000, 0x001, 0x002, 0x003, 0x004, 0x005, 0x006, 0x007}; 583 static bus_addr_t port_table_1[] = 584 {0x000, 0x002, 0x004, 0x006, 0x008, 0x00a, 0x00c, 0x00e}; 585 static bus_addr_t port_table_8[] = 586 {0x000, 0x100, 0x200, 0x300, 0x400, 0x500, 0x600, 0x700}; 587 static bus_addr_t port_table_rsa[] = { 588 0x008, 0x009, 0x00a, 0x00b, 0x00c, 0x00d, 0x00e, 0x00f, 589 0x000, 0x001, 0x002, 0x003, 0x004, 0x005, 0x006, 0x007 590 }; 591 592 struct { 593 char *name; 594 short irr_read; 595 short irr_write; 596 bus_addr_t *iat; 597 bus_size_t iatsz; 598 u_long rclk; 599 } if_16550a_type[] = { 600 /* COM_IF_RSA98 */ 601 {" (RSA-98)", -1, -1, port_table_0, IO_COMSIZE, DEFAULT_RCLK}, 602 /* COM_IF_NS16550 */ 603 {"", -1, -1, port_table_0, IO_COMSIZE, DEFAULT_RCLK}, 604 /* COM_IF_SECOND_CCU */ 605 {"", -1, -1, port_table_0, IO_COMSIZE, DEFAULT_RCLK}, 606 /* COM_IF_MC16550II */ 607 {" (MC16550II)", -1, 0x1000, port_table_8, IO_COMSIZE, 608 DEFAULT_RCLK * 4}, 609 /* COM_IF_MCRS98 */ 610 {" (MC-RS98)", -1, 0x1000, port_table_8, IO_COMSIZE, DEFAULT_RCLK * 4}, 611 /* COM_IF_RSB3000 */ 612 {" (RSB-3000)", 0xbf, -1, port_table_1, IO_COMSIZE, DEFAULT_RCLK * 10}, 613 /* COM_IF_RSB384 */ 614 {" (RSB-384)", 0xbf, -1, port_table_1, IO_COMSIZE, DEFAULT_RCLK * 10}, 615 /* COM_IF_MODEM_CARD */ 616 {"", -1, -1, port_table_0, IO_COMSIZE, DEFAULT_RCLK}, 617 /* COM_IF_RSA98III */ 618 {" (RSA-98III)", -1, -1, port_table_rsa, 16, DEFAULT_RCLK * 8}, 619 /* COM_IF_ESP98 */ 620 {" (ESP98)", -1, -1, port_table_1, IO_COMSIZE, DEFAULT_RCLK * 4}, 621 }; 622 #endif /* PC98 */ 623 624 #ifdef GDB 625 static Port_t siogdbiobase = 0; 626 #endif 627 628 #ifdef COM_ESP 629 #ifdef PC98 630 631 /* XXX configure this properly. */ 632 /* XXX quite broken for new-bus. */ 633 static Port_t likely_com_ports[] = { 0, 0xb0, 0xb1, 0 }; 634 static Port_t likely_esp_ports[] = { 0xc0d0, 0 }; 635 636 #define ESP98_CMD1 (ESP_CMD1 * 0x100) 637 #define ESP98_CMD2 (ESP_CMD2 * 0x100) 638 #define ESP98_STATUS1 (ESP_STATUS1 * 0x100) 639 #define ESP98_STATUS2 (ESP_STATUS2 * 0x100) 640 641 #else /* PC98 */ 642 643 /* XXX configure this properly. */ 644 static Port_t likely_com_ports[] = { 0x3f8, 0x2f8, 0x3e8, 0x2e8, }; 645 static Port_t likely_esp_ports[] = { 0x140, 0x180, 0x280, 0 }; 646 647 #endif /* PC98 */ 648 #endif 649 650 /* 651 * handle sysctl read/write requests for console speed 652 * 653 * In addition to setting comdefaultrate for I/O through /dev/console, 654 * also set the initial and lock values for the /dev/ttyXX device 655 * if there is one associated with the console. Finally, if the /dev/tty 656 * device has already been open, change the speed on the open running port 657 * itself. 658 */ 659 660 static int 661 sysctl_machdep_comdefaultrate(SYSCTL_HANDLER_ARGS) 662 { 663 int error, s; 664 speed_t newspeed; 665 struct com_s *com; 666 struct tty *tp; 667 668 newspeed = comdefaultrate; 669 670 error = sysctl_handle_opaque(oidp, &newspeed, sizeof newspeed, req); 671 if (error || !req->newptr) 672 return (error); 673 674 comdefaultrate = newspeed; 675 676 if (comconsole < 0) /* serial console not selected? */ 677 return (0); 678 679 com = com_addr(comconsole); 680 if (com == NULL) 681 return (ENXIO); 682 683 tp = com->tp; 684 if (tp == NULL) 685 return (ENXIO); 686 687 /* 688 * set the initial and lock rates for /dev/ttydXX and /dev/cuaXX 689 * (note, the lock rates really are boolean -- if non-zero, disallow 690 * speed changes) 691 */ 692 tp->t_init_in.c_ispeed = tp->t_init_in.c_ospeed = 693 tp->t_lock_in.c_ispeed = tp->t_lock_in.c_ospeed = 694 tp->t_init_out.c_ispeed = tp->t_init_out.c_ospeed = 695 tp->t_lock_out.c_ispeed = tp->t_lock_out.c_ospeed = comdefaultrate; 696 697 if (tp->t_state & TS_ISOPEN) { 698 tp->t_termios.c_ispeed = 699 tp->t_termios.c_ospeed = comdefaultrate; 700 s = spltty(); 701 error = comparam(tp, &tp->t_termios); 702 splx(s); 703 } 704 return error; 705 } 706 707 SYSCTL_PROC(_machdep, OID_AUTO, conspeed, CTLTYPE_INT | CTLFLAG_RW, 708 0, 0, sysctl_machdep_comdefaultrate, "I", ""); 709 TUNABLE_INT("machdep.conspeed", __DEVOLATILE(int *, &comdefaultrate)); 710 711 /* 712 * Unload the driver and clear the table. 713 * XXX this is mostly wrong. 714 * XXX TODO: 715 * This is usually called when the card is ejected, but 716 * can be caused by a kldunload of a controller driver. 717 * The idea is to reset the driver's view of the device 718 * and ensure that any driver entry points such as 719 * read and write do not hang. 720 */ 721 int 722 siodetach(device_t dev) 723 { 724 struct com_s *com; 725 726 com = (struct com_s *) device_get_softc(dev); 727 if (com == NULL) { 728 device_printf(dev, "NULL com in siounload\n"); 729 return (0); 730 } 731 com->gone = TRUE; 732 if (com->tp) 733 ttyfree(com->tp); 734 if (com->irqres) { 735 bus_teardown_intr(dev, com->irqres, com->cookie); 736 bus_release_resource(dev, SYS_RES_IRQ, 0, com->irqres); 737 } 738 if (com->ioportres) 739 bus_release_resource(dev, SYS_RES_IOPORT, com->ioportrid, 740 com->ioportres); 741 if (com->ibuf != NULL) 742 free(com->ibuf, M_DEVBUF); 743 #ifdef PC98 744 if (com->obuf1 != NULL) 745 free(com->obuf1, M_DEVBUF); 746 #endif 747 748 device_set_softc(dev, NULL); 749 free(com, M_DEVBUF); 750 return (0); 751 } 752 753 int 754 sioprobe(dev, xrid, rclk, noprobe) 755 device_t dev; 756 int xrid; 757 u_long rclk; 758 int noprobe; 759 { 760 #if 0 761 static bool_t already_init; 762 device_t xdev; 763 #endif 764 struct com_s *com; 765 u_int divisor; 766 bool_t failures[10]; 767 int fn; 768 device_t idev; 769 Port_t iobase; 770 intrmask_t irqmap[4]; 771 intrmask_t irqs; 772 u_char mcr_image; 773 int result; 774 u_long xirq; 775 u_int flags = device_get_flags(dev); 776 int rid; 777 struct resource *port; 778 #ifdef PC98 779 int tmp; 780 struct siodev iod; 781 #endif 782 783 #ifdef PC98 784 iod.if_type = GET_IFTYPE(flags); 785 if ((iod.if_type < 0 || iod.if_type > COM_IF_END1) && 786 (iod.if_type < 0x10 || iod.if_type > COM_IF_END2)) 787 return ENXIO; 788 #endif 789 790 rid = xrid; 791 #ifdef PC98 792 if (IS_8251(iod.if_type)) { 793 port = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &rid, 794 RF_ACTIVE); 795 } else if (iod.if_type == COM_IF_MODEM_CARD || 796 iod.if_type == COM_IF_RSA98III || 797 isa_get_vendorid(dev)) { 798 port = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid, 0, ~0, 799 if_16550a_type[iod.if_type & 0x0f].iatsz, RF_ACTIVE); 800 } else { 801 port = isa_alloc_resourcev(dev, SYS_RES_IOPORT, &rid, 802 if_16550a_type[iod.if_type & 0x0f].iat, 803 if_16550a_type[iod.if_type & 0x0f].iatsz, RF_ACTIVE); 804 } 805 #else 806 port = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid, 807 0, ~0, IO_COMSIZE, RF_ACTIVE); 808 #endif 809 if (!port) 810 return (ENXIO); 811 #ifdef PC98 812 if (!IS_8251(iod.if_type)) { 813 if (isa_load_resourcev(port, 814 if_16550a_type[iod.if_type & 0x0f].iat, 815 if_16550a_type[iod.if_type & 0x0f].iatsz) != 0) { 816 bus_release_resource(dev, SYS_RES_IOPORT, rid, port); 817 return ENXIO; 818 } 819 } 820 #endif 821 822 com = malloc(sizeof(*com), M_DEVBUF, M_NOWAIT | M_ZERO); 823 if (com == NULL) { 824 bus_release_resource(dev, SYS_RES_IOPORT, rid, port); 825 return (ENOMEM); 826 } 827 device_set_softc(dev, com); 828 com->bst = rman_get_bustag(port); 829 com->bsh = rman_get_bushandle(port); 830 #ifdef PC98 831 if (!IS_8251(iod.if_type) && rclk == 0) 832 rclk = if_16550a_type[iod.if_type & 0x0f].rclk; 833 #else 834 if (rclk == 0) 835 rclk = DEFAULT_RCLK; 836 #endif 837 com->rclk = rclk; 838 839 while (sio_inited != 2) 840 if (atomic_cmpset_int(&sio_inited, 0, 1)) { 841 mtx_init(&sio_lock, sio_driver_name, NULL, 842 (comconsole != -1) ? 843 MTX_SPIN | MTX_QUIET : MTX_SPIN); 844 atomic_store_rel_int(&sio_inited, 2); 845 } 846 847 #if 0 848 /* 849 * XXX this is broken - when we are first called, there are no 850 * previously configured IO ports. We could hard code 851 * 0x3f8, 0x2f8, 0x3e8, 0x2e8 etc but that's probably worse. 852 * This code has been doing nothing since the conversion since 853 * "count" is zero the first time around. 854 */ 855 if (!already_init) { 856 /* 857 * Turn off MCR_IENABLE for all likely serial ports. An unused 858 * port with its MCR_IENABLE gate open will inhibit interrupts 859 * from any used port that shares the interrupt vector. 860 * XXX the gate enable is elsewhere for some multiports. 861 */ 862 device_t *devs; 863 int count, i, xioport; 864 #ifdef PC98 865 int xiftype; 866 #endif 867 868 devclass_get_devices(sio_devclass, &devs, &count); 869 #ifdef PC98 870 for (i = 0; i < count; i++) { 871 xdev = devs[i]; 872 xioport = bus_get_resource_start(xdev, SYS_RES_IOPORT, 0); 873 xiftype = GET_IFTYPE(device_get_flags(xdev)); 874 if (device_is_enabled(xdev) && xioport > 0) { 875 if (IS_8251(xiftype)) 876 outb((xioport & 0xff00) | PC98SIO_cmd_port(xiftype & 0x0f), 0xf2); 877 else 878 outb(xioport + if_16550a_type[xiftype & 0x0f].iat[com_mcr], 0); 879 } 880 } 881 #else 882 for (i = 0; i < count; i++) { 883 xdev = devs[i]; 884 if (device_is_enabled(xdev) && 885 bus_get_resource(xdev, SYS_RES_IOPORT, 0, &xioport, 886 NULL) == 0) 887 outb(xioport + com_mcr, 0); 888 } 889 #endif 890 free(devs, M_TEMP); 891 already_init = TRUE; 892 } 893 #endif 894 895 if (COM_LLCONSOLE(flags)) { 896 printf("sio%d: reserved for low-level i/o\n", 897 device_get_unit(dev)); 898 bus_release_resource(dev, SYS_RES_IOPORT, rid, port); 899 device_set_softc(dev, NULL); 900 free(com, M_DEVBUF); 901 return (ENXIO); 902 } 903 904 #ifdef PC98 905 DELAY(10); 906 907 /* 908 * If the port is i8251 UART (internal, B98_01) 909 */ 910 if (pc98_check_if_type(dev, &iod) == -1) { 911 bus_release_resource(dev, SYS_RES_IOPORT, rid, port); 912 device_set_softc(dev, NULL); 913 free(com, M_DEVBUF); 914 return (ENXIO); 915 } 916 if (iod.irq > 0) 917 bus_set_resource(dev, SYS_RES_IRQ, 0, iod.irq, 1); 918 if (IS_8251(iod.if_type)) { 919 outb(iod.cmd, 0); 920 DELAY(10); 921 outb(iod.cmd, 0); 922 DELAY(10); 923 outb(iod.cmd, 0); 924 DELAY(10); 925 outb(iod.cmd, CMD8251_RESET); 926 DELAY(1000); /* for a while...*/ 927 outb(iod.cmd, 0xf2); /* MODE (dummy) */ 928 DELAY(10); 929 outb(iod.cmd, 0x01); /* CMD (dummy) */ 930 DELAY(1000); /* for a while...*/ 931 if (( inb(iod.sts) & STS8251_TxEMP ) == 0 ) { 932 result = (ENXIO); 933 } 934 if (if_8251_type[iod.if_type & 0x0f].check_irq) { 935 COM_INT_DISABLE 936 tmp = ( inb( iod.ctrl ) & ~(IEN_Rx|IEN_TxEMP|IEN_Tx)); 937 outb( iod.ctrl, tmp|IEN_TxEMP ); 938 DELAY(10); 939 result = isa_irq_pending() ? 0 : ENXIO; 940 outb( iod.ctrl, tmp ); 941 COM_INT_ENABLE 942 } else { 943 /* 944 * B98_01 doesn't activate TxEMP interrupt line 945 * when being reset, so we can't check irq pending. 946 */ 947 result = 0; 948 } 949 bus_release_resource(dev, SYS_RES_IOPORT, rid, port); 950 if (result) { 951 device_set_softc(dev, NULL); 952 free(com, M_DEVBUF); 953 } 954 return result; 955 } 956 #endif /* PC98 */ 957 /* 958 * If the device is on a multiport card and has an AST/4 959 * compatible interrupt control register, initialize this 960 * register and prepare to leave MCR_IENABLE clear in the mcr. 961 * Otherwise, prepare to set MCR_IENABLE in the mcr. 962 * Point idev to the device struct giving the correct id_irq. 963 * This is the struct for the master device if there is one. 964 */ 965 idev = dev; 966 mcr_image = MCR_IENABLE; 967 #ifdef COM_MULTIPORT 968 if (COM_ISMULTIPORT(flags)) { 969 #ifndef PC98 970 Port_t xiobase; 971 u_long io; 972 #endif 973 974 idev = devclass_get_device(sio_devclass, COM_MPMASTER(flags)); 975 if (idev == NULL) { 976 printf("sio%d: master device %d not configured\n", 977 device_get_unit(dev), COM_MPMASTER(flags)); 978 idev = dev; 979 } 980 #ifndef PC98 981 if (!COM_NOTAST4(flags)) { 982 if (bus_get_resource(idev, SYS_RES_IOPORT, 0, &io, 983 NULL) == 0) { 984 xiobase = io; 985 if (bus_get_resource(idev, SYS_RES_IRQ, 0, 986 NULL, NULL) == 0) 987 outb(xiobase + com_scr, 0x80); 988 else 989 outb(xiobase + com_scr, 0); 990 } 991 mcr_image = 0; 992 } 993 #endif 994 } 995 #endif /* COM_MULTIPORT */ 996 if (bus_get_resource(idev, SYS_RES_IRQ, 0, NULL, NULL) != 0) 997 mcr_image = 0; 998 999 bzero(failures, sizeof failures); 1000 iobase = rman_get_start(port); 1001 1002 #ifdef PC98 1003 if (iod.if_type == COM_IF_RSA98III) { 1004 mcr_image = 0; 1005 1006 outb(iobase + rsa_msr, 0x04); 1007 outb(iobase + rsa_frr, 0x00); 1008 if ((inb(iobase + rsa_srr) & 0x36) != 0x36) { 1009 bus_release_resource(dev, SYS_RES_IOPORT, rid, port); 1010 device_set_softc(dev, NULL); 1011 free(com, M_DEVBUF); 1012 return (ENXIO); 1013 } 1014 outb(iobase + rsa_ier, 0x00); 1015 outb(iobase + rsa_frr, 0x00); 1016 outb(iobase + rsa_tivsr, 0x00); 1017 outb(iobase + rsa_tcr, 0x00); 1018 } 1019 1020 tmp = if_16550a_type[iod.if_type & 0x0f].irr_write; 1021 if (tmp != -1) { 1022 /* MC16550II */ 1023 int irqout; 1024 switch (isa_get_irq(idev)) { 1025 case 3: irqout = 4; break; 1026 case 5: irqout = 5; break; 1027 case 6: irqout = 6; break; 1028 case 12: irqout = 7; break; 1029 default: 1030 printf("sio%d: irq configuration error\n", 1031 device_get_unit(dev)); 1032 bus_release_resource(dev, SYS_RES_IOPORT, rid, port); 1033 device_set_softc(dev, NULL); 1034 free(com, M_DEVBUF); 1035 return (ENXIO); 1036 } 1037 outb((iobase & 0x00ff) | tmp, irqout); 1038 } 1039 #endif 1040 1041 /* 1042 * We don't want to get actual interrupts, just masked ones. 1043 * Interrupts from this line should already be masked in the ICU, 1044 * but mask them in the processor as well in case there are some 1045 * (misconfigured) shared interrupts. 1046 */ 1047 mtx_lock_spin(&sio_lock); 1048 /* EXTRA DELAY? */ 1049 1050 /* 1051 * Initialize the speed and the word size and wait long enough to 1052 * drain the maximum of 16 bytes of junk in device output queues. 1053 * The speed is undefined after a master reset and must be set 1054 * before relying on anything related to output. There may be 1055 * junk after a (very fast) soft reboot and (apparently) after 1056 * master reset. 1057 * XXX what about the UART bug avoided by waiting in comparam()? 1058 * We don't want to to wait long enough to drain at 2 bps. 1059 */ 1060 if (iobase == siocniobase) 1061 DELAY((16 + 1) * 1000000 / (comdefaultrate / 10)); 1062 else { 1063 sio_setreg(com, com_cfcr, CFCR_DLAB | CFCR_8BITS); 1064 divisor = siodivisor(rclk, SIO_TEST_SPEED); 1065 sio_setreg(com, com_dlbl, divisor & 0xff); 1066 sio_setreg(com, com_dlbh, divisor >> 8); 1067 sio_setreg(com, com_cfcr, CFCR_8BITS); 1068 DELAY((16 + 1) * 1000000 / (SIO_TEST_SPEED / 10)); 1069 } 1070 1071 /* 1072 * Enable the interrupt gate and disable device interrupts. This 1073 * should leave the device driving the interrupt line low and 1074 * guarantee an edge trigger if an interrupt can be generated. 1075 */ 1076 /* EXTRA DELAY? */ 1077 sio_setreg(com, com_mcr, mcr_image); 1078 sio_setreg(com, com_ier, 0); 1079 DELAY(1000); /* XXX */ 1080 irqmap[0] = isa_irq_pending(); 1081 1082 /* 1083 * Attempt to set loopback mode so that we can send a null byte 1084 * without annoying any external device. 1085 */ 1086 /* EXTRA DELAY? */ 1087 sio_setreg(com, com_mcr, mcr_image | MCR_LOOPBACK); 1088 1089 /* 1090 * Attempt to generate an output interrupt. On 8250's, setting 1091 * IER_ETXRDY generates an interrupt independent of the current 1092 * setting and independent of whether the THR is empty. On 16450's, 1093 * setting IER_ETXRDY generates an interrupt independent of the 1094 * current setting. On 16550A's, setting IER_ETXRDY only 1095 * generates an interrupt when IER_ETXRDY is not already set. 1096 */ 1097 sio_setreg(com, com_ier, IER_ETXRDY); 1098 #ifdef PC98 1099 if (iod.if_type == COM_IF_RSA98III) 1100 outb(iobase + rsa_ier, 0x04); 1101 #endif 1102 1103 /* 1104 * On some 16x50 incompatibles, setting IER_ETXRDY doesn't generate 1105 * an interrupt. They'd better generate one for actually doing 1106 * output. Loopback may be broken on the same incompatibles but 1107 * it's unlikely to do more than allow the null byte out. 1108 */ 1109 sio_setreg(com, com_data, 0); 1110 if (iobase == siocniobase) 1111 DELAY((1 + 2) * 1000000 / (comdefaultrate / 10)); 1112 else 1113 DELAY((1 + 2) * 1000000 / (SIO_TEST_SPEED / 10)); 1114 1115 /* 1116 * Turn off loopback mode so that the interrupt gate works again 1117 * (MCR_IENABLE was hidden). This should leave the device driving 1118 * an interrupt line high. It doesn't matter if the interrupt 1119 * line oscillates while we are not looking at it, since interrupts 1120 * are disabled. 1121 */ 1122 /* EXTRA DELAY? */ 1123 sio_setreg(com, com_mcr, mcr_image); 1124 1125 /* 1126 * It seems my Xircom CBEM56G Cardbus modem wants to be reset 1127 * to 8 bits *again*, or else probe test 0 will fail. 1128 * gwk@sgi.com, 4/19/2001 1129 */ 1130 sio_setreg(com, com_cfcr, CFCR_8BITS); 1131 1132 /* 1133 * Some PCMCIA cards (Palido 321s, DC-1S, ...) have the "TXRDY bug", 1134 * so we probe for a buggy IIR_TXRDY implementation even in the 1135 * noprobe case. We don't probe for it in the !noprobe case because 1136 * noprobe is always set for PCMCIA cards and the problem is not 1137 * known to affect any other cards. 1138 */ 1139 if (noprobe) { 1140 /* Read IIR a few times. */ 1141 for (fn = 0; fn < 2; fn ++) { 1142 DELAY(10000); 1143 failures[6] = sio_getreg(com, com_iir); 1144 } 1145 1146 /* IIR_TXRDY should be clear. Is it? */ 1147 result = 0; 1148 if (failures[6] & IIR_TXRDY) { 1149 /* 1150 * No. We seem to have the bug. Does our fix for 1151 * it work? 1152 */ 1153 sio_setreg(com, com_ier, 0); 1154 if (sio_getreg(com, com_iir) & IIR_NOPEND) { 1155 /* Yes. We discovered the TXRDY bug! */ 1156 SET_FLAG(dev, COM_C_IIR_TXRDYBUG); 1157 } else { 1158 /* No. Just fail. XXX */ 1159 result = ENXIO; 1160 sio_setreg(com, com_mcr, 0); 1161 } 1162 } else { 1163 /* Yes. No bug. */ 1164 CLR_FLAG(dev, COM_C_IIR_TXRDYBUG); 1165 } 1166 sio_setreg(com, com_ier, 0); 1167 sio_setreg(com, com_cfcr, CFCR_8BITS); 1168 mtx_unlock_spin(&sio_lock); 1169 bus_release_resource(dev, SYS_RES_IOPORT, rid, port); 1170 if (iobase == siocniobase) 1171 result = 0; 1172 if (result != 0) { 1173 device_set_softc(dev, NULL); 1174 free(com, M_DEVBUF); 1175 } 1176 return (result); 1177 } 1178 1179 /* 1180 * Check that 1181 * o the CFCR, IER and MCR in UART hold the values written to them 1182 * (the values happen to be all distinct - this is good for 1183 * avoiding false positive tests from bus echoes). 1184 * o an output interrupt is generated and its vector is correct. 1185 * o the interrupt goes away when the IIR in the UART is read. 1186 */ 1187 /* EXTRA DELAY? */ 1188 failures[0] = sio_getreg(com, com_cfcr) - CFCR_8BITS; 1189 failures[1] = sio_getreg(com, com_ier) - IER_ETXRDY; 1190 failures[2] = sio_getreg(com, com_mcr) - mcr_image; 1191 DELAY(10000); /* Some internal modems need this time */ 1192 irqmap[1] = isa_irq_pending(); 1193 failures[4] = (sio_getreg(com, com_iir) & IIR_IMASK) - IIR_TXRDY; 1194 #ifdef PC98 1195 if (iod.if_type == COM_IF_RSA98III) 1196 inb(iobase + rsa_srr); 1197 #endif 1198 DELAY(1000); /* XXX */ 1199 irqmap[2] = isa_irq_pending(); 1200 failures[6] = (sio_getreg(com, com_iir) & IIR_IMASK) - IIR_NOPEND; 1201 #ifdef PC98 1202 if (iod.if_type == COM_IF_RSA98III) 1203 inb(iobase + rsa_srr); 1204 #endif 1205 1206 /* 1207 * Turn off all device interrupts and check that they go off properly. 1208 * Leave MCR_IENABLE alone. For ports without a master port, it gates 1209 * the OUT2 output of the UART to 1210 * the ICU input. Closing the gate would give a floating ICU input 1211 * (unless there is another device driving it) and spurious interrupts. 1212 * (On the system that this was first tested on, the input floats high 1213 * and gives a (masked) interrupt as soon as the gate is closed.) 1214 */ 1215 sio_setreg(com, com_ier, 0); 1216 sio_setreg(com, com_cfcr, CFCR_8BITS); /* dummy to avoid bus echo */ 1217 failures[7] = sio_getreg(com, com_ier); 1218 #ifdef PC98 1219 if (iod.if_type == COM_IF_RSA98III) 1220 outb(iobase + rsa_ier, 0x00); 1221 #endif 1222 DELAY(1000); /* XXX */ 1223 irqmap[3] = isa_irq_pending(); 1224 failures[9] = (sio_getreg(com, com_iir) & IIR_IMASK) - IIR_NOPEND; 1225 #ifdef PC98 1226 if (iod.if_type == COM_IF_RSA98III) { 1227 inb(iobase + rsa_srr); 1228 outb(iobase + rsa_frr, 0x00); 1229 } 1230 #endif 1231 1232 mtx_unlock_spin(&sio_lock); 1233 1234 irqs = irqmap[1] & ~irqmap[0]; 1235 if (bus_get_resource(idev, SYS_RES_IRQ, 0, &xirq, NULL) == 0 && 1236 ((1 << xirq) & irqs) == 0) { 1237 printf( 1238 "sio%d: configured irq %ld not in bitmap of probed irqs %#x\n", 1239 device_get_unit(dev), xirq, irqs); 1240 printf( 1241 "sio%d: port may not be enabled\n", 1242 device_get_unit(dev)); 1243 } 1244 if (bootverbose) 1245 printf("sio%d: irq maps: %#x %#x %#x %#x\n", 1246 device_get_unit(dev), 1247 irqmap[0], irqmap[1], irqmap[2], irqmap[3]); 1248 1249 result = 0; 1250 for (fn = 0; fn < sizeof failures; ++fn) 1251 if (failures[fn]) { 1252 sio_setreg(com, com_mcr, 0); 1253 result = ENXIO; 1254 if (bootverbose) { 1255 printf("sio%d: probe failed test(s):", 1256 device_get_unit(dev)); 1257 for (fn = 0; fn < sizeof failures; ++fn) 1258 if (failures[fn]) 1259 printf(" %d", fn); 1260 printf("\n"); 1261 } 1262 break; 1263 } 1264 bus_release_resource(dev, SYS_RES_IOPORT, rid, port); 1265 if (iobase == siocniobase) 1266 result = 0; 1267 if (result != 0) { 1268 device_set_softc(dev, NULL); 1269 free(com, M_DEVBUF); 1270 } 1271 return (result); 1272 } 1273 1274 #ifdef COM_ESP 1275 static int 1276 espattach(com, esp_port) 1277 struct com_s *com; 1278 Port_t esp_port; 1279 { 1280 u_char dips; 1281 u_char val; 1282 1283 /* 1284 * Check the ESP-specific I/O port to see if we're an ESP 1285 * card. If not, return failure immediately. 1286 */ 1287 if ((inb(esp_port) & 0xf3) == 0) { 1288 printf(" port 0x%x is not an ESP board?\n", esp_port); 1289 return (0); 1290 } 1291 1292 /* 1293 * We've got something that claims to be a Hayes ESP card. 1294 * Let's hope so. 1295 */ 1296 1297 /* Get the dip-switch configuration */ 1298 #ifdef PC98 1299 outb(esp_port + ESP98_CMD1, ESP_GETDIPS); 1300 dips = inb(esp_port + ESP98_STATUS1); 1301 #else 1302 outb(esp_port + ESP_CMD1, ESP_GETDIPS); 1303 dips = inb(esp_port + ESP_STATUS1); 1304 #endif 1305 1306 /* 1307 * Bits 0,1 of dips say which COM port we are. 1308 */ 1309 #ifdef PC98 1310 if ((rman_get_start(com->ioportres) & 0xff) == 1311 likely_com_ports[dips & 0x03]) 1312 #else 1313 if (rman_get_start(com->ioportres) == likely_com_ports[dips & 0x03]) 1314 #endif 1315 printf(" : ESP"); 1316 else { 1317 printf(" esp_port has com %d\n", dips & 0x03); 1318 return (0); 1319 } 1320 1321 /* 1322 * Check for ESP version 2.0 or later: bits 4,5,6 = 010. 1323 */ 1324 #ifdef PC98 1325 outb(esp_port + ESP98_CMD1, ESP_GETTEST); 1326 val = inb(esp_port + ESP98_STATUS1); /* clear reg 1 */ 1327 val = inb(esp_port + ESP98_STATUS2); 1328 #else 1329 outb(esp_port + ESP_CMD1, ESP_GETTEST); 1330 val = inb(esp_port + ESP_STATUS1); /* clear reg 1 */ 1331 val = inb(esp_port + ESP_STATUS2); 1332 #endif 1333 if ((val & 0x70) < 0x20) { 1334 printf("-old (%o)", val & 0x70); 1335 return (0); 1336 } 1337 1338 /* 1339 * Check for ability to emulate 16550: bit 7 == 1 1340 */ 1341 if ((dips & 0x80) == 0) { 1342 printf(" slave"); 1343 return (0); 1344 } 1345 1346 /* 1347 * Okay, we seem to be a Hayes ESP card. Whee. 1348 */ 1349 com->esp = TRUE; 1350 com->esp_port = esp_port; 1351 return (1); 1352 } 1353 #endif /* COM_ESP */ 1354 1355 int 1356 sioattach(dev, xrid, rclk) 1357 device_t dev; 1358 int xrid; 1359 u_long rclk; 1360 { 1361 struct com_s *com; 1362 #ifdef COM_ESP 1363 Port_t *espp; 1364 #endif 1365 Port_t iobase; 1366 int unit; 1367 u_int flags; 1368 int rid; 1369 struct resource *port; 1370 int ret; 1371 int error; 1372 struct tty *tp; 1373 #ifdef PC98 1374 u_char *obuf; 1375 u_long obufsize; 1376 int if_type = GET_IFTYPE(device_get_flags(dev)); 1377 #endif 1378 1379 rid = xrid; 1380 #ifdef PC98 1381 if (IS_8251(if_type)) { 1382 port = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &rid, 1383 RF_ACTIVE); 1384 } else if (if_type == COM_IF_MODEM_CARD || 1385 if_type == COM_IF_RSA98III || 1386 isa_get_vendorid(dev)) { 1387 port = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid, 0, ~0, 1388 if_16550a_type[if_type & 0x0f].iatsz, RF_ACTIVE); 1389 } else { 1390 port = isa_alloc_resourcev(dev, SYS_RES_IOPORT, &rid, 1391 if_16550a_type[if_type & 0x0f].iat, 1392 if_16550a_type[if_type & 0x0f].iatsz, RF_ACTIVE); 1393 } 1394 #else 1395 port = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid, 1396 0, ~0, IO_COMSIZE, RF_ACTIVE); 1397 #endif 1398 if (!port) 1399 return (ENXIO); 1400 #ifdef PC98 1401 if (!IS_8251(if_type)) { 1402 if (isa_load_resourcev(port, 1403 if_16550a_type[if_type & 0x0f].iat, 1404 if_16550a_type[if_type & 0x0f].iatsz) != 0) { 1405 bus_release_resource(dev, SYS_RES_IOPORT, rid, port); 1406 return ENXIO; 1407 } 1408 } 1409 #endif 1410 1411 iobase = rman_get_start(port); 1412 unit = device_get_unit(dev); 1413 com = device_get_softc(dev); 1414 flags = device_get_flags(dev); 1415 1416 if (unit >= sio_numunits) 1417 sio_numunits = unit + 1; 1418 1419 #ifdef PC98 1420 obufsize = 256; 1421 if (if_type == COM_IF_RSA98III) 1422 obufsize = 2048; 1423 if ((obuf = malloc(obufsize * 2, M_DEVBUF, M_NOWAIT)) == NULL) { 1424 bus_release_resource(dev, SYS_RES_IOPORT, rid, port); 1425 return ENXIO; 1426 } 1427 bzero(obuf, obufsize * 2); 1428 #endif 1429 1430 /* 1431 * sioprobe() has initialized the device registers as follows: 1432 * o cfcr = CFCR_8BITS. 1433 * It is most important that CFCR_DLAB is off, so that the 1434 * data port is not hidden when we enable interrupts. 1435 * o ier = 0. 1436 * Interrupts are only enabled when the line is open. 1437 * o mcr = MCR_IENABLE, or 0 if the port has AST/4 compatible 1438 * interrupt control register or the config specifies no irq. 1439 * Keeping MCR_DTR and MCR_RTS off might stop the external 1440 * device from sending before we are ready. 1441 */ 1442 bzero(com, sizeof *com); 1443 com->unit = unit; 1444 com->ioportres = port; 1445 com->ioportrid = rid; 1446 com->bst = rman_get_bustag(port); 1447 com->bsh = rman_get_bushandle(port); 1448 com->cfcr_image = CFCR_8BITS; 1449 com->loses_outints = COM_LOSESOUTINTS(flags) != 0; 1450 com->no_irq = bus_get_resource(dev, SYS_RES_IRQ, 0, NULL, NULL) != 0; 1451 com->tx_fifo_size = 1; 1452 #ifdef PC98 1453 com->obufsize = obufsize; 1454 com->obuf1 = obuf; 1455 com->obuf2 = obuf + obufsize; 1456 #endif 1457 com->obufs[0].l_head = com->obuf1; 1458 com->obufs[1].l_head = com->obuf2; 1459 1460 #ifdef PC98 1461 com->pc98_if_type = if_type; 1462 1463 if (IS_8251(if_type)) { 1464 pc98_set_ioport(com); 1465 1466 if (if_type == COM_IF_INTERNAL && pc98_check_8251fifo()) { 1467 com->pc98_8251fifo = 1; 1468 com->pc98_8251fifo_enable = 0; 1469 } 1470 } else { 1471 bus_addr_t *iat = if_16550a_type[if_type & 0x0f].iat; 1472 1473 com->data_port = iobase + iat[com_data]; 1474 com->int_ctl_port = iobase + iat[com_ier]; 1475 com->int_id_port = iobase + iat[com_iir]; 1476 com->modem_ctl_port = iobase + iat[com_mcr]; 1477 com->mcr_image = inb(com->modem_ctl_port); 1478 com->line_status_port = iobase + iat[com_lsr]; 1479 com->modem_status_port = iobase + iat[com_msr]; 1480 } 1481 #else /* not PC98 */ 1482 com->data_port = iobase + com_data; 1483 com->int_ctl_port = iobase + com_ier; 1484 com->int_id_port = iobase + com_iir; 1485 com->modem_ctl_port = iobase + com_mcr; 1486 com->mcr_image = inb(com->modem_ctl_port); 1487 com->line_status_port = iobase + com_lsr; 1488 com->modem_status_port = iobase + com_msr; 1489 #endif 1490 1491 tp = com->tp = ttyalloc(); 1492 tp->t_oproc = comstart; 1493 tp->t_param = comparam; 1494 tp->t_stop = comstop; 1495 tp->t_modem = commodem; 1496 tp->t_break = combreak; 1497 tp->t_close = comclose; 1498 tp->t_open = comopen; 1499 tp->t_sc = com; 1500 1501 #ifdef PC98 1502 if (!IS_8251(if_type) && rclk == 0) 1503 rclk = if_16550a_type[if_type & 0x0f].rclk; 1504 #else 1505 if (rclk == 0) 1506 rclk = DEFAULT_RCLK; 1507 #endif 1508 com->rclk = rclk; 1509 1510 if (unit == comconsole) 1511 ttyconsolemode(tp, comdefaultrate); 1512 error = siosetwater(com, tp->t_init_in.c_ispeed); 1513 mtx_unlock_spin(&sio_lock); 1514 if (error) { 1515 /* 1516 * Leave i/o resources allocated if this is a `cn'-level 1517 * console, so that other devices can't snarf them. 1518 */ 1519 if (iobase != siocniobase) 1520 bus_release_resource(dev, SYS_RES_IOPORT, rid, port); 1521 return (ENOMEM); 1522 } 1523 1524 /* attempt to determine UART type */ 1525 printf("sio%d: type", unit); 1526 1527 #ifndef PC98 1528 if (!COM_ISMULTIPORT(flags) && 1529 !COM_IIR_TXRDYBUG(flags) && !COM_NOSCR(flags)) { 1530 u_char scr; 1531 u_char scr1; 1532 u_char scr2; 1533 1534 scr = sio_getreg(com, com_scr); 1535 sio_setreg(com, com_scr, 0xa5); 1536 scr1 = sio_getreg(com, com_scr); 1537 sio_setreg(com, com_scr, 0x5a); 1538 scr2 = sio_getreg(com, com_scr); 1539 sio_setreg(com, com_scr, scr); 1540 if (scr1 != 0xa5 || scr2 != 0x5a) { 1541 printf(" 8250 or not responding"); 1542 goto determined_type; 1543 } 1544 } 1545 #endif /* !PC98 */ 1546 #ifdef PC98 1547 if (IS_8251(com->pc98_if_type)) { 1548 if (com->pc98_8251fifo && !COM_NOFIFO(flags)) 1549 com->tx_fifo_size = 16; 1550 com_int_TxRx_disable( com ); 1551 com_cflag_and_speed_set( com, tp->t_init_in.c_cflag, comdefaultrate ); 1552 com_tiocm_bic( com, TIOCM_DTR|TIOCM_RTS|TIOCM_LE ); 1553 com_send_break_off( com ); 1554 1555 if (com->pc98_if_type == COM_IF_INTERNAL) { 1556 printf(" (internal%s%s)", 1557 com->pc98_8251fifo ? " fifo" : "", 1558 PC98SIO_baud_rate_port(com->pc98_if_type) != -1 ? 1559 " v-fast" : ""); 1560 } else { 1561 printf(" 8251%s", if_8251_type[com->pc98_if_type & 0x0f].name); 1562 } 1563 } else { 1564 #endif /* PC98 */ 1565 sio_setreg(com, com_fifo, FIFO_ENABLE | FIFO_RX_HIGH); 1566 DELAY(100); 1567 switch (inb(com->int_id_port) & IIR_FIFO_MASK) { 1568 case FIFO_RX_LOW: 1569 printf(" 16450"); 1570 break; 1571 case FIFO_RX_MEDL: 1572 printf(" 16450?"); 1573 break; 1574 case FIFO_RX_MEDH: 1575 printf(" 16550?"); 1576 break; 1577 case FIFO_RX_HIGH: 1578 if (COM_NOFIFO(flags)) { 1579 printf(" 16550A fifo disabled"); 1580 break; 1581 } 1582 com->hasfifo = TRUE; 1583 #ifdef PC98 1584 if (com->pc98_if_type == COM_IF_RSA98III) { 1585 com->tx_fifo_size = 2048; 1586 com->rsabase = iobase; 1587 outb(com->rsabase + rsa_ier, 0x00); 1588 outb(com->rsabase + rsa_frr, 0x00); 1589 } 1590 #else 1591 if (COM_ST16650A(flags)) { 1592 printf(" ST16650A"); 1593 com->st16650a = TRUE; 1594 com->tx_fifo_size = 32; 1595 break; 1596 } 1597 if (COM_TI16754(flags)) { 1598 printf(" TI16754"); 1599 com->tx_fifo_size = 64; 1600 break; 1601 } 1602 #endif 1603 printf(" 16550A"); 1604 #ifdef COM_ESP 1605 #ifdef PC98 1606 if (com->pc98_if_type == COM_IF_ESP98) 1607 #endif 1608 for (espp = likely_esp_ports; *espp != 0; espp++) 1609 if (espattach(com, *espp)) { 1610 com->tx_fifo_size = 1024; 1611 break; 1612 } 1613 if (com->esp) 1614 break; 1615 #endif 1616 #ifdef PC98 1617 com->tx_fifo_size = 16; 1618 #else 1619 com->tx_fifo_size = COM_FIFOSIZE(flags); 1620 if (com->tx_fifo_size == 0) 1621 com->tx_fifo_size = 16; 1622 else 1623 printf(" lookalike with %u bytes FIFO", 1624 com->tx_fifo_size); 1625 #endif 1626 break; 1627 } 1628 1629 #ifdef PC98 1630 if (com->pc98_if_type == COM_IF_RSB3000) { 1631 /* Set RSB-2000/3000 Extended Buffer mode. */ 1632 u_char lcr; 1633 lcr = sio_getreg(com, com_cfcr); 1634 sio_setreg(com, com_cfcr, lcr | CFCR_DLAB); 1635 sio_setreg(com, com_emr, EMR_EXBUFF | EMR_EFMODE); 1636 sio_setreg(com, com_cfcr, lcr); 1637 } 1638 #endif 1639 1640 #ifdef COM_ESP 1641 if (com->esp) { 1642 /* 1643 * Set 16550 compatibility mode. 1644 * We don't use the ESP_MODE_SCALE bit to increase the 1645 * fifo trigger levels because we can't handle large 1646 * bursts of input. 1647 * XXX flow control should be set in comparam(), not here. 1648 */ 1649 #ifdef PC98 1650 outb(com->esp_port + ESP98_CMD1, ESP_SETMODE); 1651 outb(com->esp_port + ESP98_CMD2, ESP_MODE_RTS | ESP_MODE_FIFO); 1652 #else 1653 outb(com->esp_port + ESP_CMD1, ESP_SETMODE); 1654 outb(com->esp_port + ESP_CMD2, ESP_MODE_RTS | ESP_MODE_FIFO); 1655 #endif 1656 1657 /* Set RTS/CTS flow control. */ 1658 #ifdef PC98 1659 outb(com->esp_port + ESP98_CMD1, ESP_SETFLOWTYPE); 1660 outb(com->esp_port + ESP98_CMD2, ESP_FLOW_RTS); 1661 outb(com->esp_port + ESP98_CMD2, ESP_FLOW_CTS); 1662 #else 1663 outb(com->esp_port + ESP_CMD1, ESP_SETFLOWTYPE); 1664 outb(com->esp_port + ESP_CMD2, ESP_FLOW_RTS); 1665 outb(com->esp_port + ESP_CMD2, ESP_FLOW_CTS); 1666 #endif 1667 1668 /* Set flow-control levels. */ 1669 #ifdef PC98 1670 outb(com->esp_port + ESP98_CMD1, ESP_SETRXFLOW); 1671 outb(com->esp_port + ESP98_CMD2, HIBYTE(768)); 1672 outb(com->esp_port + ESP98_CMD2, LOBYTE(768)); 1673 outb(com->esp_port + ESP98_CMD2, HIBYTE(512)); 1674 outb(com->esp_port + ESP98_CMD2, LOBYTE(512)); 1675 #else 1676 outb(com->esp_port + ESP_CMD1, ESP_SETRXFLOW); 1677 outb(com->esp_port + ESP_CMD2, HIBYTE(768)); 1678 outb(com->esp_port + ESP_CMD2, LOBYTE(768)); 1679 outb(com->esp_port + ESP_CMD2, HIBYTE(512)); 1680 outb(com->esp_port + ESP_CMD2, LOBYTE(512)); 1681 #endif 1682 1683 #ifdef PC98 1684 /* Set UART clock prescaler. */ 1685 outb(com->esp_port + ESP98_CMD1, ESP_SETCLOCK); 1686 outb(com->esp_port + ESP98_CMD2, 2); /* 4 times */ 1687 #endif 1688 } 1689 #endif /* COM_ESP */ 1690 sio_setreg(com, com_fifo, 0); 1691 #ifdef PC98 1692 printf("%s", if_16550a_type[com->pc98_if_type & 0x0f].name); 1693 #else 1694 determined_type: ; 1695 #endif 1696 1697 #ifdef COM_MULTIPORT 1698 if (COM_ISMULTIPORT(flags)) { 1699 device_t masterdev; 1700 1701 com->multiport = TRUE; 1702 printf(" (multiport"); 1703 if (unit == COM_MPMASTER(flags)) 1704 printf(" master"); 1705 printf(")"); 1706 masterdev = devclass_get_device(sio_devclass, 1707 COM_MPMASTER(flags)); 1708 com->no_irq = (masterdev == NULL || bus_get_resource(masterdev, 1709 SYS_RES_IRQ, 0, NULL, NULL) != 0); 1710 } 1711 #endif /* COM_MULTIPORT */ 1712 #ifdef PC98 1713 } 1714 #endif 1715 if (unit == comconsole) 1716 printf(", console"); 1717 if (COM_IIR_TXRDYBUG(flags)) 1718 printf(" with a buggy IIR_TXRDY implementation"); 1719 printf("\n"); 1720 1721 if (sio_fast_ih == NULL) { 1722 swi_add(&tty_intr_event, "sio", siopoll, NULL, SWI_TTY, 0, 1723 &sio_fast_ih); 1724 swi_add(&clk_intr_event, "sio", siopoll, NULL, SWI_CLOCK, 0, 1725 &sio_slow_ih); 1726 } 1727 1728 com->flags = flags; 1729 com->pps.ppscap = PPS_CAPTUREASSERT | PPS_CAPTURECLEAR; 1730 tp->t_pps = &com->pps; 1731 1732 if (COM_PPSCTS(flags)) 1733 com->pps_bit = MSR_CTS; 1734 else 1735 com->pps_bit = MSR_DCD; 1736 pps_init(&com->pps); 1737 1738 rid = 0; 1739 com->irqres = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, RF_ACTIVE); 1740 if (com->irqres) { 1741 ret = bus_setup_intr(dev, com->irqres, 1742 INTR_TYPE_TTY, 1743 siointr, NULL, com, &com->cookie); 1744 if (ret) { 1745 ret = bus_setup_intr(dev, 1746 com->irqres, INTR_TYPE_TTY, 1747 NULL, (driver_intr_t *)siointr, 1748 com, &com->cookie); 1749 if (ret == 0) 1750 device_printf(dev, "unable to activate interrupt in fast mode - using normal mode\n"); 1751 } 1752 if (ret) 1753 device_printf(dev, "could not activate interrupt\n"); 1754 #if defined(KDB) && (defined(BREAK_TO_DEBUGGER) || \ 1755 defined(ALT_BREAK_TO_DEBUGGER)) 1756 /* 1757 * Enable interrupts for early break-to-debugger support 1758 * on the console. 1759 */ 1760 if (ret == 0 && unit == comconsole) 1761 outb(siocniobase + com_ier, IER_ERXRDY | IER_ERLS | 1762 IER_EMSC); 1763 #endif 1764 } 1765 1766 /* We're ready, open the doors... */ 1767 ttycreate(tp, TS_CALLOUT, "d%r", unit); 1768 1769 return (0); 1770 } 1771 1772 static int 1773 comopen(struct tty *tp, struct cdev *dev) 1774 { 1775 struct com_s *com; 1776 int i; 1777 1778 com = tp->t_sc; 1779 com->poll = com->no_irq; 1780 com->poll_output = com->loses_outints; 1781 #ifdef PC98 1782 if (IS_8251(com->pc98_if_type)) { 1783 com_tiocm_bis(com, TIOCM_DTR|TIOCM_RTS); 1784 pc98_msrint_start(dev); 1785 if (com->pc98_8251fifo) { 1786 com->pc98_8251fifo_enable = 1; 1787 outb(I8251F_fcr, CTRL8251F_ENABLE | 1788 CTRL8251F_XMT_RST | CTRL8251F_RCV_RST); 1789 } 1790 } 1791 #endif 1792 if (com->hasfifo) { 1793 /* 1794 * (Re)enable and drain fifos. 1795 * 1796 * Certain SMC chips cause problems if the fifos 1797 * are enabled while input is ready. Turn off the 1798 * fifo if necessary to clear the input. We test 1799 * the input ready bit after enabling the fifos 1800 * since we've already enabled them in comparam() 1801 * and to handle races between enabling and fresh 1802 * input. 1803 */ 1804 for (i = 0; i < 500; i++) { 1805 sio_setreg(com, com_fifo, 1806 FIFO_RCV_RST | FIFO_XMT_RST 1807 | com->fifo_image); 1808 #ifdef PC98 1809 if (com->pc98_if_type == COM_IF_RSA98III) 1810 outb(com->rsabase + rsa_frr , 0x00); 1811 #endif 1812 /* 1813 * XXX the delays are for superstitious 1814 * historical reasons. It must be less than 1815 * the character time at the maximum 1816 * supported speed (87 usec at 115200 bps 1817 * 8N1). Otherwise we might loop endlessly 1818 * if data is streaming in. We used to use 1819 * delays of 100. That usually worked 1820 * because DELAY(100) used to usually delay 1821 * for about 85 usec instead of 100. 1822 */ 1823 DELAY(50); 1824 #ifdef PC98 1825 if (com->pc98_if_type == COM_IF_RSA98III ? 1826 !(inb(com->rsabase + rsa_srr) & 0x08) : 1827 !(inb(com->line_status_port) & LSR_RXRDY)) 1828 break; 1829 #else 1830 if (!(inb(com->line_status_port) & LSR_RXRDY)) 1831 break; 1832 #endif 1833 sio_setreg(com, com_fifo, 0); 1834 DELAY(50); 1835 (void) inb(com->data_port); 1836 } 1837 if (i == 500) 1838 return (EIO); 1839 } 1840 1841 mtx_lock_spin(&sio_lock); 1842 #ifdef PC98 1843 if (IS_8251(com->pc98_if_type)) { 1844 com_tiocm_bis(com, TIOCM_LE); 1845 com->pc98_prev_modem_status = pc98_get_modem_status(com); 1846 com_int_Rx_enable(com); 1847 } else { 1848 #endif 1849 (void) inb(com->line_status_port); 1850 (void) inb(com->data_port); 1851 com->prev_modem_status = com->last_modem_status 1852 = inb(com->modem_status_port); 1853 outb(com->int_ctl_port, 1854 IER_ERXRDY | IER_ERLS | IER_EMSC 1855 | (COM_IIR_TXRDYBUG(com->flags) ? 0 : IER_ETXRDY)); 1856 #ifdef PC98 1857 if (com->pc98_if_type == COM_IF_RSA98III) { 1858 outb(com->rsabase + rsa_ier, 0x1d); 1859 outb(com->int_ctl_port, IER_ERLS | IER_EMSC); 1860 } 1861 #endif 1862 #ifdef PC98 1863 } 1864 #endif 1865 mtx_unlock_spin(&sio_lock); 1866 siosettimeout(); 1867 /* XXX: should be generic ? */ 1868 #ifdef PC98 1869 if ((IS_8251(com->pc98_if_type) && 1870 (pc98_get_modem_status(com) & TIOCM_CAR)) || 1871 (!IS_8251(com->pc98_if_type) && 1872 (com->prev_modem_status & MSR_DCD)) || 1873 ISCALLOUT(dev)) 1874 ttyld_modem(tp, 1); 1875 #else 1876 if (com->prev_modem_status & MSR_DCD || ISCALLOUT(dev)) 1877 ttyld_modem(tp, 1); 1878 #endif 1879 return (0); 1880 } 1881 1882 static void 1883 comclose(tp) 1884 struct tty *tp; 1885 { 1886 int s; 1887 struct com_s *com; 1888 1889 s = spltty(); 1890 com = tp->t_sc; 1891 com->poll = FALSE; 1892 com->poll_output = FALSE; 1893 #ifdef PC98 1894 com_send_break_off(com); 1895 #else 1896 sio_setreg(com, com_cfcr, com->cfcr_image &= ~CFCR_SBREAK); 1897 #endif 1898 1899 #if defined(KDB) && (defined(BREAK_TO_DEBUGGER) || \ 1900 defined(ALT_BREAK_TO_DEBUGGER)) 1901 /* 1902 * Leave interrupts enabled and don't clear DTR if this is the 1903 * console. This allows us to detect break-to-debugger events 1904 * while the console device is closed. 1905 */ 1906 if (com->unit != comconsole) 1907 #endif 1908 { 1909 #ifdef PC98 1910 int tmp; 1911 if (IS_8251(com->pc98_if_type)) 1912 com_int_TxRx_disable(com); 1913 else 1914 sio_setreg(com, com_ier, 0); 1915 if (com->pc98_if_type == COM_IF_RSA98III) 1916 outb(com->rsabase + rsa_ier, 0x00); 1917 if (IS_8251(com->pc98_if_type)) 1918 tmp = pc98_get_modem_status(com) & TIOCM_CAR; 1919 else 1920 tmp = com->prev_modem_status & MSR_DCD; 1921 #else 1922 sio_setreg(com, com_ier, 0); 1923 #endif 1924 if (tp->t_cflag & HUPCL 1925 /* 1926 * XXX we will miss any carrier drop between here and the 1927 * next open. Perhaps we should watch DCD even when the 1928 * port is closed; it is not sufficient to check it at 1929 * the next open because it might go up and down while 1930 * we're not watching. 1931 */ 1932 || (!tp->t_actout 1933 #ifdef PC98 1934 && !(tmp) 1935 #else 1936 && !(com->prev_modem_status & MSR_DCD) 1937 #endif 1938 && !(tp->t_init_in.c_cflag & CLOCAL)) 1939 || !(tp->t_state & TS_ISOPEN)) { 1940 #ifdef PC98 1941 if (IS_8251(com->pc98_if_type)) 1942 com_tiocm_bic(com, TIOCM_DTR|TIOCM_RTS|TIOCM_LE); 1943 else 1944 #endif 1945 (void)commodem(tp, 0, SER_DTR); 1946 ttydtrwaitstart(tp); 1947 } 1948 #ifdef PC98 1949 else { 1950 if (IS_8251(com->pc98_if_type)) 1951 com_tiocm_bic(com, TIOCM_LE); 1952 } 1953 #endif 1954 } 1955 #ifdef PC98 1956 if (com->pc98_8251fifo) { 1957 if (com->pc98_8251fifo_enable) 1958 outb(I8251F_fcr, CTRL8251F_XMT_RST | CTRL8251F_RCV_RST); 1959 com->pc98_8251fifo_enable = 0; 1960 } 1961 #endif 1962 if (com->hasfifo) { 1963 /* 1964 * Disable fifos so that they are off after controlled 1965 * reboots. Some BIOSes fail to detect 16550s when the 1966 * fifos are enabled. 1967 */ 1968 sio_setreg(com, com_fifo, 0); 1969 } 1970 tp->t_actout = FALSE; 1971 wakeup(&tp->t_actout); 1972 wakeup(TSA_CARR_ON(tp)); /* restart any wopeners */ 1973 siosettimeout(); 1974 splx(s); 1975 } 1976 1977 static void 1978 siobusycheck(chan) 1979 void *chan; 1980 { 1981 struct com_s *com; 1982 int s; 1983 1984 com = (struct com_s *)chan; 1985 1986 /* 1987 * Clear TS_BUSY if low-level output is complete. 1988 * spl locking is sufficient because siointr1() does not set CS_BUSY. 1989 * If siointr1() clears CS_BUSY after we look at it, then we'll get 1990 * called again. Reading the line status port outside of siointr1() 1991 * is safe because CS_BUSY is clear so there are no output interrupts 1992 * to lose. 1993 */ 1994 s = spltty(); 1995 if (com->state & CS_BUSY) 1996 com->extra_state &= ~CSE_BUSYCHECK; /* False alarm. */ 1997 #ifdef PC98 1998 else if ((IS_8251(com->pc98_if_type) && 1999 ((com->pc98_8251fifo_enable && 2000 (inb(I8251F_lsr) & (STS8251F_TxRDY | STS8251F_TxEMP)) 2001 == (STS8251F_TxRDY | STS8251F_TxEMP)) || 2002 (!com->pc98_8251fifo_enable && 2003 (inb(com->sts_port) & (STS8251_TxRDY | STS8251_TxEMP)) 2004 == (STS8251_TxRDY | STS8251_TxEMP)))) || 2005 ((inb(com->line_status_port) & (LSR_TSRE | LSR_TXRDY)) 2006 == (LSR_TSRE | LSR_TXRDY))) { 2007 #else 2008 else if ((inb(com->line_status_port) & (LSR_TSRE | LSR_TXRDY)) 2009 == (LSR_TSRE | LSR_TXRDY)) { 2010 #endif 2011 com->tp->t_state &= ~TS_BUSY; 2012 ttwwakeup(com->tp); 2013 com->extra_state &= ~CSE_BUSYCHECK; 2014 } else 2015 timeout(siobusycheck, com, hz / 100); 2016 splx(s); 2017 } 2018 2019 static u_int 2020 siodivisor(rclk, speed) 2021 u_long rclk; 2022 speed_t speed; 2023 { 2024 long actual_speed; 2025 u_int divisor; 2026 int error; 2027 2028 if (speed == 0) 2029 return (0); 2030 #if UINT_MAX > (ULONG_MAX - 1) / 8 2031 if (speed > (ULONG_MAX - 1) / 8) 2032 return (0); 2033 #endif 2034 divisor = (rclk / (8UL * speed) + 1) / 2; 2035 if (divisor == 0 || divisor >= 65536) 2036 return (0); 2037 actual_speed = rclk / (16UL * divisor); 2038 2039 /* 10 times error in percent: */ 2040 error = ((actual_speed - (long)speed) * 2000 / (long)speed + 1) / 2; 2041 2042 /* 3.0% maximum error tolerance: */ 2043 if (error < -30 || error > 30) 2044 return (0); 2045 2046 return (divisor); 2047 } 2048 2049 /* 2050 * Call this function with the sio_lock mutex held. It will return with the 2051 * lock still held. 2052 */ 2053 static void 2054 sioinput(com) 2055 struct com_s *com; 2056 { 2057 u_char *buf; 2058 int incc; 2059 u_char line_status; 2060 int recv_data; 2061 struct tty *tp; 2062 2063 buf = com->ibuf; 2064 tp = com->tp; 2065 if (!(tp->t_state & TS_ISOPEN) || !(tp->t_cflag & CREAD)) { 2066 com_events -= (com->iptr - com->ibuf); 2067 com->iptr = com->ibuf; 2068 return; 2069 } 2070 if (tp->t_state & TS_CAN_BYPASS_L_RINT) { 2071 /* 2072 * Avoid the grotesquely inefficient lineswitch routine 2073 * (ttyinput) in "raw" mode. It usually takes about 450 2074 * instructions (that's without canonical processing or echo!). 2075 * slinput is reasonably fast (usually 40 instructions plus 2076 * call overhead). 2077 */ 2078 do { 2079 /* 2080 * This may look odd, but it is using save-and-enable 2081 * semantics instead of the save-and-disable semantics 2082 * that are used everywhere else. 2083 */ 2084 mtx_unlock_spin(&sio_lock); 2085 incc = com->iptr - buf; 2086 if (tp->t_rawq.c_cc + incc > tp->t_ihiwat 2087 && (com->state & CS_RTS_IFLOW 2088 || tp->t_iflag & IXOFF) 2089 && !(tp->t_state & TS_TBLOCK)) 2090 ttyblock(tp); 2091 com->delta_error_counts[CE_TTY_BUF_OVERFLOW] 2092 += b_to_q((char *)buf, incc, &tp->t_rawq); 2093 buf += incc; 2094 tk_nin += incc; 2095 tk_rawcc += incc; 2096 tp->t_rawcc += incc; 2097 ttwakeup(tp); 2098 if (tp->t_state & TS_TTSTOP 2099 && (tp->t_iflag & IXANY 2100 || tp->t_cc[VSTART] == tp->t_cc[VSTOP])) { 2101 tp->t_state &= ~TS_TTSTOP; 2102 tp->t_lflag &= ~FLUSHO; 2103 comstart(tp); 2104 } 2105 mtx_lock_spin(&sio_lock); 2106 } while (buf < com->iptr); 2107 } else { 2108 do { 2109 /* 2110 * This may look odd, but it is using save-and-enable 2111 * semantics instead of the save-and-disable semantics 2112 * that are used everywhere else. 2113 */ 2114 mtx_unlock_spin(&sio_lock); 2115 line_status = buf[com->ierroff]; 2116 recv_data = *buf++; 2117 if (line_status 2118 & (LSR_BI | LSR_FE | LSR_OE | LSR_PE)) { 2119 if (line_status & LSR_BI) 2120 recv_data |= TTY_BI; 2121 if (line_status & LSR_FE) 2122 recv_data |= TTY_FE; 2123 if (line_status & LSR_OE) 2124 recv_data |= TTY_OE; 2125 if (line_status & LSR_PE) 2126 recv_data |= TTY_PE; 2127 } 2128 ttyld_rint(tp, recv_data); 2129 mtx_lock_spin(&sio_lock); 2130 } while (buf < com->iptr); 2131 } 2132 com_events -= (com->iptr - com->ibuf); 2133 com->iptr = com->ibuf; 2134 2135 /* 2136 * There is now room for another low-level buffer full of input, 2137 * so enable RTS if it is now disabled and there is room in the 2138 * high-level buffer. 2139 */ 2140 #ifdef PC98 2141 if (IS_8251(com->pc98_if_type)) { 2142 if ((com->state & CS_RTS_IFLOW) && 2143 !(com_tiocm_get(com) & TIOCM_RTS) && 2144 !(tp->t_state & TS_TBLOCK)) 2145 com_tiocm_bis(com, TIOCM_RTS); 2146 } else { 2147 if ((com->state & CS_RTS_IFLOW) && 2148 !(com->mcr_image & MCR_RTS) && 2149 !(tp->t_state & TS_TBLOCK)) 2150 outb(com->modem_ctl_port, com->mcr_image |= MCR_RTS); 2151 } 2152 #else 2153 if ((com->state & CS_RTS_IFLOW) && !(com->mcr_image & MCR_RTS) && 2154 !(tp->t_state & TS_TBLOCK)) 2155 outb(com->modem_ctl_port, com->mcr_image |= MCR_RTS); 2156 #endif 2157 } 2158 2159 static int 2160 siointr(arg) 2161 void *arg; 2162 { 2163 struct com_s *com; 2164 #if defined(PC98) && defined(COM_MULTIPORT) 2165 u_char rsa_buf_status; 2166 #endif 2167 2168 #ifndef COM_MULTIPORT 2169 com = (struct com_s *)arg; 2170 2171 mtx_lock_spin(&sio_lock); 2172 siointr1(com); 2173 mtx_unlock_spin(&sio_lock); 2174 #else /* COM_MULTIPORT */ 2175 bool_t possibly_more_intrs; 2176 int unit; 2177 2178 /* 2179 * Loop until there is no activity on any port. This is necessary 2180 * to get an interrupt edge more than to avoid another interrupt. 2181 * If the IRQ signal is just an OR of the IRQ signals from several 2182 * devices, then the edge from one may be lost because another is 2183 * on. 2184 */ 2185 mtx_lock_spin(&sio_lock); 2186 do { 2187 possibly_more_intrs = FALSE; 2188 for (unit = 0; unit < sio_numunits; ++unit) { 2189 com = com_addr(unit); 2190 /* 2191 * XXX COM_LOCK(); 2192 * would it work here, or be counter-productive? 2193 */ 2194 #ifdef PC98 2195 if (com != NULL 2196 && !com->gone 2197 && IS_8251(com->pc98_if_type)) { 2198 siointr1(com); 2199 } else if (com != NULL 2200 && !com->gone 2201 && com->pc98_if_type == COM_IF_RSA98III) { 2202 rsa_buf_status = 2203 inb(com->rsabase + rsa_srr) & 0xc9; 2204 if ((rsa_buf_status & 0xc8) 2205 || !(rsa_buf_status & 0x01)) { 2206 siointr1(com); 2207 if (rsa_buf_status != 2208 (inb(com->rsabase + rsa_srr) & 0xc9)) 2209 possibly_more_intrs = TRUE; 2210 } 2211 } else 2212 #endif 2213 if (com != NULL 2214 && !com->gone 2215 && (inb(com->int_id_port) & IIR_IMASK) 2216 != IIR_NOPEND) { 2217 siointr1(com); 2218 possibly_more_intrs = TRUE; 2219 } 2220 /* XXX COM_UNLOCK(); */ 2221 } 2222 } while (possibly_more_intrs); 2223 mtx_unlock_spin(&sio_lock); 2224 #endif /* COM_MULTIPORT */ 2225 return (FILTER_HANDLED); 2226 } 2227 2228 static struct timespec siots[8]; 2229 static int siotso; 2230 static int volatile siotsunit = -1; 2231 2232 static int 2233 sysctl_siots(SYSCTL_HANDLER_ARGS) 2234 { 2235 char buf[128]; 2236 long long delta; 2237 size_t len; 2238 int error, i, tso; 2239 2240 for (i = 1, tso = siotso; i < tso; i++) { 2241 delta = (long long)(siots[i].tv_sec - siots[i - 1].tv_sec) * 2242 1000000000 + 2243 (siots[i].tv_nsec - siots[i - 1].tv_nsec); 2244 len = sprintf(buf, "%lld\n", delta); 2245 if (delta >= 110000) 2246 len += sprintf(buf + len - 1, ": *** %ld.%09ld\n", 2247 (long)siots[i].tv_sec, siots[i].tv_nsec) - 1; 2248 if (i == tso - 1) 2249 buf[len - 1] = '\0'; 2250 error = SYSCTL_OUT(req, buf, len); 2251 if (error != 0) 2252 return (error); 2253 uio_yield(); 2254 } 2255 return (0); 2256 } 2257 2258 SYSCTL_PROC(_machdep, OID_AUTO, siots, CTLTYPE_STRING | CTLFLAG_RD, 2259 0, 0, sysctl_siots, "A", "sio timestamps"); 2260 2261 static void 2262 siointr1(com) 2263 struct com_s *com; 2264 { 2265 u_char int_ctl; 2266 u_char int_ctl_new; 2267 u_char line_status; 2268 u_char modem_status; 2269 u_char *ioptr; 2270 u_char recv_data; 2271 2272 #ifdef PC98 2273 u_char tmp = 0; 2274 u_char rsa_buf_status = 0; 2275 int rsa_tx_fifo_size = 0; 2276 #endif /* PC98 */ 2277 2278 if (COM_IIR_TXRDYBUG(com->flags)) { 2279 int_ctl = inb(com->int_ctl_port); 2280 int_ctl_new = int_ctl; 2281 } else { 2282 int_ctl = 0; 2283 int_ctl_new = 0; 2284 } 2285 2286 while (!com->gone) { 2287 #ifdef PC98 2288 status_read:; 2289 if (IS_8251(com->pc98_if_type)) { 2290 if (com->pc98_8251fifo_enable) 2291 tmp = inb(I8251F_lsr); 2292 else 2293 tmp = inb(com->sts_port); 2294 more_intr: 2295 line_status = 0; 2296 if (com->pc98_8251fifo_enable) { 2297 if (tmp & STS8251F_TxRDY) line_status |= LSR_TXRDY; 2298 if (tmp & STS8251F_RxRDY) line_status |= LSR_RXRDY; 2299 if (tmp & STS8251F_TxEMP) line_status |= LSR_TSRE; 2300 if (tmp & STS8251F_PE) line_status |= LSR_PE; 2301 if (tmp & STS8251F_OE) line_status |= LSR_OE; 2302 if (tmp & STS8251F_BD_SD) line_status |= LSR_BI; 2303 } else { 2304 if (tmp & STS8251_TxRDY) line_status |= LSR_TXRDY; 2305 if (tmp & STS8251_RxRDY) line_status |= LSR_RXRDY; 2306 if (tmp & STS8251_TxEMP) line_status |= LSR_TSRE; 2307 if (tmp & STS8251_PE) line_status |= LSR_PE; 2308 if (tmp & STS8251_OE) line_status |= LSR_OE; 2309 if (tmp & STS8251_FE) line_status |= LSR_FE; 2310 if (tmp & STS8251_BD_SD) line_status |= LSR_BI; 2311 } 2312 } else { 2313 #endif /* PC98 */ 2314 if (com->pps.ppsparam.mode & PPS_CAPTUREBOTH) { 2315 modem_status = inb(com->modem_status_port); 2316 if ((modem_status ^ com->last_modem_status) & 2317 com->pps_bit) { 2318 pps_capture(&com->pps); 2319 pps_event(&com->pps, 2320 (modem_status & com->pps_bit) ? 2321 PPS_CAPTUREASSERT : PPS_CAPTURECLEAR); 2322 } 2323 } 2324 line_status = inb(com->line_status_port); 2325 #ifdef PC98 2326 } 2327 if (com->pc98_if_type == COM_IF_RSA98III) 2328 rsa_buf_status = inb(com->rsabase + rsa_srr); 2329 #endif /* PC98 */ 2330 2331 /* input event? (check first to help avoid overruns) */ 2332 #ifndef PC98 2333 while (line_status & LSR_RCV_MASK) { 2334 #else 2335 while ((line_status & LSR_RCV_MASK) 2336 || (com->pc98_if_type == COM_IF_RSA98III 2337 && (rsa_buf_status & 0x08))) { 2338 #endif /* PC98 */ 2339 /* break/unnattached error bits or real input? */ 2340 #ifdef PC98 2341 if (IS_8251(com->pc98_if_type)) { 2342 if (com->pc98_8251fifo_enable) { 2343 recv_data = inb(I8251F_data); 2344 if (tmp & (STS8251F_PE | STS8251F_OE | 2345 STS8251F_BD_SD)) { 2346 pc98_i8251_or_cmd(com, CMD8251_ER); 2347 recv_data = 0; 2348 } 2349 } else { 2350 recv_data = inb(com->data_port); 2351 if (tmp & (STS8251_PE | STS8251_OE | 2352 STS8251_FE | STS8251_BD_SD)) { 2353 pc98_i8251_or_cmd(com, CMD8251_ER); 2354 recv_data = 0; 2355 } 2356 } 2357 } else if (com->pc98_if_type == COM_IF_RSA98III) { 2358 if (!(rsa_buf_status & 0x08)) 2359 recv_data = 0; 2360 else 2361 recv_data = inb(com->data_port); 2362 } else 2363 #endif 2364 if (!(line_status & LSR_RXRDY)) 2365 recv_data = 0; 2366 else 2367 recv_data = inb(com->data_port); 2368 #ifdef KDB 2369 #ifdef ALT_BREAK_TO_DEBUGGER 2370 if (com->unit == comconsole && 2371 kdb_alt_break(recv_data, &com->alt_brk_state) != 0) 2372 kdb_enter_why(KDB_WHY_BREAK, 2373 "Break sequence on console"); 2374 #endif /* ALT_BREAK_TO_DEBUGGER */ 2375 #endif /* KDB */ 2376 if (line_status & (LSR_BI | LSR_FE | LSR_PE)) { 2377 /* 2378 * Don't store BI if IGNBRK or FE/PE if IGNPAR. 2379 * Otherwise, push the work to a higher level 2380 * (to handle PARMRK) if we're bypassing. 2381 * Otherwise, convert BI/FE and PE+INPCK to 0. 2382 * 2383 * This makes bypassing work right in the 2384 * usual "raw" case (IGNBRK set, and IGNPAR 2385 * and INPCK clear). 2386 * 2387 * Note: BI together with FE/PE means just BI. 2388 */ 2389 if (line_status & LSR_BI) { 2390 #if defined(KDB) && defined(BREAK_TO_DEBUGGER) 2391 if (com->unit == comconsole) { 2392 kdb_enter_why(KDB_WHY_BREAK, 2393 "Line break on console"); 2394 goto cont; 2395 } 2396 #endif 2397 if (com->tp == NULL 2398 || com->tp->t_iflag & IGNBRK) 2399 goto cont; 2400 } else { 2401 if (com->tp == NULL 2402 || com->tp->t_iflag & IGNPAR) 2403 goto cont; 2404 } 2405 if (com->tp->t_state & TS_CAN_BYPASS_L_RINT 2406 && (line_status & (LSR_BI | LSR_FE) 2407 || com->tp->t_iflag & INPCK)) 2408 recv_data = 0; 2409 } 2410 ++com->bytes_in; 2411 if (com->tp != NULL && 2412 com->tp->t_hotchar != 0 && recv_data == com->tp->t_hotchar) 2413 swi_sched(sio_fast_ih, 0); 2414 ioptr = com->iptr; 2415 if (ioptr >= com->ibufend) 2416 CE_RECORD(com, CE_INTERRUPT_BUF_OVERFLOW); 2417 else { 2418 if (com->tp != NULL && com->tp->t_do_timestamp) 2419 microtime(&com->tp->t_timestamp); 2420 ++com_events; 2421 swi_sched(sio_slow_ih, SWI_DELAY); 2422 #if 0 /* for testing input latency vs efficiency */ 2423 if (com->iptr - com->ibuf == 8) 2424 swi_sched(sio_fast_ih, 0); 2425 #endif 2426 ioptr[0] = recv_data; 2427 ioptr[com->ierroff] = line_status; 2428 com->iptr = ++ioptr; 2429 if (ioptr == com->ihighwater 2430 && com->state & CS_RTS_IFLOW) 2431 #ifdef PC98 2432 IS_8251(com->pc98_if_type) ? 2433 com_tiocm_bic(com, TIOCM_RTS) : 2434 #endif 2435 outb(com->modem_ctl_port, 2436 com->mcr_image &= ~MCR_RTS); 2437 if (line_status & LSR_OE) 2438 CE_RECORD(com, CE_OVERRUN); 2439 } 2440 cont: 2441 if (line_status & LSR_TXRDY 2442 && com->state >= (CS_BUSY | CS_TTGO | CS_ODEVREADY)) 2443 goto txrdy; 2444 2445 /* 2446 * "& 0x7F" is to avoid the gcc-1.40 generating a slow 2447 * jump from the top of the loop to here 2448 */ 2449 #ifdef PC98 2450 if (IS_8251(com->pc98_if_type)) 2451 goto status_read; 2452 else 2453 #endif 2454 line_status = inb(com->line_status_port) & 0x7F; 2455 #ifdef PC98 2456 if (com->pc98_if_type == COM_IF_RSA98III) 2457 rsa_buf_status = inb(com->rsabase + rsa_srr); 2458 #endif /* PC98 */ 2459 } 2460 2461 /* modem status change? (always check before doing output) */ 2462 #ifdef PC98 2463 if (!IS_8251(com->pc98_if_type)) { 2464 #endif 2465 modem_status = inb(com->modem_status_port); 2466 if (modem_status != com->last_modem_status) { 2467 /* 2468 * Schedule high level to handle DCD changes. Note 2469 * that we don't use the delta bits anywhere. Some 2470 * UARTs mess them up, and it's easy to remember the 2471 * previous bits and calculate the delta. 2472 */ 2473 com->last_modem_status = modem_status; 2474 if (!(com->state & CS_CHECKMSR)) { 2475 com_events += LOTS_OF_EVENTS; 2476 com->state |= CS_CHECKMSR; 2477 swi_sched(sio_fast_ih, 0); 2478 } 2479 2480 /* handle CTS change immediately for crisp flow ctl */ 2481 if (com->state & CS_CTS_OFLOW) { 2482 if (modem_status & MSR_CTS) 2483 com->state |= CS_ODEVREADY; 2484 else 2485 com->state &= ~CS_ODEVREADY; 2486 } 2487 } 2488 #ifdef PC98 2489 } 2490 #endif 2491 2492 txrdy: 2493 /* output queued and everything ready? */ 2494 #ifndef PC98 2495 if (line_status & LSR_TXRDY 2496 && com->state >= (CS_BUSY | CS_TTGO | CS_ODEVREADY)) { 2497 #else 2498 if (((com->pc98_if_type == COM_IF_RSA98III) 2499 ? (rsa_buf_status & 0x02) 2500 : (line_status & LSR_TXRDY)) 2501 && com->state >= (CS_BUSY | CS_TTGO | CS_ODEVREADY)) { 2502 #endif 2503 #ifdef PC98 2504 Port_t tmp_data_port; 2505 2506 if (IS_8251(com->pc98_if_type) && 2507 com->pc98_8251fifo_enable) 2508 tmp_data_port = I8251F_data; 2509 else 2510 tmp_data_port = com->data_port; 2511 #endif 2512 2513 ioptr = com->obufq.l_head; 2514 if (com->tx_fifo_size > 1 && com->unit != siotsunit) { 2515 u_int ocount; 2516 2517 ocount = com->obufq.l_tail - ioptr; 2518 #ifdef PC98 2519 if (com->pc98_if_type == COM_IF_RSA98III) { 2520 rsa_buf_status = inb(com->rsabase + rsa_srr); 2521 rsa_tx_fifo_size = 1024; 2522 if (!(rsa_buf_status & 0x01)) 2523 rsa_tx_fifo_size = 2048; 2524 if (ocount > rsa_tx_fifo_size) 2525 ocount = rsa_tx_fifo_size; 2526 } else 2527 #endif 2528 if (ocount > com->tx_fifo_size) 2529 ocount = com->tx_fifo_size; 2530 com->bytes_out += ocount; 2531 do 2532 #ifdef PC98 2533 outb(tmp_data_port, *ioptr++); 2534 #else 2535 outb(com->data_port, *ioptr++); 2536 #endif 2537 while (--ocount != 0); 2538 } else { 2539 #ifdef PC98 2540 outb(tmp_data_port, *ioptr++); 2541 #else 2542 outb(com->data_port, *ioptr++); 2543 #endif 2544 ++com->bytes_out; 2545 if (com->unit == siotsunit 2546 && siotso < sizeof siots / sizeof siots[0]) 2547 nanouptime(&siots[siotso++]); 2548 } 2549 #ifdef PC98 2550 if (IS_8251(com->pc98_if_type)) 2551 if (!(pc98_check_i8251_interrupt(com) & IEN_TxFLAG)) 2552 com_int_Tx_enable(com); 2553 #endif 2554 com->obufq.l_head = ioptr; 2555 if (COM_IIR_TXRDYBUG(com->flags)) 2556 int_ctl_new = int_ctl | IER_ETXRDY; 2557 if (ioptr >= com->obufq.l_tail) { 2558 struct lbq *qp; 2559 2560 qp = com->obufq.l_next; 2561 qp->l_queued = FALSE; 2562 qp = qp->l_next; 2563 if (qp != NULL) { 2564 com->obufq.l_head = qp->l_head; 2565 com->obufq.l_tail = qp->l_tail; 2566 com->obufq.l_next = qp; 2567 } else { 2568 /* output just completed */ 2569 if (COM_IIR_TXRDYBUG(com->flags)) 2570 int_ctl_new = int_ctl 2571 & ~IER_ETXRDY; 2572 com->state &= ~CS_BUSY; 2573 #if defined(PC98) 2574 if (IS_8251(com->pc98_if_type) && 2575 pc98_check_i8251_interrupt(com) & IEN_TxFLAG) 2576 com_int_Tx_disable(com); 2577 #endif 2578 } 2579 if (!(com->state & CS_ODONE)) { 2580 com_events += LOTS_OF_EVENTS; 2581 com->state |= CS_ODONE; 2582 /* handle at high level ASAP */ 2583 swi_sched(sio_fast_ih, 0); 2584 } 2585 } 2586 #ifdef PC98 2587 if (COM_IIR_TXRDYBUG(com->flags) 2588 && int_ctl != int_ctl_new) { 2589 if (com->pc98_if_type == COM_IF_RSA98III) { 2590 int_ctl_new &= ~(IER_ETXRDY | IER_ERXRDY); 2591 outb(com->int_ctl_port, int_ctl_new); 2592 outb(com->rsabase + rsa_ier, 0x1d); 2593 } else 2594 outb(com->int_ctl_port, int_ctl_new); 2595 } 2596 #else 2597 if (COM_IIR_TXRDYBUG(com->flags) 2598 && int_ctl != int_ctl_new) 2599 outb(com->int_ctl_port, int_ctl_new); 2600 #endif 2601 } 2602 #ifdef PC98 2603 else if (line_status & LSR_TXRDY) { 2604 if (IS_8251(com->pc98_if_type)) 2605 if (pc98_check_i8251_interrupt(com) & IEN_TxFLAG) 2606 com_int_Tx_disable(com); 2607 } 2608 if (IS_8251(com->pc98_if_type)) { 2609 if (com->pc98_8251fifo_enable) { 2610 if ((tmp = inb(I8251F_lsr)) & STS8251F_RxRDY) 2611 goto more_intr; 2612 } else { 2613 if ((tmp = inb(com->sts_port)) & STS8251_RxRDY) 2614 goto more_intr; 2615 } 2616 } 2617 #endif 2618 2619 /* finished? */ 2620 #ifndef COM_MULTIPORT 2621 #ifdef PC98 2622 if (IS_8251(com->pc98_if_type)) 2623 return; 2624 #endif 2625 if ((inb(com->int_id_port) & IIR_IMASK) == IIR_NOPEND) 2626 #endif /* COM_MULTIPORT */ 2627 return; 2628 } 2629 } 2630 2631 /* software interrupt handler for SWI_TTY */ 2632 static void 2633 siopoll(void *dummy) 2634 { 2635 int unit; 2636 2637 if (com_events == 0) 2638 return; 2639 repeat: 2640 for (unit = 0; unit < sio_numunits; ++unit) { 2641 struct com_s *com; 2642 int incc; 2643 struct tty *tp; 2644 2645 com = com_addr(unit); 2646 if (com == NULL) 2647 continue; 2648 tp = com->tp; 2649 if (tp == NULL || com->gone) { 2650 /* 2651 * Discard any events related to never-opened or 2652 * going-away devices. 2653 */ 2654 mtx_lock_spin(&sio_lock); 2655 incc = com->iptr - com->ibuf; 2656 com->iptr = com->ibuf; 2657 if (com->state & CS_CHECKMSR) { 2658 incc += LOTS_OF_EVENTS; 2659 com->state &= ~CS_CHECKMSR; 2660 } 2661 com_events -= incc; 2662 mtx_unlock_spin(&sio_lock); 2663 continue; 2664 } 2665 if (com->iptr != com->ibuf) { 2666 mtx_lock_spin(&sio_lock); 2667 sioinput(com); 2668 mtx_unlock_spin(&sio_lock); 2669 } 2670 if (com->state & CS_CHECKMSR) { 2671 u_char delta_modem_status; 2672 2673 #ifdef PC98 2674 if (!IS_8251(com->pc98_if_type)) { 2675 #endif 2676 mtx_lock_spin(&sio_lock); 2677 delta_modem_status = com->last_modem_status 2678 ^ com->prev_modem_status; 2679 com->prev_modem_status = com->last_modem_status; 2680 com_events -= LOTS_OF_EVENTS; 2681 com->state &= ~CS_CHECKMSR; 2682 mtx_unlock_spin(&sio_lock); 2683 if (delta_modem_status & MSR_DCD) 2684 ttyld_modem(tp, 2685 com->prev_modem_status & MSR_DCD); 2686 #ifdef PC98 2687 } 2688 #endif 2689 } 2690 if (com->state & CS_ODONE) { 2691 mtx_lock_spin(&sio_lock); 2692 com_events -= LOTS_OF_EVENTS; 2693 com->state &= ~CS_ODONE; 2694 mtx_unlock_spin(&sio_lock); 2695 if (!(com->state & CS_BUSY) 2696 && !(com->extra_state & CSE_BUSYCHECK)) { 2697 timeout(siobusycheck, com, hz / 100); 2698 com->extra_state |= CSE_BUSYCHECK; 2699 } 2700 ttyld_start(tp); 2701 } 2702 if (com_events == 0) 2703 break; 2704 } 2705 if (com_events >= LOTS_OF_EVENTS) 2706 goto repeat; 2707 } 2708 2709 static void 2710 combreak(tp, sig) 2711 struct tty *tp; 2712 int sig; 2713 { 2714 struct com_s *com; 2715 2716 com = tp->t_sc; 2717 2718 #ifdef PC98 2719 if (sig) 2720 com_send_break_on(com); 2721 else 2722 com_send_break_off(com); 2723 #else 2724 if (sig) 2725 sio_setreg(com, com_cfcr, com->cfcr_image |= CFCR_SBREAK); 2726 else 2727 sio_setreg(com, com_cfcr, com->cfcr_image &= ~CFCR_SBREAK); 2728 #endif 2729 } 2730 2731 static int 2732 comparam(tp, t) 2733 struct tty *tp; 2734 struct termios *t; 2735 { 2736 u_int cfcr; 2737 int cflag; 2738 struct com_s *com; 2739 u_int divisor; 2740 u_char dlbh; 2741 u_char dlbl; 2742 u_char efr_flowbits; 2743 int s; 2744 #ifdef PC98 2745 u_char param = 0; 2746 #endif 2747 2748 com = tp->t_sc; 2749 if (com == NULL) 2750 return (ENODEV); 2751 2752 #ifdef PC98 2753 cfcr = 0; 2754 2755 if (IS_8251(com->pc98_if_type)) { 2756 if (pc98_ttspeedtab(com, t->c_ospeed, &divisor) != 0) 2757 return (EINVAL); 2758 } else { 2759 #endif 2760 /* check requested parameters */ 2761 if (t->c_ispeed != (t->c_ospeed != 0 ? t->c_ospeed : tp->t_ospeed)) 2762 return (EINVAL); 2763 divisor = siodivisor(com->rclk, t->c_ispeed); 2764 if (divisor == 0) 2765 return (EINVAL); 2766 #ifdef PC98 2767 } 2768 #endif 2769 2770 /* parameters are OK, convert them to the com struct and the device */ 2771 s = spltty(); 2772 #ifdef PC98 2773 if (IS_8251(com->pc98_if_type)) { 2774 if (t->c_ospeed == 0) 2775 com_tiocm_bic(com, TIOCM_DTR|TIOCM_RTS|TIOCM_LE); 2776 else 2777 com_tiocm_bis(com, TIOCM_DTR|TIOCM_RTS|TIOCM_LE); 2778 } else 2779 #endif 2780 if (t->c_ospeed == 0) 2781 (void)commodem(tp, 0, SER_DTR); /* hang up line */ 2782 else 2783 (void)commodem(tp, SER_DTR, 0); 2784 cflag = t->c_cflag; 2785 #ifdef PC98 2786 if (!IS_8251(com->pc98_if_type)) { 2787 #endif 2788 switch (cflag & CSIZE) { 2789 case CS5: 2790 cfcr = CFCR_5BITS; 2791 break; 2792 case CS6: 2793 cfcr = CFCR_6BITS; 2794 break; 2795 case CS7: 2796 cfcr = CFCR_7BITS; 2797 break; 2798 default: 2799 cfcr = CFCR_8BITS; 2800 break; 2801 } 2802 if (cflag & PARENB) { 2803 cfcr |= CFCR_PENAB; 2804 if (!(cflag & PARODD)) 2805 cfcr |= CFCR_PEVEN; 2806 } 2807 if (cflag & CSTOPB) 2808 cfcr |= CFCR_STOPB; 2809 2810 if (com->hasfifo) { 2811 /* 2812 * Use a fifo trigger level low enough so that the input 2813 * latency from the fifo is less than about 16 msec and 2814 * the total latency is less than about 30 msec. These 2815 * latencies are reasonable for humans. Serial comms 2816 * protocols shouldn't expect anything better since modem 2817 * latencies are larger. 2818 * 2819 * The fifo trigger level cannot be set at RX_HIGH for high 2820 * speed connections without further work on reducing 2821 * interrupt disablement times in other parts of the system, 2822 * without producing silo overflow errors. 2823 */ 2824 com->fifo_image = com->unit == siotsunit ? 0 2825 : t->c_ispeed <= 4800 2826 ? FIFO_ENABLE : FIFO_ENABLE | FIFO_RX_MEDH; 2827 #ifdef COM_ESP 2828 /* 2829 * The Hayes ESP card needs the fifo DMA mode bit set 2830 * in compatibility mode. If not, it will interrupt 2831 * for each character received. 2832 */ 2833 if (com->esp) 2834 com->fifo_image |= FIFO_DMA_MODE; 2835 #endif 2836 sio_setreg(com, com_fifo, com->fifo_image); 2837 } 2838 #ifdef PC98 2839 } 2840 #endif 2841 2842 /* 2843 * This returns with interrupts disabled so that we can complete 2844 * the speed change atomically. Keeping interrupts disabled is 2845 * especially important while com_data is hidden. 2846 */ 2847 (void) siosetwater(com, t->c_ispeed); 2848 2849 #ifdef PC98 2850 if (IS_8251(com->pc98_if_type)) 2851 com_cflag_and_speed_set(com, cflag, t->c_ospeed); 2852 else { 2853 #endif 2854 sio_setreg(com, com_cfcr, cfcr | CFCR_DLAB); 2855 /* 2856 * Only set the divisor registers if they would change, since on 2857 * some 16550 incompatibles (UMC8669F), setting them while input 2858 * is arriving loses sync until data stops arriving. 2859 */ 2860 dlbl = divisor & 0xFF; 2861 if (sio_getreg(com, com_dlbl) != dlbl) 2862 sio_setreg(com, com_dlbl, dlbl); 2863 dlbh = divisor >> 8; 2864 if (sio_getreg(com, com_dlbh) != dlbh) 2865 sio_setreg(com, com_dlbh, dlbh); 2866 #ifdef PC98 2867 } 2868 #endif 2869 2870 efr_flowbits = 0; 2871 2872 if (cflag & CRTS_IFLOW) { 2873 com->state |= CS_RTS_IFLOW; 2874 efr_flowbits |= EFR_AUTORTS; 2875 /* 2876 * If CS_RTS_IFLOW just changed from off to on, the change 2877 * needs to be propagated to MCR_RTS. This isn't urgent, 2878 * so do it later by calling comstart() instead of repeating 2879 * a lot of code from comstart() here. 2880 */ 2881 } else if (com->state & CS_RTS_IFLOW) { 2882 com->state &= ~CS_RTS_IFLOW; 2883 /* 2884 * CS_RTS_IFLOW just changed from on to off. Force MCR_RTS 2885 * on here, since comstart() won't do it later. 2886 */ 2887 #ifdef PC98 2888 if (IS_8251(com->pc98_if_type)) 2889 com_tiocm_bis(com, TIOCM_RTS); 2890 else 2891 outb(com->modem_ctl_port, com->mcr_image |= MCR_RTS); 2892 #else 2893 outb(com->modem_ctl_port, com->mcr_image |= MCR_RTS); 2894 #endif 2895 } 2896 2897 /* 2898 * Set up state to handle output flow control. 2899 * XXX - worth handling MDMBUF (DCD) flow control at the lowest level? 2900 * Now has 10+ msec latency, while CTS flow has 50- usec latency. 2901 */ 2902 com->state |= CS_ODEVREADY; 2903 com->state &= ~CS_CTS_OFLOW; 2904 #ifdef PC98 2905 if (com->pc98_if_type == COM_IF_RSA98III) { 2906 param = inb(com->rsabase + rsa_msr); 2907 outb(com->rsabase + rsa_msr, param & 0x14); 2908 } 2909 #endif 2910 if (cflag & CCTS_OFLOW) { 2911 com->state |= CS_CTS_OFLOW; 2912 efr_flowbits |= EFR_AUTOCTS; 2913 #ifdef PC98 2914 if (IS_8251(com->pc98_if_type)) { 2915 if (!(pc98_get_modem_status(com) & TIOCM_CTS)) 2916 com->state &= ~CS_ODEVREADY; 2917 } else if (com->pc98_if_type == COM_IF_RSA98III) { 2918 /* Set automatic flow control mode */ 2919 outb(com->rsabase + rsa_msr, param | 0x08); 2920 } else 2921 #endif 2922 if (!(com->last_modem_status & MSR_CTS)) 2923 com->state &= ~CS_ODEVREADY; 2924 } 2925 2926 #ifdef PC98 2927 if (!IS_8251(com->pc98_if_type)) 2928 sio_setreg(com, com_cfcr, com->cfcr_image = cfcr); 2929 #else 2930 if (com->st16650a) { 2931 sio_setreg(com, com_lcr, LCR_EFR_ENABLE); 2932 sio_setreg(com, com_efr, 2933 (sio_getreg(com, com_efr) 2934 & ~(EFR_AUTOCTS | EFR_AUTORTS)) | efr_flowbits); 2935 } 2936 sio_setreg(com, com_cfcr, com->cfcr_image = cfcr); 2937 #endif 2938 2939 /* XXX shouldn't call functions while intrs are disabled. */ 2940 ttyldoptim(tp); 2941 2942 mtx_unlock_spin(&sio_lock); 2943 splx(s); 2944 comstart(tp); 2945 if (com->ibufold != NULL) { 2946 free(com->ibufold, M_DEVBUF); 2947 com->ibufold = NULL; 2948 } 2949 return (0); 2950 } 2951 2952 /* 2953 * This function must be called with the sio_lock mutex released and will 2954 * return with it obtained. 2955 */ 2956 static int 2957 siosetwater(com, speed) 2958 struct com_s *com; 2959 speed_t speed; 2960 { 2961 int cp4ticks; 2962 u_char *ibuf; 2963 int ibufsize; 2964 struct tty *tp; 2965 2966 /* 2967 * Make the buffer size large enough to handle a softtty interrupt 2968 * latency of about 2 ticks without loss of throughput or data 2969 * (about 3 ticks if input flow control is not used or not honoured, 2970 * but a bit less for CS5-CS7 modes). 2971 */ 2972 cp4ticks = speed / 10 / hz * 4; 2973 for (ibufsize = 128; ibufsize < cp4ticks;) 2974 ibufsize <<= 1; 2975 #ifdef PC98 2976 if (com->pc98_if_type == COM_IF_RSA98III) 2977 ibufsize = 2048; 2978 #endif 2979 if (ibufsize == com->ibufsize) { 2980 mtx_lock_spin(&sio_lock); 2981 return (0); 2982 } 2983 2984 /* 2985 * Allocate input buffer. The extra factor of 2 in the size is 2986 * to allow for an error byte for each input byte. 2987 */ 2988 ibuf = malloc(2 * ibufsize, M_DEVBUF, M_NOWAIT); 2989 if (ibuf == NULL) { 2990 mtx_lock_spin(&sio_lock); 2991 return (ENOMEM); 2992 } 2993 2994 /* Initialize non-critical variables. */ 2995 com->ibufold = com->ibuf; 2996 com->ibufsize = ibufsize; 2997 tp = com->tp; 2998 if (tp != NULL) { 2999 tp->t_ififosize = 2 * ibufsize; 3000 tp->t_ispeedwat = (speed_t)-1; 3001 tp->t_ospeedwat = (speed_t)-1; 3002 } 3003 3004 /* 3005 * Read current input buffer, if any. Continue with interrupts 3006 * disabled. 3007 */ 3008 mtx_lock_spin(&sio_lock); 3009 if (com->iptr != com->ibuf) 3010 sioinput(com); 3011 3012 /*- 3013 * Initialize critical variables, including input buffer watermarks. 3014 * The external device is asked to stop sending when the buffer 3015 * exactly reaches high water, or when the high level requests it. 3016 * The high level is notified immediately (rather than at a later 3017 * clock tick) when this watermark is reached. 3018 * The buffer size is chosen so the watermark should almost never 3019 * be reached. 3020 * The low watermark is invisibly 0 since the buffer is always 3021 * emptied all at once. 3022 */ 3023 com->iptr = com->ibuf = ibuf; 3024 com->ibufend = ibuf + ibufsize; 3025 com->ierroff = ibufsize; 3026 com->ihighwater = ibuf + 3 * ibufsize / 4; 3027 return (0); 3028 } 3029 3030 static void 3031 comstart(tp) 3032 struct tty *tp; 3033 { 3034 struct com_s *com; 3035 int s; 3036 3037 com = tp->t_sc; 3038 if (com == NULL) 3039 return; 3040 s = spltty(); 3041 mtx_lock_spin(&sio_lock); 3042 if (tp->t_state & TS_TTSTOP) 3043 com->state &= ~CS_TTGO; 3044 else 3045 com->state |= CS_TTGO; 3046 if (tp->t_state & TS_TBLOCK) { 3047 #ifdef PC98 3048 if (IS_8251(com->pc98_if_type)) { 3049 if ((com_tiocm_get(com) & TIOCM_RTS) && 3050 (com->state & CS_RTS_IFLOW)) 3051 com_tiocm_bic(com, TIOCM_RTS); 3052 } else { 3053 if ((com->mcr_image & MCR_RTS) && 3054 (com->state & CS_RTS_IFLOW)) 3055 outb(com->modem_ctl_port, com->mcr_image &= ~MCR_RTS); 3056 } 3057 #else 3058 if (com->mcr_image & MCR_RTS && com->state & CS_RTS_IFLOW) 3059 outb(com->modem_ctl_port, com->mcr_image &= ~MCR_RTS); 3060 #endif 3061 } else { 3062 #ifdef PC98 3063 if (IS_8251(com->pc98_if_type)) { 3064 if (!(com_tiocm_get(com) & TIOCM_RTS) && 3065 com->iptr < com->ihighwater && 3066 com->state & CS_RTS_IFLOW) 3067 com_tiocm_bis(com, TIOCM_RTS); 3068 } else { 3069 if (!(com->mcr_image & MCR_RTS) && 3070 com->iptr < com->ihighwater && 3071 com->state & CS_RTS_IFLOW) 3072 outb(com->modem_ctl_port, com->mcr_image |= MCR_RTS); 3073 } 3074 #else 3075 if (!(com->mcr_image & MCR_RTS) && com->iptr < com->ihighwater 3076 && com->state & CS_RTS_IFLOW) 3077 outb(com->modem_ctl_port, com->mcr_image |= MCR_RTS); 3078 #endif 3079 } 3080 mtx_unlock_spin(&sio_lock); 3081 if (tp->t_state & (TS_TIMEOUT | TS_TTSTOP)) { 3082 ttwwakeup(tp); 3083 splx(s); 3084 return; 3085 } 3086 if (tp->t_outq.c_cc != 0) { 3087 struct lbq *qp; 3088 struct lbq *next; 3089 3090 if (!com->obufs[0].l_queued) { 3091 com->obufs[0].l_tail 3092 = com->obuf1 + q_to_b(&tp->t_outq, com->obuf1, 3093 #ifdef PC98 3094 com->obufsize); 3095 #else 3096 sizeof com->obuf1); 3097 #endif 3098 com->obufs[0].l_next = NULL; 3099 com->obufs[0].l_queued = TRUE; 3100 mtx_lock_spin(&sio_lock); 3101 if (com->state & CS_BUSY) { 3102 qp = com->obufq.l_next; 3103 while ((next = qp->l_next) != NULL) 3104 qp = next; 3105 qp->l_next = &com->obufs[0]; 3106 } else { 3107 com->obufq.l_head = com->obufs[0].l_head; 3108 com->obufq.l_tail = com->obufs[0].l_tail; 3109 com->obufq.l_next = &com->obufs[0]; 3110 com->state |= CS_BUSY; 3111 } 3112 mtx_unlock_spin(&sio_lock); 3113 } 3114 if (tp->t_outq.c_cc != 0 && !com->obufs[1].l_queued) { 3115 com->obufs[1].l_tail 3116 = com->obuf2 + q_to_b(&tp->t_outq, com->obuf2, 3117 #ifdef PC98 3118 com->obufsize); 3119 #else 3120 sizeof com->obuf2); 3121 #endif 3122 com->obufs[1].l_next = NULL; 3123 com->obufs[1].l_queued = TRUE; 3124 mtx_lock_spin(&sio_lock); 3125 if (com->state & CS_BUSY) { 3126 qp = com->obufq.l_next; 3127 while ((next = qp->l_next) != NULL) 3128 qp = next; 3129 qp->l_next = &com->obufs[1]; 3130 } else { 3131 com->obufq.l_head = com->obufs[1].l_head; 3132 com->obufq.l_tail = com->obufs[1].l_tail; 3133 com->obufq.l_next = &com->obufs[1]; 3134 com->state |= CS_BUSY; 3135 } 3136 mtx_unlock_spin(&sio_lock); 3137 } 3138 tp->t_state |= TS_BUSY; 3139 } 3140 mtx_lock_spin(&sio_lock); 3141 if (com->state >= (CS_BUSY | CS_TTGO)) 3142 siointr1(com); /* fake interrupt to start output */ 3143 mtx_unlock_spin(&sio_lock); 3144 ttwwakeup(tp); 3145 splx(s); 3146 } 3147 3148 static void 3149 comstop(tp, rw) 3150 struct tty *tp; 3151 int rw; 3152 { 3153 struct com_s *com; 3154 #ifdef PC98 3155 int rsa98_tmp = 0; 3156 #endif 3157 3158 com = tp->t_sc; 3159 if (com == NULL || com->gone) 3160 return; 3161 mtx_lock_spin(&sio_lock); 3162 if (rw & FWRITE) { 3163 #ifdef PC98 3164 if (!IS_8251(com->pc98_if_type)) { 3165 #endif 3166 if (com->hasfifo) 3167 #ifdef COM_ESP 3168 /* XXX avoid h/w bug. */ 3169 if (!com->esp) 3170 #endif 3171 sio_setreg(com, com_fifo, 3172 FIFO_XMT_RST | com->fifo_image); 3173 #ifdef PC98 3174 if (com->pc98_if_type == COM_IF_RSA98III) 3175 for (rsa98_tmp = 0; rsa98_tmp < 2048; rsa98_tmp++) 3176 sio_setreg(com, com_fifo, 3177 FIFO_XMT_RST | com->fifo_image); 3178 } 3179 #endif 3180 com->obufs[0].l_queued = FALSE; 3181 com->obufs[1].l_queued = FALSE; 3182 if (com->state & CS_ODONE) 3183 com_events -= LOTS_OF_EVENTS; 3184 com->state &= ~(CS_ODONE | CS_BUSY); 3185 com->tp->t_state &= ~TS_BUSY; 3186 } 3187 if (rw & FREAD) { 3188 #ifdef PC98 3189 if (!IS_8251(com->pc98_if_type)) { 3190 if (com->pc98_if_type == COM_IF_RSA98III) 3191 for (rsa98_tmp = 0; rsa98_tmp < 2048; rsa98_tmp++) 3192 sio_getreg(com, com_data); 3193 #endif 3194 if (com->hasfifo) 3195 #ifdef COM_ESP 3196 /* XXX avoid h/w bug. */ 3197 if (!com->esp) 3198 #endif 3199 sio_setreg(com, com_fifo, 3200 FIFO_RCV_RST | com->fifo_image); 3201 #ifdef PC98 3202 } 3203 #endif 3204 com_events -= (com->iptr - com->ibuf); 3205 com->iptr = com->ibuf; 3206 } 3207 mtx_unlock_spin(&sio_lock); 3208 comstart(tp); 3209 } 3210 3211 static int 3212 commodem(struct tty *tp, int sigon, int sigoff) 3213 { 3214 struct com_s *com; 3215 int bitand, bitor, msr; 3216 #ifdef PC98 3217 int clr, set; 3218 #endif 3219 3220 com = tp->t_sc; 3221 if (com->gone) 3222 return(0); 3223 if (sigon != 0 || sigoff != 0) { 3224 #ifdef PC98 3225 if (IS_8251(com->pc98_if_type)) { 3226 bitand = bitor = 0; 3227 clr = set = 0; 3228 if (sigoff & SER_DTR) { 3229 bitand |= TIOCM_DTR; 3230 clr |= CMD8251_DTR; 3231 } 3232 if (sigoff & SER_RTS) { 3233 bitand |= TIOCM_RTS; 3234 clr |= CMD8251_RxEN | CMD8251_RTS; 3235 } 3236 if (sigon & SER_DTR) { 3237 bitor |= TIOCM_DTR; 3238 set |= CMD8251_TxEN | CMD8251_RxEN | 3239 CMD8251_DTR; 3240 } 3241 if (sigon & SER_RTS) { 3242 bitor |= TIOCM_RTS; 3243 set |= CMD8251_TxEN | CMD8251_RxEN | 3244 CMD8251_RTS; 3245 } 3246 bitand = ~bitand; 3247 mtx_lock_spin(&sio_lock); 3248 com->pc98_prev_modem_status &= bitand; 3249 com->pc98_prev_modem_status |= bitor; 3250 pc98_i8251_clear_or_cmd(com, clr, set); 3251 mtx_unlock_spin(&sio_lock); 3252 return (0); 3253 } else { 3254 #endif 3255 bitand = bitor = 0; 3256 if (sigoff & SER_DTR) 3257 bitand |= MCR_DTR; 3258 if (sigoff & SER_RTS) 3259 bitand |= MCR_RTS; 3260 if (sigon & SER_DTR) 3261 bitor |= MCR_DTR; 3262 if (sigon & SER_RTS) 3263 bitor |= MCR_RTS; 3264 bitand = ~bitand; 3265 mtx_lock_spin(&sio_lock); 3266 com->mcr_image &= bitand; 3267 com->mcr_image |= bitor; 3268 outb(com->modem_ctl_port, com->mcr_image); 3269 mtx_unlock_spin(&sio_lock); 3270 return (0); 3271 #ifdef PC98 3272 } 3273 #endif 3274 } else { 3275 #ifdef PC98 3276 if (IS_8251(com->pc98_if_type)) 3277 return (com_tiocm_get(com)); 3278 else { 3279 #endif 3280 bitor = 0; 3281 if (com->mcr_image & MCR_DTR) 3282 bitor |= SER_DTR; 3283 if (com->mcr_image & MCR_RTS) 3284 bitor |= SER_RTS; 3285 msr = com->prev_modem_status; 3286 if (msr & MSR_CTS) 3287 bitor |= SER_CTS; 3288 if (msr & MSR_DCD) 3289 bitor |= SER_DCD; 3290 if (msr & MSR_DSR) 3291 bitor |= SER_DSR; 3292 if (msr & MSR_DSR) 3293 bitor |= SER_DSR; 3294 if (msr & (MSR_RI | MSR_TERI)) 3295 bitor |= SER_RI; 3296 return (bitor); 3297 #ifdef PC98 3298 } 3299 #endif 3300 } 3301 } 3302 3303 static void 3304 siosettimeout() 3305 { 3306 struct com_s *com; 3307 bool_t someopen; 3308 int unit; 3309 3310 /* 3311 * Set our timeout period to 1 second if no polled devices are open. 3312 * Otherwise set it to max(1/200, 1/hz). 3313 * Enable timeouts iff some device is open. 3314 */ 3315 untimeout(comwakeup, (void *)NULL, sio_timeout_handle); 3316 sio_timeout = hz; 3317 someopen = FALSE; 3318 for (unit = 0; unit < sio_numunits; ++unit) { 3319 com = com_addr(unit); 3320 if (com != NULL && com->tp != NULL 3321 && com->tp->t_state & TS_ISOPEN && !com->gone) { 3322 someopen = TRUE; 3323 if (com->poll || com->poll_output) { 3324 sio_timeout = hz > 200 ? hz / 200 : 1; 3325 break; 3326 } 3327 } 3328 } 3329 if (someopen) { 3330 sio_timeouts_until_log = hz / sio_timeout; 3331 sio_timeout_handle = timeout(comwakeup, (void *)NULL, 3332 sio_timeout); 3333 } else { 3334 /* Flush error messages, if any. */ 3335 sio_timeouts_until_log = 1; 3336 comwakeup((void *)NULL); 3337 untimeout(comwakeup, (void *)NULL, sio_timeout_handle); 3338 } 3339 } 3340 3341 static void 3342 comwakeup(chan) 3343 void *chan; 3344 { 3345 struct com_s *com; 3346 int unit; 3347 3348 sio_timeout_handle = timeout(comwakeup, (void *)NULL, sio_timeout); 3349 3350 /* 3351 * Recover from lost output interrupts. 3352 * Poll any lines that don't use interrupts. 3353 */ 3354 for (unit = 0; unit < sio_numunits; ++unit) { 3355 com = com_addr(unit); 3356 if (com != NULL && !com->gone 3357 && (com->state >= (CS_BUSY | CS_TTGO) || com->poll)) { 3358 mtx_lock_spin(&sio_lock); 3359 siointr1(com); 3360 mtx_unlock_spin(&sio_lock); 3361 } 3362 } 3363 3364 /* 3365 * Check for and log errors, but not too often. 3366 */ 3367 if (--sio_timeouts_until_log > 0) 3368 return; 3369 sio_timeouts_until_log = hz / sio_timeout; 3370 for (unit = 0; unit < sio_numunits; ++unit) { 3371 int errnum; 3372 3373 com = com_addr(unit); 3374 if (com == NULL) 3375 continue; 3376 if (com->gone) 3377 continue; 3378 for (errnum = 0; errnum < CE_NTYPES; ++errnum) { 3379 u_int delta; 3380 u_long total; 3381 3382 mtx_lock_spin(&sio_lock); 3383 delta = com->delta_error_counts[errnum]; 3384 com->delta_error_counts[errnum] = 0; 3385 mtx_unlock_spin(&sio_lock); 3386 if (delta == 0) 3387 continue; 3388 total = com->error_counts[errnum] += delta; 3389 log(LOG_ERR, "sio%d: %u more %s%s (total %lu)\n", 3390 unit, delta, error_desc[errnum], 3391 delta == 1 ? "" : "s", total); 3392 } 3393 } 3394 } 3395 3396 #ifdef PC98 3397 /* commint is called when modem control line changes */ 3398 static void 3399 commint(struct cdev *dev) 3400 { 3401 register struct tty *tp; 3402 int stat,delta; 3403 struct com_s *com; 3404 3405 com = dev->si_drv1; 3406 tp = com->tp; 3407 3408 stat = com_tiocm_get(com); 3409 delta = com_tiocm_get_delta(com); 3410 3411 if (com->state & CS_CTS_OFLOW) { 3412 if (stat & TIOCM_CTS) 3413 com->state |= CS_ODEVREADY; 3414 else 3415 com->state &= ~CS_ODEVREADY; 3416 } 3417 if ((delta & TIOCM_CAR) && (ISCALLOUT(dev)) == 0) { 3418 if (stat & TIOCM_CAR ) 3419 (void)ttyld_modem(tp, 1); 3420 else if (ttyld_modem(tp, 0) == 0) { 3421 /* negate DTR, RTS */ 3422 com_tiocm_bic(com, (tp->t_cflag & HUPCL) ? 3423 TIOCM_DTR|TIOCM_RTS|TIOCM_LE : TIOCM_LE ); 3424 /* disable IENABLE */ 3425 com_int_TxRx_disable( com ); 3426 } 3427 } 3428 } 3429 #endif 3430 3431 /* 3432 * Following are all routines needed for SIO to act as console 3433 */ 3434 struct siocnstate { 3435 u_char dlbl; 3436 u_char dlbh; 3437 u_char ier; 3438 u_char cfcr; 3439 u_char mcr; 3440 }; 3441 3442 /* 3443 * This is a function in order to not replicate "ttyd%d" more 3444 * places than absolutely necessary. 3445 */ 3446 static void 3447 siocnset(struct consdev *cd, int unit) 3448 { 3449 3450 cd->cn_unit = unit; 3451 sprintf(cd->cn_name, "ttyd%d", unit); 3452 } 3453 3454 static speed_t siocngetspeed(Port_t, u_long rclk); 3455 static void siocnclose(struct siocnstate *sp, Port_t iobase); 3456 static void siocnopen(struct siocnstate *sp, Port_t iobase, int speed); 3457 static void siocntxwait(Port_t iobase); 3458 3459 static cn_probe_t sio_cnprobe; 3460 static cn_init_t sio_cninit; 3461 static cn_term_t sio_cnterm; 3462 static cn_getc_t sio_cngetc; 3463 static cn_putc_t sio_cnputc; 3464 3465 CONSOLE_DRIVER(sio); 3466 3467 static void 3468 siocntxwait(iobase) 3469 Port_t iobase; 3470 { 3471 int timo; 3472 3473 /* 3474 * Wait for any pending transmission to finish. Required to avoid 3475 * the UART lockup bug when the speed is changed, and for normal 3476 * transmits. 3477 */ 3478 timo = 100000; 3479 while ((inb(iobase + com_lsr) & (LSR_TSRE | LSR_TXRDY)) 3480 != (LSR_TSRE | LSR_TXRDY) && --timo != 0) 3481 ; 3482 } 3483 3484 /* 3485 * Read the serial port specified and try to figure out what speed 3486 * it's currently running at. We're assuming the serial port has 3487 * been initialized and is basicly idle. This routine is only intended 3488 * to be run at system startup. 3489 * 3490 * If the value read from the serial port doesn't make sense, return 0. 3491 */ 3492 3493 static speed_t 3494 siocngetspeed(iobase, rclk) 3495 Port_t iobase; 3496 u_long rclk; 3497 { 3498 u_int divisor; 3499 u_char dlbh; 3500 u_char dlbl; 3501 u_char cfcr; 3502 3503 cfcr = inb(iobase + com_cfcr); 3504 outb(iobase + com_cfcr, CFCR_DLAB | cfcr); 3505 3506 dlbl = inb(iobase + com_dlbl); 3507 dlbh = inb(iobase + com_dlbh); 3508 3509 outb(iobase + com_cfcr, cfcr); 3510 3511 divisor = dlbh << 8 | dlbl; 3512 3513 /* XXX there should be more sanity checking. */ 3514 if (divisor == 0) 3515 return (CONSPEED); 3516 return (rclk / (16UL * divisor)); 3517 } 3518 3519 static void 3520 siocnopen(sp, iobase, speed) 3521 struct siocnstate *sp; 3522 Port_t iobase; 3523 int speed; 3524 { 3525 u_int divisor; 3526 u_char dlbh; 3527 u_char dlbl; 3528 3529 /* 3530 * Save all the device control registers except the fifo register 3531 * and set our default ones (cs8 -parenb speed=comdefaultrate). 3532 * We can't save the fifo register since it is read-only. 3533 */ 3534 sp->ier = inb(iobase + com_ier); 3535 outb(iobase + com_ier, 0); /* spltty() doesn't stop siointr() */ 3536 siocntxwait(iobase); 3537 sp->cfcr = inb(iobase + com_cfcr); 3538 outb(iobase + com_cfcr, CFCR_DLAB | CFCR_8BITS); 3539 sp->dlbl = inb(iobase + com_dlbl); 3540 sp->dlbh = inb(iobase + com_dlbh); 3541 /* 3542 * Only set the divisor registers if they would change, since on 3543 * some 16550 incompatibles (Startech), setting them clears the 3544 * data input register. This also reduces the effects of the 3545 * UMC8669F bug. 3546 */ 3547 divisor = siodivisor(comdefaultrclk, speed); 3548 dlbl = divisor & 0xFF; 3549 if (sp->dlbl != dlbl) 3550 outb(iobase + com_dlbl, dlbl); 3551 dlbh = divisor >> 8; 3552 if (sp->dlbh != dlbh) 3553 outb(iobase + com_dlbh, dlbh); 3554 outb(iobase + com_cfcr, CFCR_8BITS); 3555 sp->mcr = inb(iobase + com_mcr); 3556 /* 3557 * We don't want interrupts, but must be careful not to "disable" 3558 * them by clearing the MCR_IENABLE bit, since that might cause 3559 * an interrupt by floating the IRQ line. 3560 */ 3561 outb(iobase + com_mcr, (sp->mcr & MCR_IENABLE) | MCR_DTR | MCR_RTS); 3562 } 3563 3564 static void 3565 siocnclose(sp, iobase) 3566 struct siocnstate *sp; 3567 Port_t iobase; 3568 { 3569 /* 3570 * Restore the device control registers. 3571 */ 3572 siocntxwait(iobase); 3573 outb(iobase + com_cfcr, CFCR_DLAB | CFCR_8BITS); 3574 if (sp->dlbl != inb(iobase + com_dlbl)) 3575 outb(iobase + com_dlbl, sp->dlbl); 3576 if (sp->dlbh != inb(iobase + com_dlbh)) 3577 outb(iobase + com_dlbh, sp->dlbh); 3578 outb(iobase + com_cfcr, sp->cfcr); 3579 /* 3580 * XXX damp oscillations of MCR_DTR and MCR_RTS by not restoring them. 3581 */ 3582 outb(iobase + com_mcr, sp->mcr | MCR_DTR | MCR_RTS); 3583 outb(iobase + com_ier, sp->ier); 3584 } 3585 3586 static void 3587 sio_cnprobe(cp) 3588 struct consdev *cp; 3589 { 3590 speed_t boot_speed; 3591 u_char cfcr; 3592 u_int divisor; 3593 int s, unit; 3594 struct siocnstate sp; 3595 3596 /* 3597 * Find our first enabled console, if any. If it is a high-level 3598 * console device, then initialize it and return successfully. 3599 * If it is a low-level console device, then initialize it and 3600 * return unsuccessfully. It must be initialized in both cases 3601 * for early use by console drivers and debuggers. Initializing 3602 * the hardware is not necessary in all cases, since the i/o 3603 * routines initialize it on the fly, but it is necessary if 3604 * input might arrive while the hardware is switched back to an 3605 * uninitialized state. We can't handle multiple console devices 3606 * yet because our low-level routines don't take a device arg. 3607 * We trust the user to set the console flags properly so that we 3608 * don't need to probe. 3609 */ 3610 cp->cn_pri = CN_DEAD; 3611 3612 for (unit = 0; unit < 16; unit++) { /* XXX need to know how many */ 3613 int flags; 3614 3615 if (resource_disabled("sio", unit)) 3616 continue; 3617 if (resource_int_value("sio", unit, "flags", &flags)) 3618 continue; 3619 if (COM_CONSOLE(flags) || COM_DEBUGGER(flags)) { 3620 int port; 3621 Port_t iobase; 3622 3623 if (resource_int_value("sio", unit, "port", &port)) 3624 continue; 3625 iobase = port; 3626 s = spltty(); 3627 if (boothowto & RB_SERIAL) { 3628 boot_speed = 3629 siocngetspeed(iobase, comdefaultrclk); 3630 if (boot_speed) 3631 comdefaultrate = boot_speed; 3632 } 3633 3634 /* 3635 * Initialize the divisor latch. We can't rely on 3636 * siocnopen() to do this the first time, since it 3637 * avoids writing to the latch if the latch appears 3638 * to have the correct value. Also, if we didn't 3639 * just read the speed from the hardware, then we 3640 * need to set the speed in hardware so that 3641 * switching it later is null. 3642 */ 3643 cfcr = inb(iobase + com_cfcr); 3644 outb(iobase + com_cfcr, CFCR_DLAB | cfcr); 3645 divisor = siodivisor(comdefaultrclk, comdefaultrate); 3646 outb(iobase + com_dlbl, divisor & 0xff); 3647 outb(iobase + com_dlbh, divisor >> 8); 3648 outb(iobase + com_cfcr, cfcr); 3649 3650 siocnopen(&sp, iobase, comdefaultrate); 3651 3652 splx(s); 3653 if (COM_CONSOLE(flags) && !COM_LLCONSOLE(flags)) { 3654 siocnset(cp, unit); 3655 cp->cn_pri = COM_FORCECONSOLE(flags) 3656 || boothowto & RB_SERIAL 3657 ? CN_REMOTE : CN_NORMAL; 3658 siocniobase = iobase; 3659 siocnunit = unit; 3660 } 3661 #ifdef GDB 3662 if (COM_DEBUGGER(flags)) 3663 siogdbiobase = iobase; 3664 #endif 3665 } 3666 } 3667 } 3668 3669 static void 3670 sio_cninit(cp) 3671 struct consdev *cp; 3672 { 3673 comconsole = cp->cn_unit; 3674 } 3675 3676 static void 3677 sio_cnterm(cp) 3678 struct consdev *cp; 3679 { 3680 comconsole = -1; 3681 } 3682 3683 static int 3684 sio_cngetc(struct consdev *cd) 3685 { 3686 int c; 3687 Port_t iobase; 3688 int s; 3689 struct siocnstate sp; 3690 speed_t speed; 3691 3692 if (cd != NULL && cd->cn_unit == siocnunit) { 3693 iobase = siocniobase; 3694 speed = comdefaultrate; 3695 } else { 3696 #ifdef GDB 3697 iobase = siogdbiobase; 3698 speed = gdbdefaultrate; 3699 #else 3700 return (-1); 3701 #endif 3702 } 3703 s = spltty(); 3704 siocnopen(&sp, iobase, speed); 3705 if (inb(iobase + com_lsr) & LSR_RXRDY) 3706 c = inb(iobase + com_data); 3707 else 3708 c = -1; 3709 siocnclose(&sp, iobase); 3710 splx(s); 3711 return (c); 3712 } 3713 3714 static void 3715 sio_cnputc(struct consdev *cd, int c) 3716 { 3717 int need_unlock; 3718 int s; 3719 struct siocnstate sp; 3720 Port_t iobase; 3721 speed_t speed; 3722 3723 if (cd != NULL && cd->cn_unit == siocnunit) { 3724 iobase = siocniobase; 3725 speed = comdefaultrate; 3726 } else { 3727 #ifdef GDB 3728 iobase = siogdbiobase; 3729 speed = gdbdefaultrate; 3730 #else 3731 return; 3732 #endif 3733 } 3734 s = spltty(); 3735 need_unlock = 0; 3736 if (!kdb_active && sio_inited == 2 && !mtx_owned(&sio_lock)) { 3737 mtx_lock_spin(&sio_lock); 3738 need_unlock = 1; 3739 } 3740 siocnopen(&sp, iobase, speed); 3741 siocntxwait(iobase); 3742 outb(iobase + com_data, c); 3743 siocnclose(&sp, iobase); 3744 if (need_unlock) 3745 mtx_unlock_spin(&sio_lock); 3746 splx(s); 3747 } 3748 3749 /* 3750 * Remote gdb(1) support. 3751 */ 3752 3753 #if defined(GDB) 3754 3755 #include <gdb/gdb.h> 3756 3757 static gdb_probe_f siogdbprobe; 3758 static gdb_init_f siogdbinit; 3759 static gdb_term_f siogdbterm; 3760 static gdb_getc_f siogdbgetc; 3761 static gdb_putc_f siogdbputc; 3762 3763 GDB_DBGPORT(sio, siogdbprobe, siogdbinit, siogdbterm, siogdbgetc, siogdbputc); 3764 3765 static int 3766 siogdbprobe(void) 3767 { 3768 return ((siogdbiobase != 0) ? 0 : -1); 3769 } 3770 3771 static void 3772 siogdbinit(void) 3773 { 3774 } 3775 3776 static void 3777 siogdbterm(void) 3778 { 3779 } 3780 3781 static void 3782 siogdbputc(int c) 3783 { 3784 sio_cnputc(NULL, c); 3785 } 3786 3787 static int 3788 siogdbgetc(void) 3789 { 3790 return (sio_cngetc(NULL)); 3791 } 3792 3793 #endif 3794 3795 #ifdef PC98 3796 /* 3797 * pc98 local function 3798 */ 3799 static void 3800 com_tiocm_bis(struct com_s *com, int msr) 3801 { 3802 int s; 3803 int tmp = 0; 3804 3805 s=spltty(); 3806 com->pc98_prev_modem_status |= ( msr & (TIOCM_LE|TIOCM_DTR|TIOCM_RTS) ); 3807 tmp |= CMD8251_TxEN|CMD8251_RxEN; 3808 if ( msr & TIOCM_DTR ) tmp |= CMD8251_DTR; 3809 if ( msr & TIOCM_RTS ) tmp |= CMD8251_RTS; 3810 3811 pc98_i8251_or_cmd( com, tmp ); 3812 splx(s); 3813 } 3814 3815 static void 3816 com_tiocm_bic(struct com_s *com, int msr) 3817 { 3818 int s; 3819 int tmp = msr; 3820 3821 s=spltty(); 3822 com->pc98_prev_modem_status &= ~( msr & (TIOCM_LE|TIOCM_DTR|TIOCM_RTS) ); 3823 if ( msr & TIOCM_DTR ) tmp |= CMD8251_DTR; 3824 if ( msr & TIOCM_RTS ) tmp |= CMD8251_RTS; 3825 3826 pc98_i8251_clear_cmd( com, tmp ); 3827 splx(s); 3828 } 3829 3830 static int 3831 com_tiocm_get(struct com_s *com) 3832 { 3833 return( com->pc98_prev_modem_status ); 3834 } 3835 3836 static int 3837 com_tiocm_get_delta(struct com_s *com) 3838 { 3839 int tmp; 3840 3841 tmp = com->pc98_modem_delta; 3842 com->pc98_modem_delta = 0; 3843 return( tmp ); 3844 } 3845 3846 /* convert to TIOCM_?? ( ioctl.h ) */ 3847 static int 3848 pc98_get_modem_status(struct com_s *com) 3849 { 3850 register int msr; 3851 3852 msr = com->pc98_prev_modem_status 3853 & ~(TIOCM_CAR|TIOCM_RI|TIOCM_DSR|TIOCM_CTS); 3854 if (com->pc98_8251fifo_enable) { 3855 int stat2; 3856 3857 stat2 = inb(I8251F_msr); 3858 if ( stat2 & CICSCDF_CD ) msr |= TIOCM_CAR; 3859 if ( stat2 & CICSCDF_CI ) msr |= TIOCM_RI; 3860 if ( stat2 & CICSCDF_DR ) msr |= TIOCM_DSR; 3861 if ( stat2 & CICSCDF_CS ) msr |= TIOCM_CTS; 3862 #if COM_CARRIER_DETECT_EMULATE 3863 if ( msr & (TIOCM_DSR|TIOCM_CTS) ) { 3864 msr |= TIOCM_CAR; 3865 } 3866 #endif 3867 } else { 3868 int stat, stat2; 3869 3870 stat = inb(com->sts_port); 3871 stat2 = inb(com->in_modem_port); 3872 if ( !(stat2 & CICSCD_CD) ) msr |= TIOCM_CAR; 3873 if ( !(stat2 & CICSCD_CI) ) msr |= TIOCM_RI; 3874 if ( stat & STS8251_DSR ) msr |= TIOCM_DSR; 3875 if ( !(stat2 & CICSCD_CS) ) msr |= TIOCM_CTS; 3876 #if COM_CARRIER_DETECT_EMULATE 3877 if ( msr & (TIOCM_DSR|TIOCM_CTS) ) { 3878 msr |= TIOCM_CAR; 3879 } 3880 #endif 3881 } 3882 return(msr); 3883 } 3884 3885 static void 3886 pc98_check_msr(void* chan) 3887 { 3888 int msr, delta; 3889 int s; 3890 register struct tty *tp; 3891 struct com_s *com; 3892 struct cdev *dev; 3893 3894 dev=(struct cdev *)chan; 3895 com = dev->si_drv1; 3896 tp = dev->si_tty; 3897 3898 s = spltty(); 3899 msr = pc98_get_modem_status(com); 3900 /* make change flag */ 3901 delta = msr ^ com->pc98_prev_modem_status; 3902 if ( delta & TIOCM_CAR ) { 3903 if ( com->modem_car_chg_timer ) { 3904 if ( -- com->modem_car_chg_timer ) 3905 msr ^= TIOCM_CAR; 3906 } else { 3907 if ((com->modem_car_chg_timer = (msr & TIOCM_CAR) ? 3908 DCD_ON_RECOGNITION : DCD_OFF_TOLERANCE) != 0) 3909 msr ^= TIOCM_CAR; 3910 } 3911 } else 3912 com->modem_car_chg_timer = 0; 3913 delta = ( msr ^ com->pc98_prev_modem_status ) & 3914 (TIOCM_CAR|TIOCM_RI|TIOCM_DSR|TIOCM_CTS); 3915 com->pc98_prev_modem_status = msr; 3916 delta = ( com->pc98_modem_delta |= delta ); 3917 splx(s); 3918 if ( com->modem_checking || (tp->t_state & (TS_ISOPEN)) ) { 3919 if ( delta ) { 3920 commint(dev); 3921 } 3922 timeout(pc98_check_msr, (caddr_t)dev, 3923 PC98_CHECK_MODEM_INTERVAL); 3924 } else { 3925 com->modem_checking = 0; 3926 } 3927 } 3928 3929 static void 3930 pc98_msrint_start(struct cdev *dev) 3931 { 3932 struct com_s *com; 3933 int s = spltty(); 3934 3935 com = dev->si_drv1; 3936 /* modem control line check routine envoke interval is 1/10 sec */ 3937 if ( com->modem_checking == 0 ) { 3938 com->pc98_prev_modem_status = pc98_get_modem_status(com); 3939 com->pc98_modem_delta = 0; 3940 timeout(pc98_check_msr, (caddr_t)dev, 3941 PC98_CHECK_MODEM_INTERVAL); 3942 com->modem_checking = 1; 3943 } 3944 splx(s); 3945 } 3946 3947 static void 3948 pc98_disable_i8251_interrupt(struct com_s *com, int mod) 3949 { 3950 /* disable interrupt */ 3951 register int tmp; 3952 3953 mod |= ~(IEN_Tx|IEN_TxEMP|IEN_Rx); 3954 COM_INT_DISABLE 3955 tmp = inb( com->intr_ctrl_port ) & ~(IEN_Tx|IEN_TxEMP|IEN_Rx); 3956 outb( com->intr_ctrl_port, (com->intr_enable&=~mod) | tmp ); 3957 COM_INT_ENABLE 3958 } 3959 3960 static void 3961 pc98_enable_i8251_interrupt(struct com_s *com, int mod) 3962 { 3963 register int tmp; 3964 3965 COM_INT_DISABLE 3966 tmp = inb( com->intr_ctrl_port ) & ~(IEN_Tx|IEN_TxEMP|IEN_Rx); 3967 outb( com->intr_ctrl_port, (com->intr_enable|=mod) | tmp ); 3968 COM_INT_ENABLE 3969 } 3970 3971 static int 3972 pc98_check_i8251_interrupt(struct com_s *com) 3973 { 3974 return ( com->intr_enable & 0x07 ); 3975 } 3976 3977 static void 3978 pc98_i8251_clear_cmd(struct com_s *com, int x) 3979 { 3980 int tmp; 3981 3982 COM_INT_DISABLE 3983 tmp = com->pc98_prev_siocmd & ~(x); 3984 if (com->pc98_8251fifo_enable) 3985 outb(I8251F_fcr, 0); 3986 outb(com->cmd_port, tmp); 3987 com->pc98_prev_siocmd = tmp & ~(CMD8251_ER|CMD8251_RESET|CMD8251_EH); 3988 if (com->pc98_8251fifo_enable) 3989 outb(I8251F_fcr, CTRL8251F_ENABLE); 3990 COM_INT_ENABLE 3991 } 3992 3993 static void 3994 pc98_i8251_or_cmd(struct com_s *com, int x) 3995 { 3996 int tmp; 3997 3998 COM_INT_DISABLE 3999 if (com->pc98_8251fifo_enable) 4000 outb(I8251F_fcr, 0); 4001 tmp = com->pc98_prev_siocmd | (x); 4002 outb(com->cmd_port, tmp); 4003 com->pc98_prev_siocmd = tmp & ~(CMD8251_ER|CMD8251_RESET|CMD8251_EH); 4004 if (com->pc98_8251fifo_enable) 4005 outb(I8251F_fcr, CTRL8251F_ENABLE); 4006 COM_INT_ENABLE 4007 } 4008 4009 static void 4010 pc98_i8251_set_cmd(struct com_s *com, int x) 4011 { 4012 int tmp; 4013 4014 COM_INT_DISABLE 4015 if (com->pc98_8251fifo_enable) 4016 outb(I8251F_fcr, 0); 4017 tmp = (x); 4018 outb(com->cmd_port, tmp); 4019 com->pc98_prev_siocmd = tmp & ~(CMD8251_ER|CMD8251_RESET|CMD8251_EH); 4020 if (com->pc98_8251fifo_enable) 4021 outb(I8251F_fcr, CTRL8251F_ENABLE); 4022 COM_INT_ENABLE 4023 } 4024 4025 static void 4026 pc98_i8251_clear_or_cmd(struct com_s *com, int clr, int x) 4027 { 4028 int tmp; 4029 COM_INT_DISABLE 4030 if (com->pc98_8251fifo_enable) 4031 outb(I8251F_fcr, 0); 4032 tmp = com->pc98_prev_siocmd & ~(clr); 4033 tmp |= (x); 4034 outb(com->cmd_port, tmp); 4035 com->pc98_prev_siocmd = tmp & ~(CMD8251_ER|CMD8251_RESET|CMD8251_EH); 4036 if (com->pc98_8251fifo_enable) 4037 outb(I8251F_fcr, CTRL8251F_ENABLE); 4038 COM_INT_ENABLE 4039 } 4040 4041 static int 4042 pc98_i8251_get_cmd(struct com_s *com) 4043 { 4044 return com->pc98_prev_siocmd; 4045 } 4046 4047 static int 4048 pc98_i8251_get_mod(struct com_s *com) 4049 { 4050 return com->pc98_prev_siomod; 4051 } 4052 4053 static void 4054 pc98_i8251_reset(struct com_s *com, int mode, int command) 4055 { 4056 if (com->pc98_8251fifo_enable) 4057 outb(I8251F_fcr, 0); 4058 outb(com->cmd_port, 0); /* dummy */ 4059 DELAY(2); 4060 outb(com->cmd_port, 0); /* dummy */ 4061 DELAY(2); 4062 outb(com->cmd_port, 0); /* dummy */ 4063 DELAY(2); 4064 outb(com->cmd_port, CMD8251_RESET); /* internal reset */ 4065 DELAY(2); 4066 outb(com->cmd_port, mode ); /* mode register */ 4067 com->pc98_prev_siomod = mode; 4068 DELAY(2); 4069 pc98_i8251_set_cmd( com, (command|CMD8251_ER) ); 4070 DELAY(10); 4071 if (com->pc98_8251fifo_enable) 4072 outb(I8251F_fcr, CTRL8251F_ENABLE | 4073 CTRL8251F_XMT_RST | CTRL8251F_RCV_RST); 4074 } 4075 4076 static void 4077 pc98_check_sysclock(void) 4078 { 4079 /* get system clock from port */ 4080 if ( pc98_machine_type & M_8M ) { 4081 /* 8 MHz system & H98 */ 4082 sysclock = 8; 4083 } else { 4084 /* 5 MHz system */ 4085 sysclock = 5; 4086 } 4087 } 4088 4089 static void 4090 com_cflag_and_speed_set( struct com_s *com, int cflag, int speed) 4091 { 4092 int cfcr=0; 4093 int previnterrupt; 4094 int tmp; 4095 u_int count; 4096 4097 if (pc98_ttspeedtab(com, speed, &count) != 0) 4098 return; 4099 4100 previnterrupt = pc98_check_i8251_interrupt(com); 4101 pc98_disable_i8251_interrupt( com, IEN_Tx|IEN_TxEMP|IEN_Rx ); 4102 4103 switch ( cflag&CSIZE ) { 4104 case CS5: 4105 cfcr = MOD8251_5BITS; break; 4106 case CS6: 4107 cfcr = MOD8251_6BITS; break; 4108 case CS7: 4109 cfcr = MOD8251_7BITS; break; 4110 case CS8: 4111 cfcr = MOD8251_8BITS; break; 4112 } 4113 if ( cflag&PARENB ) { 4114 if ( cflag&PARODD ) 4115 cfcr |= MOD8251_PODD; 4116 else 4117 cfcr |= MOD8251_PEVEN; 4118 } else 4119 cfcr |= MOD8251_PDISAB; 4120 4121 if ( cflag&CSTOPB ) 4122 cfcr |= MOD8251_STOP2; 4123 else 4124 cfcr |= MOD8251_STOP1; 4125 4126 if ( count & 0x10000 ) 4127 cfcr |= MOD8251_CLKX1; 4128 else 4129 cfcr |= MOD8251_CLKX16; 4130 4131 while (!((tmp = inb(com->sts_port)) & STS8251_TxEMP)) 4132 ; 4133 4134 /* set baud rate from ospeed */ 4135 pc98_set_baud_rate( com, count ); 4136 4137 if ( cfcr != pc98_i8251_get_mod(com) ) 4138 pc98_i8251_reset(com, cfcr, pc98_i8251_get_cmd(com) ); 4139 4140 pc98_enable_i8251_interrupt( com, previnterrupt ); 4141 } 4142 4143 static int 4144 pc98_ttspeedtab(struct com_s *com, int speed, u_int *divisor) 4145 { 4146 int if_type, effect_sp, count = -1, mod; 4147 4148 if_type = com->pc98_if_type & 0x0f; 4149 4150 switch (com->pc98_if_type) { 4151 case COM_IF_INTERNAL: 4152 if (PC98SIO_baud_rate_port(if_type) != -1) { 4153 count = ttspeedtab(speed, if_8251_type[if_type].speedtab); 4154 if (count > 0) { 4155 count |= COM1_EXT_CLOCK; 4156 break; 4157 } 4158 } 4159 4160 /* for *1CLK asynchronous! mode, TEFUTEFU */ 4161 mod = (sysclock == 5) ? 2457600 : 1996800; 4162 effect_sp = ttspeedtab( speed, pc98speedtab ); 4163 if ( effect_sp < 0 ) /* XXX */ 4164 effect_sp = ttspeedtab( (speed - 1), pc98speedtab ); 4165 if ( effect_sp <= 0 ) 4166 return effect_sp; 4167 if ( effect_sp == speed ) 4168 mod /= 16; 4169 if ( mod % effect_sp ) 4170 return(-1); 4171 count = mod / effect_sp; 4172 if ( count > 65535 ) 4173 return(-1); 4174 if ( effect_sp != speed ) 4175 count |= 0x10000; 4176 break; 4177 case COM_IF_PC9861K_1: 4178 case COM_IF_PC9861K_2: 4179 count = 1; 4180 break; 4181 case COM_IF_IND_SS_1: 4182 case COM_IF_IND_SS_2: 4183 case COM_IF_PIO9032B_1: 4184 case COM_IF_PIO9032B_2: 4185 count = ttspeedtab( speed, if_8251_type[if_type].speedtab ); 4186 break; 4187 case COM_IF_B98_01_1: 4188 case COM_IF_B98_01_2: 4189 count = ttspeedtab( speed, if_8251_type[if_type].speedtab ); 4190 #ifdef B98_01_OLD 4191 if (count == 0 || count == 1) { 4192 count += 4; 4193 count |= 0x20000; /* x1 mode for 76800 and 153600 */ 4194 } 4195 #endif 4196 break; 4197 } 4198 4199 if (count < 0) 4200 return count; 4201 4202 *divisor = (u_int) count; 4203 return 0; 4204 } 4205 4206 static void 4207 pc98_set_baud_rate( struct com_s *com, u_int count ) 4208 { 4209 int if_type, io, s; 4210 4211 if_type = com->pc98_if_type & 0x0f; 4212 io = rman_get_start(com->ioportres) & 0xff00; 4213 4214 switch (com->pc98_if_type) { 4215 case COM_IF_INTERNAL: 4216 if (PC98SIO_baud_rate_port(if_type) != -1) { 4217 if (count & COM1_EXT_CLOCK) { 4218 outb((Port_t)PC98SIO_baud_rate_port(if_type), count & 0xff); 4219 break; 4220 } else { 4221 outb((Port_t)PC98SIO_baud_rate_port(if_type), 0x09); 4222 } 4223 } 4224 4225 if (count == 0) 4226 return; 4227 4228 /* set i8253 */ 4229 s = splclock(); 4230 if (count != 3) 4231 outb( 0x77, 0xb6 ); 4232 else 4233 outb( 0x77, 0xb4 ); 4234 outb( 0x5f, 0); 4235 outb( 0x75, count & 0xff ); 4236 outb( 0x5f, 0); 4237 outb( 0x75, (count >> 8) & 0xff ); 4238 splx(s); 4239 break; 4240 case COM_IF_IND_SS_1: 4241 case COM_IF_IND_SS_2: 4242 outb(io | PC98SIO_intr_ctrl_port(if_type), 0); 4243 outb(io | PC98SIO_baud_rate_port(if_type), 0); 4244 outb(io | PC98SIO_baud_rate_port(if_type), 0xc0); 4245 outb(io | PC98SIO_baud_rate_port(if_type), (count >> 8) | 0x80); 4246 outb(io | PC98SIO_baud_rate_port(if_type), count & 0xff); 4247 break; 4248 case COM_IF_PIO9032B_1: 4249 case COM_IF_PIO9032B_2: 4250 outb(io | PC98SIO_baud_rate_port(if_type), count); 4251 break; 4252 case COM_IF_B98_01_1: 4253 case COM_IF_B98_01_2: 4254 outb(io | PC98SIO_baud_rate_port(if_type), count & 0x0f); 4255 #ifdef B98_01_OLD 4256 /* 4257 * Some old B98_01 board should be controlled 4258 * in different way, but this hasn't been tested yet. 4259 */ 4260 outb(io | PC98SIO_func_port(if_type), 4261 (count & 0x20000) ? 0xf0 : 0xf2); 4262 #endif 4263 break; 4264 } 4265 } 4266 static int 4267 pc98_check_if_type(device_t dev, struct siodev *iod) 4268 { 4269 int irr, io, if_type, tmp; 4270 static short irq_tab[2][8] = { 4271 { 3, 5, 6, 9, 10, 12, 13, -1}, 4272 { 3, 10, 12, 13, 5, 6, 9, -1} 4273 }; 4274 4275 if_type = iod->if_type & 0x0f; 4276 iod->irq = 0; 4277 io = isa_get_port(dev) & 0xff00; 4278 4279 if (IS_8251(iod->if_type)) { 4280 if (PC98SIO_func_port(if_type) != -1) { 4281 outb(io | PC98SIO_func_port(if_type), 0xf2); 4282 tmp = ttspeedtab(9600, if_8251_type[if_type].speedtab); 4283 if (tmp != -1 && PC98SIO_baud_rate_port(if_type) != -1) 4284 outb(io | PC98SIO_baud_rate_port(if_type), tmp); 4285 } 4286 4287 iod->cmd = io | PC98SIO_cmd_port(if_type); 4288 iod->sts = io | PC98SIO_sts_port(if_type); 4289 iod->mod = io | PC98SIO_in_modem_port(if_type); 4290 iod->ctrl = io | PC98SIO_intr_ctrl_port(if_type); 4291 4292 if (iod->if_type == COM_IF_INTERNAL) { 4293 iod->irq = 4; 4294 4295 if (pc98_check_8251vfast()) { 4296 PC98SIO_baud_rate_port(if_type) = I8251F_div; 4297 if_8251_type[if_type].speedtab = pc98fast_speedtab; 4298 } 4299 } else { 4300 tmp = inb( iod->mod ) & if_8251_type[if_type].irr_mask; 4301 if ((isa_get_port(dev) & 0xff) == IO_COM2) 4302 iod->irq = irq_tab[0][tmp]; 4303 else 4304 iod->irq = irq_tab[1][tmp]; 4305 } 4306 } else { 4307 irr = if_16550a_type[if_type].irr_read; 4308 #ifdef COM_MULTIPORT 4309 if (!COM_ISMULTIPORT(device_get_flags(dev)) || 4310 device_get_unit(dev) == COM_MPMASTER(device_get_flags(dev))) 4311 #endif 4312 if (irr != -1) { 4313 tmp = inb(io | irr); 4314 if (isa_get_port(dev) & 0x01) /* XXX depend on RSB-384 */ 4315 iod->irq = irq_tab[1][tmp >> 3]; 4316 else 4317 iod->irq = irq_tab[0][tmp & 0x07]; 4318 } 4319 iod->cmd = 0; 4320 iod->sts = 0; 4321 iod->mod = 0; 4322 iod->ctrl = 0; 4323 } 4324 if ( iod->irq == -1 ) return -1; 4325 4326 return 0; 4327 } 4328 static void 4329 pc98_set_ioport(struct com_s *com) 4330 { 4331 int if_type = com->pc98_if_type & 0x0f; 4332 Port_t io = rman_get_start(com->ioportres) & 0xff00; 4333 4334 pc98_check_sysclock(); 4335 com->data_port = io | PC98SIO_data_port(if_type); 4336 com->cmd_port = io | PC98SIO_cmd_port(if_type); 4337 com->sts_port = io | PC98SIO_sts_port(if_type); 4338 com->in_modem_port = io | PC98SIO_in_modem_port(if_type); 4339 com->intr_ctrl_port = io | PC98SIO_intr_ctrl_port(if_type); 4340 } 4341 static int 4342 pc98_check_8251vfast(void) 4343 { 4344 int i; 4345 4346 outb(I8251F_div, 0x8c); 4347 DELAY(10); 4348 for (i = 0; i < 100; i++) { 4349 if ((inb(I8251F_div) & 0x80) != 0) { 4350 i = 0; 4351 break; 4352 } 4353 DELAY(1); 4354 } 4355 outb(I8251F_div, 0); 4356 DELAY(10); 4357 for (; i < 100; i++) { 4358 if ((inb(I8251F_div) & 0x80) == 0) 4359 return 1; 4360 DELAY(1); 4361 } 4362 4363 return 0; 4364 } 4365 static int 4366 pc98_check_8251fifo(void) 4367 { 4368 u_char tmp1, tmp2; 4369 4370 tmp1 = inb(I8251F_iir); 4371 DELAY(10); 4372 tmp2 = inb(I8251F_iir); 4373 if (((tmp1 ^ tmp2) & 0x40) != 0 && ((tmp1 | tmp2) & 0x20) == 0) 4374 return 1; 4375 4376 return 0; 4377 } 4378 #endif /* PC98 defined */
Cache object: f7762d9553109aa66c92cf25f182b485
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