FreeBSD/Linux Kernel Cross Reference
sys/pccard/pcic_pci.c
1 /*
2 * Copyright (c) 2000, 2002 M. Warner Losh. All Rights Reserved.
3 * Copyright (c) 1997 Ted Faber All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * 1. Redistributions of source code must retain the above copyright
10 * notice immediately at the beginning of the file, without modification,
11 * this list of conditions, and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. Absolutely no warranty of function or purpose is made by the author
16 * Ted Faber.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 *
29 * $FreeBSD$
30 */
31
32 #include <sys/param.h>
33 #include <sys/bus.h>
34 #include <sys/kernel.h>
35 #include <sys/module.h>
36 #include <sys/sysctl.h>
37 #include <sys/systm.h>
38
39 #if __FreeBSD_version < 500000
40 #include <pci/pcireg.h>
41 #include <pci/pcivar.h>
42 #else
43 #include <dev/pci/pcireg.h>
44 #include <dev/pci/pcivar.h>
45 #endif
46
47 #include <pccard/pcic_pci.h>
48 #include <pccard/i82365.h>
49 #include <pccard/cardinfo.h>
50 #include <pccard/slot.h>
51 #include <pccard/pcicvar.h>
52
53 #include <dev/pccard/pccardvar.h>
54 #include "card_if.h"
55
56 #define PRVERB(x) do { \
57 if (bootverbose) { device_printf x; } \
58 } while (0)
59
60 static int pcic_pci_get_memory(device_t dev);
61
62 SYSCTL_DECL(_hw_pcic);
63
64 static int pcic_ignore_function_1 = 0;
65 TUNABLE_INT("hw.pcic.ignore_function_1", &pcic_ignore_function_1);
66 SYSCTL_INT(_hw_pcic, OID_AUTO, ignore_function_1, CTLFLAG_RD,
67 &pcic_ignore_function_1, 0,
68 "When set, driver ignores pci function 1 of the bridge. This option\n\
69 is obsolete and will be deleted before FreeBSD 4.8.");
70
71 /*
72 * The following should be a hint, so we can do it on a per device
73 * instance, but this is convenient. Do not set this unless pci
74 * routing doesn't work. It is purposely vague and undocumented
75 * at the moment. Sadly, this seems to be needed way too often.
76 */
77 static int pcic_intr_path = (int)pcic_iw_pci;
78 TUNABLE_INT("hw.pcic.intr_path", &pcic_intr_path);
79 SYSCTL_INT(_hw_pcic, OID_AUTO, intr_path, CTLFLAG_RD, &pcic_intr_path, 0,
80 "Which path to send the interrupts over. Normally interrupts for\n\
81 cardbus bridges are routed over the PCI bus (2). However, some laptops\n\
82 will hang when using PCI interrupts due to bugs in this code. Those\n\
83 bugs can be worked around by forcings ISA interrupts (1).");
84
85 static int pcic_init_routing = 0;
86 TUNABLE_INT("hw.pcic.init_routing", &pcic_init_routing);
87 SYSCTL_INT(_hw_pcic, OID_AUTO, init_routing, CTLFLAG_RD,
88 &pcic_init_routing, 0,
89 "Force the interrupt routing to be initialized on those bridges where\n\
90 doing so will cause probelms. This is very rare and generally is not\n\
91 needed. The default of 0 is almost always appropriate. Only set to 1 if\n\
92 instructed to do so for debugging. Only TI bridges are affected by this\n\
93 option, and what the code does is of dubious value. This option is obsolete\n\
94 and will be deleted before FreeBSD 4.8.");
95
96 static int pcic_ignore_pci = 0;
97 TUNABLE_INT("hw.pcic.ignore_pci", &pcic_ignore_pci);
98 SYSCTL_INT(_hw_pcic, OID_AUTO, ignore_pci, CTLFLAG_RD,
99 &pcic_ignore_pci, 0,
100 "When set, driver ignores pci cardbus bridges it would otherwise claim.\n\
101 Generally speaking, this option is not needed for anything other than as an\n\
102 aid in debugging.");
103
104 static int pcic_pd6729_intr_path = (int)pcic_iw_isa;
105 TUNABLE_INT("hw.pcic.pd6729_intr_path", &pcic_pd6729_intr_path);
106 SYSCTL_INT(_hw_pcic, OID_AUTO, pd6729_intr_path, CTLFLAG_RD,
107 &pcic_pd6729_intr_path, 0,
108 "Determine the interrupt path or method for Cirrus Logic PD6729 and\n\
109 similar I/O space based pcmcia bridge. Chips on a PCI expansion card need\n\
110 a value of 2, while chips installed in a laptop need a value of 1 (which is\n\
111 also the default). This is similar to hw.pcic.intr_path, but separate so\n\
112 that it can default to ISA when intr_path defaults to PCI.");
113
114 static int pcic_ti12xx_enable_pci_clock = 0;
115 TUNABLE_INT("hw.pcic.ti12xx_enable_pci_clock", &pcic_ti12xx_enable_pci_clock);
116 SYSCTL_INT(_hw_pcic, OID_AUTO, ti12xx_enable_pci_clock, CTLFLAG_RD,
117 &pcic_ti12xx_enable_pci_clock, 0,
118 "Some TI-12xx parts need to have the PCI clock enabled. These designs do\n\
119 not provide a clock themselves. Most of the reference boards have the\n\
120 required oscillator parts, so the number of machines that needs this to be\n\
121 set is vanishingly small.");
122
123 static void pcic_pci_cardbus_init(device_t);
124 static pcic_intr_way_t pcic_pci_gen_func;
125 static pcic_intr_way_t pcic_pci_gen_csc;
126 static pcic_intr_mapirq_t pcic_pci_gen_mapirq;
127
128 static pcic_intr_way_t pcic_pci_oz67xx_func;
129 static pcic_intr_way_t pcic_pci_oz67xx_csc;
130 static pcic_init_t pcic_pci_oz67xx_init;
131
132 static pcic_intr_way_t pcic_pci_oz68xx_func;
133 static pcic_intr_way_t pcic_pci_oz68xx_csc;
134 static pcic_init_t pcic_pci_oz68xx_init;
135
136 static pcic_intr_way_t pcic_pci_pd6729_func;
137 static pcic_intr_way_t pcic_pci_pd6729_csc;
138 static pcic_init_t pcic_pci_pd6729_init;
139
140 static pcic_intr_way_t pcic_pci_pd68xx_func;
141 static pcic_intr_way_t pcic_pci_pd68xx_csc;
142 static pcic_init_t pcic_pci_pd68xx_init;
143
144 static pcic_intr_way_t pcic_pci_ricoh_func;
145 static pcic_intr_way_t pcic_pci_ricoh_csc;
146 static pcic_init_t pcic_pci_ricoh_init;
147
148 static pcic_intr_way_t pcic_pci_ti113x_func;
149 static pcic_intr_way_t pcic_pci_ti113x_csc;
150 static pcic_init_t pcic_pci_ti_init;
151
152 static pcic_intr_way_t pcic_pci_ti12xx_func;
153 static pcic_intr_way_t pcic_pci_ti12xx_csc;
154
155 static pcic_intr_way_t pcic_pci_topic_func;
156 static pcic_intr_way_t pcic_pci_topic_csc;
157 static pcic_init_t pcic_pci_topic_init;
158
159 static struct pcic_chip pcic_pci_oz67xx_chip = {
160 pcic_pci_oz67xx_func,
161 pcic_pci_oz67xx_csc,
162 pcic_pci_gen_mapirq,
163 pcic_pci_oz67xx_init
164 };
165
166 static struct pcic_chip pcic_pci_oz68xx_chip = {
167 pcic_pci_oz68xx_func,
168 pcic_pci_oz68xx_csc,
169 pcic_pci_gen_mapirq,
170 pcic_pci_oz68xx_init
171 };
172
173 static struct pcic_chip pcic_pci_pd6729_chip = {
174 pcic_pci_pd6729_func,
175 pcic_pci_pd6729_csc,
176 pcic_pci_gen_mapirq,
177 pcic_pci_pd6729_init
178 };
179
180 static struct pcic_chip pcic_pci_pd68xx_chip = {
181 pcic_pci_pd68xx_func,
182 pcic_pci_pd68xx_csc,
183 pcic_pci_gen_mapirq,
184 pcic_pci_pd68xx_init
185 };
186
187 static struct pcic_chip pcic_pci_ricoh_chip = {
188 pcic_pci_ricoh_func,
189 pcic_pci_ricoh_csc,
190 pcic_pci_gen_mapirq,
191 pcic_pci_ricoh_init
192 };
193
194 static struct pcic_chip pcic_pci_ti113x_chip = {
195 pcic_pci_ti113x_func,
196 pcic_pci_ti113x_csc,
197 pcic_pci_gen_mapirq,
198 pcic_pci_ti_init
199 };
200
201 static struct pcic_chip pcic_pci_ti12xx_chip = {
202 pcic_pci_ti12xx_func,
203 pcic_pci_ti12xx_csc,
204 pcic_pci_gen_mapirq,
205 pcic_pci_ti_init
206 };
207
208 static struct pcic_chip pcic_pci_topic_chip = {
209 pcic_pci_topic_func,
210 pcic_pci_topic_csc,
211 pcic_pci_gen_mapirq,
212 pcic_pci_topic_init
213 };
214
215 static struct pcic_chip pcic_pci_generic_chip = {
216 pcic_pci_gen_func,
217 pcic_pci_gen_csc,
218 pcic_pci_gen_mapirq,
219 pcic_pci_cardbus_init
220 };
221
222 /* Chipset specific flags */
223 #define TI_NO_MFUNC 0x10000
224
225 struct pcic_pci_table
226 {
227 u_int32_t devid;
228 const char *descr;
229 int type;
230 u_int32_t flags;
231 struct pcic_chip *chip;
232 } pcic_pci_devs[] = {
233 { PCIC_ID_OMEGA_82C094, "Omega 82C094G",
234 PCIC_I82365, PCIC_DF_POWER, &pcic_pci_pd6729_chip },
235 { PCIC_ID_CLPD6729, "Cirrus Logic PD6729/6730 PCI-PCMCIA Bridge",
236 PCIC_PD6729, PCIC_PD_POWER, &pcic_pci_pd6729_chip },
237 { PCIC_ID_CLPD6832, "Cirrus Logic PD6832 PCI-CardBus Bridge",
238 PCIC_PD673X, PCIC_CARDBUS_POWER, &pcic_pci_pd68xx_chip },
239 { PCIC_ID_CLPD6833, "Cirrus Logic PD6833 PCI-CardBus Bridge",
240 PCIC_PD673X, PCIC_CARDBUS_POWER, &pcic_pci_pd68xx_chip },
241 { PCIC_ID_CLPD6834, "Cirrus Logic PD6834 PCI-CardBus Bridge",
242 PCIC_PD673X, PCIC_CARDBUS_POWER, &pcic_pci_pd68xx_chip },
243 { PCIC_ID_OZ6729, "O2micro OZ6729 PC-Card Bridge",
244 PCIC_I82365, PCIC_AB_POWER, &pcic_pci_oz67xx_chip },
245 { PCIC_ID_OZ6730, "O2micro OZ6730 PC-Card Bridge",
246 PCIC_I82365, PCIC_AB_POWER, &pcic_pci_oz67xx_chip },
247 { PCIC_ID_OZ6832, "O2micro 6832/6833 PCI-Cardbus Bridge",
248 PCIC_I82365, PCIC_CARDBUS_POWER, &pcic_pci_oz68xx_chip },
249 { PCIC_ID_OZ6860, "O2micro 6836/6860 PCI-Cardbus Bridge",
250 PCIC_I82365, PCIC_CARDBUS_POWER, &pcic_pci_oz68xx_chip },
251 { PCIC_ID_OZ6872, "O2micro 6812/6872 PCI-Cardbus Bridge",
252 PCIC_I82365, PCIC_CARDBUS_POWER, &pcic_pci_oz68xx_chip },
253 { PCIC_ID_OZ6912, "O2micro 6912 PCI-Cardbus Bridge",
254 PCIC_I82365, PCIC_CARDBUS_POWER, &pcic_pci_oz68xx_chip },
255 { PCIC_ID_OZ6922, "O2micro 6922 PCI-Cardbus Bridge",
256 PCIC_I82365, PCIC_AB_POWER, &pcic_pci_oz68xx_chip },
257 { PCIC_ID_OZ6933, "O2micro 6933 PCI-Cardbus Bridge",
258 PCIC_I82365, PCIC_AB_POWER, &pcic_pci_oz68xx_chip },
259 { PCIC_ID_RICOH_RL5C465, "Ricoh RL5C465 PCI-CardBus Bridge",
260 PCIC_RF5C296, PCIC_CARDBUS_POWER, &pcic_pci_ricoh_chip },
261 { PCIC_ID_RICOH_RL5C475, "Ricoh RL5C475 PCI-CardBus Bridge",
262 PCIC_RF5C296, PCIC_CARDBUS_POWER, &pcic_pci_ricoh_chip },
263 { PCIC_ID_RICOH_RL5C476, "Ricoh RL5C476 PCI-CardBus Bridge",
264 PCIC_RF5C296, PCIC_CARDBUS_POWER, &pcic_pci_ricoh_chip },
265 { PCIC_ID_RICOH_RL5C477, "Ricoh RL5C477 PCI-CardBus Bridge",
266 PCIC_RF5C296, PCIC_CARDBUS_POWER, &pcic_pci_ricoh_chip },
267 { PCIC_ID_RICOH_RL5C478, "Ricoh RL5C478 PCI-CardBus Bridge",
268 PCIC_RF5C296, PCIC_CARDBUS_POWER, &pcic_pci_ricoh_chip },
269 { PCIC_ID_SMC_34C90, "SMC 34C90 PCI-CardBus Bridge",
270 PCIC_RF5C296, PCIC_CARDBUS_POWER, &pcic_pci_generic_chip },
271 { PCIC_ID_TI1031, "TI PCI-1031 PCI-PCMCIA Bridge",
272 PCIC_I82365SL_DF, PCIC_CARDBUS_POWER, &pcic_pci_ti113x_chip },
273 { PCIC_ID_TI1130, "TI PCI-1130 PCI-CardBus Bridge",
274 PCIC_I82365SL_DF, PCIC_CARDBUS_POWER, &pcic_pci_ti113x_chip },
275 { PCIC_ID_TI1131, "TI PCI-1131 PCI-CardBus Bridge",
276 PCIC_I82365SL_DF, PCIC_CARDBUS_POWER, &pcic_pci_ti113x_chip },
277 { PCIC_ID_TI1210, "TI PCI-1210 PCI-CardBus Bridge",
278 PCIC_I82365SL_DF, PCIC_CARDBUS_POWER, &pcic_pci_ti12xx_chip },
279 { PCIC_ID_TI1211, "TI PCI-1211 PCI-CardBus Bridge",
280 PCIC_I82365SL_DF, PCIC_CARDBUS_POWER, &pcic_pci_ti12xx_chip },
281 { PCIC_ID_TI1220, "TI PCI-1220 PCI-CardBus Bridge",
282 PCIC_I82365SL_DF, PCIC_CARDBUS_POWER, &pcic_pci_ti12xx_chip },
283 { PCIC_ID_TI1221, "TI PCI-1221 PCI-CardBus Bridge",
284 PCIC_I82365SL_DF, PCIC_CARDBUS_POWER, &pcic_pci_ti12xx_chip },
285 { PCIC_ID_TI1225, "TI PCI-1225 PCI-CardBus Bridge",
286 PCIC_I82365SL_DF, PCIC_CARDBUS_POWER, &pcic_pci_ti12xx_chip },
287 { PCIC_ID_TI1250, "TI PCI-1250 PCI-CardBus Bridge",
288 PCIC_I82365SL_DF, PCIC_CARDBUS_POWER | TI_NO_MFUNC,
289 &pcic_pci_ti12xx_chip },
290 { PCIC_ID_TI1251, "TI PCI-1251 PCI-CardBus Bridge",
291 PCIC_I82365SL_DF, PCIC_CARDBUS_POWER | TI_NO_MFUNC,
292 &pcic_pci_ti12xx_chip },
293 { PCIC_ID_TI1251B, "TI PCI-1251B PCI-CardBus Bridge",
294 PCIC_I82365SL_DF, PCIC_CARDBUS_POWER | TI_NO_MFUNC,
295 &pcic_pci_ti12xx_chip },
296 { PCIC_ID_TI1260, "TI PCI-1260 PCI-CardBus Bridge",
297 PCIC_I82365SL_DF, PCIC_CARDBUS_POWER, &pcic_pci_ti12xx_chip },
298 { PCIC_ID_TI1260B, "TI PCI-1260B PCI-CardBus Bridge",
299 PCIC_I82365SL_DF, PCIC_CARDBUS_POWER, &pcic_pci_ti12xx_chip },
300 { PCIC_ID_TI1410, "TI PCI-1410 PCI-CardBus Bridge",
301 PCIC_I82365SL_DF, PCIC_CARDBUS_POWER, &pcic_pci_ti12xx_chip },
302 { PCIC_ID_TI1420, "TI PCI-1420 PCI-CardBus Bridge",
303 PCIC_I82365SL_DF, PCIC_CARDBUS_POWER, &pcic_pci_ti12xx_chip },
304 { PCIC_ID_TI1421, "TI PCI-1421 PCI-CardBus Bridge",
305 PCIC_I82365SL_DF, PCIC_CARDBUS_POWER, &pcic_pci_ti12xx_chip },
306 { PCIC_ID_TI1450, "TI PCI-1450 PCI-CardBus Bridge",
307 PCIC_I82365SL_DF, PCIC_CARDBUS_POWER | TI_NO_MFUNC,
308 &pcic_pci_ti12xx_chip },
309 { PCIC_ID_TI1451, "TI PCI-1451 PCI-CardBus Bridge",
310 PCIC_I82365SL_DF, PCIC_CARDBUS_POWER, &pcic_pci_ti12xx_chip },
311 { PCIC_ID_TI1510, "TI PCI-1510 PCI-CardBus Bridge",
312 PCIC_I82365SL_DF, PCIC_CARDBUS_POWER, &pcic_pci_ti12xx_chip },
313 { PCIC_ID_TI1520, "TI PCI-1520 PCI-CardBus Bridge",
314 PCIC_I82365SL_DF, PCIC_CARDBUS_POWER, &pcic_pci_ti12xx_chip },
315 { PCIC_ID_TI4410, "TI PCI-4410 PCI-CardBus Bridge",
316 PCIC_I82365SL_DF, PCIC_CARDBUS_POWER, &pcic_pci_ti12xx_chip },
317 { PCIC_ID_TI4450, "TI PCI-4450 PCI-CardBus Bridge",
318 PCIC_I82365SL_DF, PCIC_CARDBUS_POWER, &pcic_pci_ti12xx_chip },
319 { PCIC_ID_TI4451, "TI PCI-4451 PCI-CardBus Bridge",
320 PCIC_I82365SL_DF, PCIC_CARDBUS_POWER, &pcic_pci_ti12xx_chip },
321 { PCIC_ID_TI4510, "TI PCI-4510 PCI-CardBus Bridge",
322 PCIC_I82365SL_DF, PCIC_CARDBUS_POWER, &pcic_pci_ti12xx_chip },
323 { PCIC_ID_TOPIC95, "Toshiba ToPIC95 PCI-CardBus Bridge",
324 PCIC_I82365, PCIC_CARDBUS_POWER, &pcic_pci_topic_chip },
325 { PCIC_ID_TOPIC95B, "Toshiba ToPIC95B PCI-CardBus Bridge",
326 PCIC_I82365, PCIC_CARDBUS_POWER, &pcic_pci_topic_chip },
327 { PCIC_ID_TOPIC97, "Toshiba ToPIC97 PCI-CardBus Bridge",
328 PCIC_I82365, PCIC_CARDBUS_POWER, &pcic_pci_topic_chip },
329 { PCIC_ID_TOPIC100, "Toshiba ToPIC100 PCI-CardBus Bridge",
330 PCIC_I82365, PCIC_CARDBUS_POWER, &pcic_pci_topic_chip },
331 { 0, NULL, 0, 0, NULL }
332 };
333
334 /*
335 * Read a register from the PCIC.
336 */
337 static unsigned char
338 pcic_pci_getb2(struct pcic_slot *sp, int reg)
339 {
340 return (bus_space_read_1(sp->bst, sp->bsh, sp->offset + reg));
341 }
342
343 /*
344 * Write a register on the PCIC
345 */
346 static void
347 pcic_pci_putb2(struct pcic_slot *sp, int reg, unsigned char val)
348 {
349 bus_space_write_1(sp->bst, sp->bsh, sp->offset + reg, val);
350 }
351
352 /*
353 * lookup inside the table
354 */
355 static struct pcic_pci_table *
356 pcic_pci_lookup(u_int32_t devid, struct pcic_pci_table *tbl)
357 {
358 while (tbl->devid) {
359 if (tbl->devid == devid)
360 return (tbl);
361 tbl++;
362 }
363 return (NULL);
364 }
365
366 /*
367 * The standard way to control fuction interrupts is via bit 7 in the BCR
368 * register. Some data sheets indicate that this is just for "intterupts"
369 * while others are clear that it is for function interrupts. When this
370 * bit is set, function interrupts are routed via the ExCA register. When
371 * this bit is clear, they are routed via the PCI bus, usually via the int
372 * in the INTPIN register.
373 */
374 static int
375 pcic_pci_gen_func(struct pcic_slot *sp, enum pcic_intr_way way)
376 {
377 u_int16_t bcr;
378
379 bcr = pci_read_config(sp->sc->dev, CB_PCI_BRIDGE_CTRL, 2);
380 if (way == pcic_iw_pci)
381 bcr &= ~CB_BCR_INT_EXCA;
382 else
383 bcr |= CB_BCR_INT_EXCA;
384 pci_write_config(sp->sc->dev, CB_PCI_BRIDGE_CTRL, bcr, 2);
385 return (0);
386 }
387
388 static int
389 pcic_pci_gen_csc(struct pcic_slot *sp, enum pcic_intr_way way)
390 {
391 return (0);
392 }
393
394 /*
395 * The O2micro OZ67xx chips functions.
396 */
397 static int
398 pcic_pci_oz67xx_func(struct pcic_slot *sp, enum pcic_intr_way way)
399 {
400 return (pcic_pci_gen_func(sp, way));
401 }
402
403 static int
404 pcic_pci_oz67xx_csc(struct pcic_slot *sp, enum pcic_intr_way way)
405 {
406 /*
407 * Need datasheet to find out what's going on. However, the
408 * 68xx datasheets are so vague that it is hard to know what
409 * the right thing to do is.
410 */
411 /* XXX */
412 return (0);
413 }
414
415
416 static void
417 pcic_pci_oz67xx_init(device_t dev)
418 {
419 device_printf(dev, "Warning: O2micro OZ67xx chips may not work\n");
420 pcic_pci_cardbus_init(dev);
421 }
422
423 /*
424 * The O2micro OZ68xx chips functions.
425 */
426 static int
427 pcic_pci_oz68xx_func(struct pcic_slot *sp, enum pcic_intr_way way)
428 {
429 return (pcic_pci_gen_func(sp, way));
430 }
431
432 static int
433 pcic_pci_oz68xx_csc(struct pcic_slot *sp, enum pcic_intr_way way)
434 {
435 /*
436 * The 68xx datasheets make it hard to know what the right thing
437 * to do here is. We do what we know, which is nothing, and
438 * hope for the best.
439 */
440 /* XXX */
441 return (0);
442 }
443
444 static void
445 pcic_pci_oz68xx_init(device_t dev)
446 {
447 /*
448 * This is almost certainly incomplete.
449 */
450 device_printf(dev, "Warning: O2micro OZ68xx chips may not work\n");
451 pcic_pci_cardbus_init(dev);
452 }
453
454 /*
455 * The Cirrus Logic PD6729/30. These are weird beasts, so be careful.
456 * They are ISA parts glued to the PCI bus and do not follow the yenta
457 * specification for cardbus bridges. They seem to be similar to the
458 * intel parts that were also cloned by o2micro and maybe others, but
459 * they are so much more common that the author doesn't have experience
460 * with them to know for sure.
461 */
462 static int
463 pcic_pci_pd6729_func(struct pcic_slot *sp, enum pcic_intr_way way)
464 {
465 /*
466 * For pci interrupts, we need to set bit 3 of extension register
467 * 3 to 1. For ISA interrupts, we need to clear it.
468 */
469 sp->putb(sp, PCIC_EXT_IND, PCIC_EXTCTRL1);
470 if (way == pcic_iw_pci)
471 pcic_setb(sp, PCIC_EXTENDED, PCIC_EC1_CARD_IRQ_INV);
472 else
473 pcic_clrb(sp, PCIC_EXTENDED, PCIC_EC1_CARD_IRQ_INV);
474
475 return (0);
476 }
477
478 static int
479 pcic_pci_pd6729_csc(struct pcic_slot *sp, enum pcic_intr_way way)
480 {
481 /*
482 * For pci interrupts, we need to set bit 4 of extension register
483 * 3 to 1. For ISA interrupts, we need to clear it.
484 */
485 sp->putb(sp, PCIC_EXT_IND, PCIC_EXTCTRL1);
486 if (way == pcic_iw_pci)
487 pcic_setb(sp, PCIC_EXTENDED, PCIC_EC1_CSC_IRQ_INV);
488 else
489 pcic_clrb(sp, PCIC_EXTENDED, PCIC_EC1_CSC_IRQ_INV);
490
491 return (0);
492 }
493
494
495 static void
496 pcic_pci_pd6729_init(device_t dev)
497 {
498 struct pcic_softc *sc = device_get_softc(dev);
499
500 /*
501 * Tell the chip to do its routing thing.
502 */
503 pcic_pci_pd6729_func(&sc->slots[0], sc->func_route);
504 pcic_pci_pd6729_csc(&sc->slots[0], sc->csc_route);
505 }
506
507 /*
508 * Set up the CL-PD6832, 6833 and 6834.
509 */
510 static int
511 pcic_pci_pd68xx_func(struct pcic_slot *sp, enum pcic_intr_way way)
512 {
513 return (pcic_pci_gen_func(sp, way));
514 }
515
516 static int
517 pcic_pci_pd68xx_csc(struct pcic_slot *sp, enum pcic_intr_way way)
518 {
519 struct pcic_softc *sc = sp->sc;
520 device_t dev = sc->dev;
521 u_int32_t device_id = pci_get_devid(dev);
522 u_long bcr;
523 u_long cm1;
524
525 /*
526 * CLPD6832 management interrupt enable bit is bit 11
527 * (MGMT_IRQ_ENA) in bridge control register(offset 0x3d).
528 * When on, card status interrupts are ISA controlled by
529 * the ExCA register 0x05.
530 *
531 * The CLPD6833 does things differently. It doesn't have bit
532 * 11 in the bridge control register. Instead, this
533 * functionality appears to be in the "Configuration
534 * Miscellaneous 1" register bit 1.
535 *
536 * I'm assuming that the CLPD6834 does things like the '33
537 */
538 if (device_id == PCIC_ID_CLPD6832) {
539 bcr = pci_read_config(dev, CB_PCI_BRIDGE_CTRL, 2);
540 if (way == pcic_iw_pci)
541 bcr &= ~CLPD6832_BCR_MGMT_IRQ_ENA;
542 else
543 bcr |= CLPD6832_BCR_MGMT_IRQ_ENA;
544 pci_write_config(dev, CB_PCI_BRIDGE_CTRL, bcr, 2);
545 }
546 if (device_id != PCIC_ID_CLPD6832) {
547 cm1 = pci_read_config(dev, CLPD6833_CFG_MISC_1, 4);
548 if (way == pcic_iw_pci)
549 cm1 &= ~CLPD6833_CM1_MGMT_EXCA_ENA;
550 else
551 cm1 |= CLPD6833_CM1_MGMT_EXCA_ENA;
552 pci_write_config(dev, CLPD6833_CFG_MISC_1, cm1, 4);
553 }
554 return (0);
555 }
556
557 static void
558 pcic_pci_pd68xx_init(device_t dev)
559 {
560 pcic_pci_cardbus_init(dev);
561 }
562
563 static int
564 pcic_pci_ricoh_func(struct pcic_slot *sp, enum pcic_intr_way way)
565 {
566 return (pcic_pci_gen_func(sp, way));
567 }
568
569 static int
570 pcic_pci_ricoh_csc(struct pcic_slot *sp, enum pcic_intr_way way)
571 {
572 struct pcic_softc *sc = sp->sc;
573 device_t dev = sc->dev;
574 u_int16_t mcr2;
575
576 /*
577 * For CSC interrupts via ISA, we can't do that exactly.
578 * However, we can disable INT# routing, which is usually what
579 * we want. This is bit 7 in the field. Note, bit 6 looks
580 * interesting, but appears to be unnecessary.
581 */
582 mcr2 = pci_read_config(dev, R5C47X_MISC_CONTROL_REGISTER_2, 2);
583 if (way == pcic_iw_pci)
584 mcr2 &= ~R5C47X_MCR2_CSC_TO_INTX_DISABLE;
585 else
586 mcr2 |= R5C47X_MCR2_CSC_TO_INTX_DISABLE;
587 pci_write_config(dev, R5C47X_MISC_CONTROL_REGISTER_2, mcr2, 2);
588
589 return (0);
590 }
591
592 static void
593 pcic_pci_ricoh_init(device_t dev)
594 {
595 u_int16_t brgcntl;
596 u_int32_t device_id = pci_get_devid(dev);
597
598 switch (device_id) {
599 case PCIC_ID_RICOH_RL5C465:
600 case PCIC_ID_RICOH_RL5C466:
601 /*
602 * Ricoh chips have a legacy bridge enable different than most
603 * Code cribbed from NEWBUS's bridge code since I can't find a
604 * datasheet for them that has register definitions.
605 */
606 brgcntl = pci_read_config(dev, CB_PCI_BRIDGE_CTRL, 2);
607 brgcntl &= ~(CB_BCR_RL_3E2_EN | CB_BCR_RL_3E0_EN);
608 pci_write_config(dev, CB_PCI_BRIDGE_CTRL, brgcntl, 2);
609 break;
610 }
611 pcic_pci_cardbus_init(dev);
612 }
613
614 /*
615 * TI 1030, 1130, and 1131.
616 */
617 static int
618 pcic_pci_ti113x_func(struct pcic_slot *sp, enum pcic_intr_way way)
619 {
620 u_int32_t cardcntl;
621 device_t dev = sp->sc->dev;
622
623 /*
624 * The TI-1130 (and 1030 and 1131) have a different interrupt
625 * routing control than the newer chips. assume we're not
626 * routing either csc or func interrupts via PCI, but enable
627 * as necessary when we find someone uses PCI interrupts. In
628 * order to get any pci interrupts, PCI_IRQ_ENA (bit 5) must
629 * be set. If either PCI_IREQ (bit 4) or PCI_CSC (bit 3) are
630 * set, then set bit 5 at the same time, since setting them
631 * enables the PCI interrupt routing.
632 *
633 * It also appears necessary to set the function routing bit
634 * in the bridge control register, but cardbus_init does that
635 * for us.
636 */
637 cardcntl = pci_read_config(dev, TI113X_PCI_CARD_CONTROL, 1);
638 if (way == pcic_iw_pci)
639 cardcntl |= TI113X_CARDCNTL_PCI_IREQ;
640 else
641 cardcntl &= ~TI113X_CARDCNTL_PCI_IREQ;
642 if (cardcntl & (TI113X_CARDCNTL_PCI_IREQ | TI113X_CARDCNTL_PCI_CSC))
643 cardcntl |= TI113X_CARDCNTL_PCI_IRQ_ENA;
644 else
645 cardcntl &= ~TI113X_CARDCNTL_PCI_IRQ_ENA;
646 pci_write_config(dev, TI113X_PCI_CARD_CONTROL, cardcntl, 1);
647
648 return (pcic_pci_gen_func(sp, way));
649 }
650
651 static int
652 pcic_pci_ti113x_csc(struct pcic_slot *sp, enum pcic_intr_way way)
653 {
654 u_int32_t cardcntl;
655 device_t dev = sp->sc->dev;
656
657 /*
658 * The TI-1130 (and 1030 and 1131) have a different interrupt
659 * routing control than the newer cards. assume we're not
660 * routing PCI, but enable as necessary when we find someone
661 * uses PCI interrupts. In order to get any pci interrupts,
662 * PCI_IRQ_ENA (bit 5) must be set. If either PCI_IREQ (bit
663 * 4) or PCI_CSC (bit 3) are set, then set bit 5 at the same
664 * time, since setting them enables the PCI interrupt routing.
665 *
666 * It also appears necessary to set the function routing bit
667 * in the bridge control register, but cardbus_init does that
668 * for us.
669 */
670 cardcntl = pci_read_config(dev, TI113X_PCI_CARD_CONTROL, 1);
671 if (way == pcic_iw_pci)
672 cardcntl |= TI113X_CARDCNTL_PCI_CSC;
673 else
674 cardcntl &= ~TI113X_CARDCNTL_PCI_CSC;
675 if (cardcntl & (TI113X_CARDCNTL_PCI_IREQ | TI113X_CARDCNTL_PCI_CSC))
676 cardcntl |= TI113X_CARDCNTL_PCI_IRQ_ENA;
677 else
678 cardcntl &= ~TI113X_CARDCNTL_PCI_IRQ_ENA;
679 pci_write_config(dev, TI113X_PCI_CARD_CONTROL, cardcntl, 1);
680
681 return (0);
682 }
683
684 static int
685 pcic_pci_ti12xx_func(struct pcic_slot *sp, enum pcic_intr_way way)
686 {
687 u_int32_t syscntl, devcntl, cardcntl, mfunc;
688 device_t dev = sp->sc->dev;
689
690 syscntl = pci_read_config(dev, TI113X_PCI_SYSTEM_CONTROL, 4);
691 devcntl = pci_read_config(dev, TI113X_PCI_DEVICE_CONTROL, 1);
692 cardcntl = pci_read_config(dev, TI113X_PCI_CARD_CONTROL, 1);
693
694 /*
695 * Special code for the Orinoco cards (and a few others). They
696 * seem to need this special code to make them work only over pci
697 * interrupts. Sadly, doing this code also causes problems for
698 * many laptops, so we have to make it controlled by a tunable.
699 * Actually, experience has shown that this rarely, if ever,
700 * helps.
701 */
702 if (way == pcic_iw_pci) {
703 /*
704 * pcic_init_routing seems to do nothing useful towards
705 * fixing the hang problems. I plan on removing it in
706 * 4.8 or so.
707 */
708 if (pcic_init_routing) {
709 devcntl &= ~TI113X_DEVCNTL_INTR_MASK;
710 pci_write_config(dev, TI113X_PCI_DEVICE_CONTROL,
711 devcntl, 1);
712 syscntl |= TI113X_SYSCNTL_INTRTIE;
713 }
714
715 /*
716 * I've had reports that we need the pci clock enabled,
717 * provide a hook to do so. The number of cards that
718 * require this is quite small.
719 */
720 if (pcic_ti12xx_enable_pci_clock) {
721 syscntl |= TI12XX_SYSCNTL_PCI_CLOCK;
722 pci_write_config(dev, TI113X_PCI_SYSTEM_CONTROL,
723 syscntl, 4);
724 }
725
726 /*
727 * Some PCI add-in cards don't have good EEPROMs on them,
728 * so they get this MUX register wrong. The MUX register
729 * defaults to 0, which is usually wrong for this register,
730 * so we initialize it to make sense.
731 *
732 * We don't bother to turn it off in the ISA case since it
733 * is an initialization issue.
734 *
735 * A few weird TI bridges don't have MFUNC, so filter
736 * those out too.
737 */
738 if ((sp->sc->flags & TI_NO_MFUNC) == 0) {
739 mfunc = pci_read_config(dev, TI12XX_PCI_MFUNC, 4);
740 if (mfunc == 0) {
741 mfunc = (mfunc & ~TI12XX_MFUNC_PIN0) |
742 TI12XX_MFUNC_PIN0_INTA;
743 if ((syscntl & TI113X_SYSCNTL_INTRTIE) == 0)
744 mfunc = (mfunc & ~TI12XX_MFUNC_PIN1) |
745 TI12XX_MFUNC_PIN1_INTB;
746 pci_write_config(dev, TI12XX_PCI_MFUNC, mfunc,
747 4);
748 }
749 }
750
751 }
752 return (pcic_pci_gen_func(sp, way));
753 }
754
755 static int
756 pcic_pci_ti12xx_csc(struct pcic_slot *sp, enum pcic_intr_way way)
757 {
758 /*
759 * Nothing happens here. The TI12xx parts will route the
760 * CSC interrupt via PCI if ExCA register tells it to use
761 * interrupt 0. And via IRQ otherwise (except for reserved
762 * values which may or may not do anything).
763 *
764 * We just hope for the best here that doing nothing is the
765 * right thing to do.
766 */
767 return (0);
768 }
769
770 /*
771 * TI PCI-CardBus Host Adapter specific function code.
772 * This function is separated from pcic_pci_attach().
773 * Takeshi Shibagaki(shiba@jp.freebsd.org).
774 */
775 static void
776 pcic_pci_ti_init(device_t dev)
777 {
778 u_int32_t syscntl, diagctl, devcntl, cardcntl;
779 u_int32_t device_id = pci_get_devid(dev);
780 int ti113x = (device_id == PCIC_ID_TI1031) ||
781 (device_id == PCIC_ID_TI1130) ||
782 (device_id == PCIC_ID_TI1131);
783
784 syscntl = pci_read_config(dev, TI113X_PCI_SYSTEM_CONTROL, 4);
785 devcntl = pci_read_config(dev, TI113X_PCI_DEVICE_CONTROL, 1);
786 cardcntl = pci_read_config(dev, TI113X_PCI_CARD_CONTROL, 1);
787
788 if (ti113x) {
789 device_printf(dev, "TI113X PCI Config Reg: ");
790 if (syscntl & TI113X_SYSCNTL_CLKRUN_ENA) {
791 if (syscntl & TI113X_SYSCNTL_CLKRUN_SEL)
792 printf("[clkrun irq 12]");
793 else
794 printf("[clkrun irq 10]");
795 }
796 } else {
797 device_printf(dev, "TI12XX PCI Config Reg: ");
798
799 /*
800 * Turn on async CSC interrupts. This appears to
801 * be the default, but the old, pre pci-aware, code
802 * did this and it appears PAO does as well.
803 */
804 diagctl = pci_read_config(dev, TI12XX_PCI_DIAGNOSTIC, 1);
805 diagctl |= TI12XX_DIAG_CSC_INTR;
806 pci_write_config(dev, TI12XX_PCI_DIAGNOSTIC, diagctl, 1);
807
808 /*
809 * Turn off Zoom Video. Some cards have this enabled,
810 * some do not but it causes problems when enabled. This
811 * register doesn't exist on the 1130 (and likely the 1131,
812 * but without a datasheet it is impossible to know).
813 * Some 12xx chips may not have it, but setting it is
814 * believed to be harmless on those models.
815 */
816 pci_write_config(dev, TI12XX_PCI_MULTIMEDIA_CONTROL, 0, 4);
817 }
818 if (cardcntl & TI113X_CARDCNTL_RING_ENA)
819 printf("[ring enable]");
820 if (cardcntl & TI113X_CARDCNTL_SPKR_ENA)
821 printf("[speaker enable]");
822 if (syscntl & TI113X_SYSCNTL_PWRSAVINGS)
823 printf("[pwr save]");
824 switch(devcntl & TI113X_DEVCNTL_INTR_MASK){
825 case TI113X_DEVCNTL_INTR_ISA :
826 printf("[CSC parallel isa irq]");
827 break;
828 case TI113X_DEVCNTL_INTR_SERIAL :
829 printf("[CSC serial isa irq]");
830 break;
831 case TI113X_DEVCNTL_INTR_NONE :
832 printf("[pci only]");
833 break;
834 case TI12XX_DEVCNTL_INTR_ALLSERIAL :
835 printf("[FUNC pci int + CSC serial isa irq]");
836 break;
837 }
838 printf("\n");
839 pcic_pci_cardbus_init(dev);
840 }
841
842 /*
843 * Code for TOPIC chips
844 */
845 static int
846 pcic_pci_topic_func(struct pcic_slot *sp, enum pcic_intr_way way)
847 {
848 #ifdef THIS_BRAEKS_THINGS
849 device_t dev = sp->sc->dev;
850 u_int32_t scr;
851
852 scr = pci_read_config(dev, TOPIC_SOCKET_CTRL, 4);
853 if (way == pcic_iw_pci)
854 scr |= TOPIC_SOCKET_CTRL_SCR_IRQSEL;
855 else
856 scr &= ~TOPIC_SOCKET_CTRL_SCR_IRQSEL;
857 pci_write_config(dev, TOPIC_SLOT_CTRL, scr, 4);
858 #endif
859 return (pcic_pci_gen_func(sp, way));
860 }
861
862 static int
863 pcic_pci_topic_csc(struct pcic_slot *sp, enum pcic_intr_way way)
864 {
865 device_t dev = sp->sc->dev;
866 u_int32_t scr;
867 u_int32_t device_id;
868
869 device_id = pci_get_devid(dev);
870 if (device_id == PCIC_ID_TOPIC100 || device_id == PCIC_ID_TOPIC97) {
871 scr = pci_read_config(dev, TOPIC_SLOT_CTRL, 4);
872 if (way == pcic_iw_pci)
873 scr |= TOPIC97_SLOT_CTRL_PCIINT;
874 else
875 scr &= ~TOPIC97_SLOT_CTRL_PCIINT;
876 pci_write_config(dev, TOPIC_SLOT_CTRL, scr, 4);
877 }
878
879 return (0);
880 }
881
882 static void
883 pcic_pci_topic_init(device_t dev)
884 {
885 struct pcic_softc *sc = device_get_softc(dev);
886 u_int32_t reg;
887 u_int32_t device_id;
888
889 device_id = pci_get_devid(dev);
890 reg = pci_read_config(dev, TOPIC_SLOT_CTRL, 4);
891 reg |= (TOPIC_SLOT_CTRL_SLOTON | TOPIC_SLOT_CTRL_SLOTEN |
892 TOPIC_SLOT_CTRL_ID_LOCK | TOPIC_SLOT_CTRL_CARDBUS);
893 reg &= ~TOPIC_SLOT_CTRL_SWDETECT;
894 if (device_id == PCIC_ID_TOPIC100 || device_id == PCIC_ID_TOPIC97) {
895 reg |= TOPIC97_SLOT_CTRL_PCIINT;
896 reg &= ~(TOPIC97_SLOT_CTRL_STSIRQP | TOPIC97_SLOT_CTRL_IRQP);
897 }
898 pci_write_config(dev, TOPIC_SLOT_CTRL, reg, 4);
899 pcic_pci_cardbus_init(dev);
900
901 if (device_id == PCIC_ID_TOPIC100 || device_id == PCIC_ID_TOPIC97) {
902 /*
903 * We need to enable voltage sense and 3V cards explicitly
904 * in the bridge. The datasheets I have for both the
905 * ToPIC 97 and 100 both lists these ports. Without
906 * datasheets for the ToPIC95s, I can't tell if we need
907 * to do it there or not.
908 */
909 pcic_setb(&sc->slots[0], PCIC_TOPIC_FCR,
910 PCIC_FCR_3V_EN | PCIC_FCR_VS_EN);
911 }
912 }
913
914 static void
915 pcic_pci_cardbus_init(device_t dev)
916 {
917 struct pcic_softc *sc = device_get_softc(dev);
918 u_int16_t brgcntl;
919 int unit;
920
921 unit = device_get_unit(dev);
922
923 brgcntl = pci_read_config(dev, CB_PCI_BRIDGE_CTRL, 2);
924 brgcntl |= CB_BCR_WRITE_POST_EN | CB_BCR_MASTER_ABORT;
925 pci_write_config(dev, CB_PCI_BRIDGE_CTRL, brgcntl, 2);
926
927 /* Turn off legacy address */
928 pci_write_config(dev, CB_PCI_LEGACY16_IOADDR, 0, 2);
929
930 /*
931 * Write zeros into the remaining memory I/O windows. This
932 * seems to turn off the pci configuration of these things and
933 * make the cardbus bridge use the values for memory
934 * programmed into the pcic registers.
935 */
936 pci_write_config(dev, CB_PCI_MEMBASE0, 0, 4);
937 pci_write_config(dev, CB_PCI_MEMLIMIT0, 0, 4);
938 pci_write_config(dev, CB_PCI_MEMBASE1, 0, 4);
939 pci_write_config(dev, CB_PCI_MEMLIMIT1, 0, 4);
940 pci_write_config(dev, CB_PCI_IOBASE0, 0, 4);
941 pci_write_config(dev, CB_PCI_IOLIMIT0, 0, 4);
942 pci_write_config(dev, CB_PCI_IOBASE1, 0, 4);
943 pci_write_config(dev, CB_PCI_IOLIMIT1, 0, 4);
944
945 /*
946 * Tell the chip to do its routing thing.
947 */
948 sc->chip->func_intr_way(&sc->slots[0], sc->func_route);
949 sc->chip->csc_intr_way(&sc->slots[0], sc->csc_route);
950
951 return;
952 }
953
954 static const char *
955 pcic_pci_cardtype(u_int32_t stat)
956 {
957 if (stat & CB_SS_NOTCARD)
958 return ("unrecognized by bridge");
959 if ((stat & (CB_SS_16BIT | CB_SS_CB)) == (CB_SS_16BIT | CB_SS_CB))
960 return ("16-bit and 32-bit (can't happen)");
961 if (stat & CB_SS_16BIT)
962 return ("16-bit pccard");
963 if (stat & CB_SS_CB)
964 return ("32-bit cardbus");
965 return ("none (can't happen)");
966 }
967
968 /*
969 * Card insertion and removal code. The insertion events need to be
970 * debounced so that the noisy insertion/removal events don't result
971 * in the hardware being initialized many times, only to be torn down
972 * as well. This may also cause races with pccardd. Instead, we wait
973 * for the insertion signal to be stable for 0.5 seconds before we declare
974 * it to be a real insertion event. Removal is also debounced. We turn
975 * off interrupt servicing during the settling time to prevent infinite
976 * loops in the driver.
977 *
978 * Note: We only handle the card detect change events. We don't handle
979 * power events and status change events.
980 */
981 static void
982 pcic_cd_change(void *arg)
983 {
984 struct pcic_softc *sc = (struct pcic_softc *) arg;
985 struct pcic_slot *sp = &sc->slots[0];
986 u_int32_t stat;
987
988 sc->cd_pending = 0;
989 stat = bus_space_read_4(sp->bst, sp->bsh, CB_SOCKET_STATE);
990
991 /* Status changed while present; remove the card from the system. */
992 if (sc->cd_present) {
993 sc->cd_present = 0;
994 pccard_event(sp->slt, card_removed);
995 }
996 /* Nothing to do if the debounced state is 'not present'. */
997 if ((stat & CB_SS_CD) != 0)
998 return;
999
1000 sc->cd_present = 1;
1001 if (bootverbose && (stat & CB_SS_BADVCC) != 0)
1002 device_printf(sc->dev, "BAD Vcc request: 0x%x\n", stat);
1003 if ((stat & CB_SS_16BIT) == 0)
1004 device_printf(sp->sc->dev, "Card type %s is unsupported\n",
1005 pcic_pci_cardtype(stat));
1006 else
1007 pccard_event(sp->slt, card_inserted);
1008 }
1009
1010 static void
1011 pcic_pci_intr(void *arg)
1012 {
1013 struct pcic_softc *sc = (struct pcic_softc *) arg;
1014 struct pcic_slot *sp = &sc->slots[0];
1015 u_int32_t event;
1016
1017 event = bus_space_read_4(sp->bst, sp->bsh, CB_SOCKET_EVENT);
1018 if (event != 0) {
1019 if (bootverbose)
1020 device_printf(sc->dev, "Event mask 0x%x\n", event);
1021
1022 /*
1023 * Treat all card-detect signal transitions the same way
1024 * since we can't reliably tell if this is an insert or a
1025 * remove event. Stop the card from getting interrupts and
1026 * defer the insert/remove event until the CB_SOCKET_STATE
1027 * signals have had time to settle.
1028 */
1029 if ((event & CB_SE_CD) != 0) {
1030 if (sc->cd_pending) {
1031 untimeout(pcic_cd_change, arg, sc->cd_ch);
1032 sc->cd_pending = 0;
1033 }
1034 sc->cd_pending = 1;
1035 sc->cd_ch = timeout(pcic_cd_change, arg, hz/2);
1036 sc->func_intr = NULL;
1037 }
1038
1039 /* Ack the interrupt */
1040 bus_space_write_4(sp->bst, sp->bsh, 0, event);
1041 }
1042
1043 /*
1044 * Some TI chips also require us to read the old ExCA register for
1045 * card status change when we route CSC via PCI! So, we go ahead
1046 * and read it to clear the bits. Maybe we should check the status
1047 * ala the ISA interrupt handler, but those changes should be caught
1048 * in the CD change.
1049 *
1050 * We have to check it every interrupt because these bits can sometimes
1051 * show up indepentently of the CB_SOCKET_EVENT register above.
1052 */
1053 sp->getb(sp, PCIC_STAT_CHG);
1054 }
1055
1056 /*
1057 * Return the ID string for the controller if the vendor/product id
1058 * matches, NULL otherwise.
1059 */
1060 static int
1061 pcic_pci_probe(device_t dev)
1062 {
1063 u_int8_t subclass;
1064 u_int8_t progif;
1065 const char *desc;
1066 u_int32_t device_id;
1067 struct pcic_pci_table *itm;
1068 struct resource *res;
1069 int rid;
1070
1071 if (pcic_ignore_pci)
1072 return (ENXIO);
1073 device_id = pci_get_devid(dev);
1074 desc = NULL;
1075 itm = pcic_pci_lookup(device_id, &pcic_pci_devs[0]);
1076 if (pcic_ignore_function_1 && pci_get_function(dev) == 1) {
1077 if (itm != NULL)
1078 PRVERB((dev, "Ignoring function 1\n"));
1079 return (ENXIO);
1080 }
1081 if (itm != NULL)
1082 desc = itm->descr;
1083 if (desc == NULL && pci_get_class(dev) == PCIC_BRIDGE) {
1084 subclass = pci_get_subclass(dev);
1085 progif = pci_get_progif(dev);
1086 if (subclass == PCIS_BRIDGE_PCMCIA && progif == 0)
1087 desc = "Generic PCI-PCMCIA Bridge";
1088 if (subclass == PCIS_BRIDGE_CARDBUS && progif == 0)
1089 desc = "YENTA PCI-CardBus Bridge";
1090 if (bootverbose && desc)
1091 printf("Found unknown %s devid 0x%x\n", desc, device_id);
1092 }
1093 if (desc == NULL)
1094 return (ENXIO);
1095 device_set_desc(dev, desc);
1096
1097 /*
1098 * Take us out of power down mode, if necessary. It also
1099 * appears that even reading the power register is enough on
1100 * some systems to cause correct behavior.
1101 */
1102 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
1103 /* Reset the power state. */
1104 device_printf(dev, "chip is in D%d power mode "
1105 "-- setting to D0\n", pci_get_powerstate(dev));
1106 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
1107 }
1108
1109 /*
1110 * Allocated/deallocate interrupt. This forces the PCI BIOS or
1111 * other MD method to route the interrupts to this card.
1112 * This so we get the interrupt number in the probe message.
1113 * We only need to route interrupts when we're doing pci
1114 * parallel interrupt routing.
1115 *
1116 * We use two different variables for the memory based and I/O
1117 * based cards, so the check here is a little more complex than
1118 * one would otherwise hope.
1119 *
1120 * XXX The bus code for PCI really should do this for us.
1121 */
1122 if ((pcic_intr_path == pcic_iw_pci &&
1123 device_id != PCIC_ID_CLPD6729) ||
1124 (pcic_pd6729_intr_path == pcic_iw_pci &&
1125 device_id == PCIC_ID_CLPD6729)) {
1126 rid = 0;
1127 #ifdef __i386__
1128 /*
1129 * IRQ 0 is invalid on x86, but not other platforms.
1130 * If we have irq 0, then write 255 to force a new, non-
1131 * bogus one to be assigned. I think that in -current
1132 * the code in this ifdef may be obsolete with the new
1133 * invalid mapping that we're doing in the pci layer -- imp
1134 */
1135 if (pci_get_irq(dev) == 0) {
1136 pci_set_irq(dev, 255);
1137 pci_write_config(dev, PCIR_INTLINE, 255, 1);
1138 }
1139 #endif
1140 res = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1,
1141 RF_ACTIVE);
1142 if (res)
1143 bus_release_resource(dev, SYS_RES_IRQ, rid, res);
1144 }
1145
1146 return (0);
1147 }
1148
1149 static void
1150 pcic_pci_shutdown(device_t dev)
1151 {
1152 /*
1153 * More reports of things working w/o this code than with it.
1154 */
1155 #if 0
1156 struct pcic_softc *sc;
1157 struct pcic_slot *sp;
1158
1159 sc = (struct pcic_softc *) device_get_softc(dev);
1160 sp = &sc->slots[0];
1161
1162 /*
1163 * Turn off the power to the slot in an attempt to
1164 * keep the system from hanging on reboot. We also turn off
1165 * card interrupts in an attempt to control interrupt storms.
1166 * on some (all?) this has the effect of also turning off
1167 * card status change interrupts. A side effect of writing 0
1168 * to INT_GEN is that the card is placed into "reset" mode
1169 * where nothing happens until it is taken out of "reset"
1170 * mode.
1171 *
1172 * Also, turn off the generation of status interrupts too.
1173 */
1174 sp->putb(sp, PCIC_INT_GEN, 0);
1175 sp->putb(sp, PCIC_STAT_INT, 0);
1176 sp->putb(sp, PCIC_POWER, 0);
1177 DELAY(4000);
1178
1179 /*
1180 * Writing to INT_GEN can cause an interrupt, so we blindly
1181 * ack all possible interrupts here. Reading the stat change
1182 * shouldn't be necessary, but some TI chipsets need it in the
1183 * normal course of operations, so we do it here too. We can't
1184 * lose any interrupts after this point, so go ahead and ack
1185 * everything. The bits in INT_GEN clear upon reading them.
1186 * We also set the interrupt mask to 0, in an effort to avoid
1187 * getting further interrupts.
1188 */
1189 bus_space_write_4(sp->bst, sp->bsh, CB_SOCKET_MASK, 0);
1190 bus_space_write_4(sp->bst, sp->bsh, CB_SOCKET_EVENT, 0xffffffff);
1191 sp->getb(sp, PCIC_STAT_CHG);
1192 #endif
1193 }
1194
1195 /*
1196 * Print out the config space
1197 */
1198 static void
1199 pcic_pci_print_config(device_t dev)
1200 {
1201 int i;
1202
1203 device_printf(dev, "PCI Configuration space:");
1204 for (i = 0; i < 256; i += 4) {
1205 if (i % 16 == 0)
1206 printf("\n 0x%02x: ", i);
1207 printf("0x%08x ", pci_read_config(dev, i, 4));
1208 }
1209 printf("\n");
1210 }
1211
1212 /*
1213 * Generic pci interrupt attach routine. It tries to understand all parts,
1214 * and do sane things for those parts it does not understand.
1215 */
1216 static int
1217 pcic_pci_attach(device_t dev)
1218 {
1219 u_int32_t device_id = pci_get_devid(dev);
1220 u_long command;
1221 struct pcic_slot *sp;
1222 struct pcic_softc *sc;
1223 u_int32_t sockbase;
1224 u_int32_t stat;
1225 struct pcic_pci_table *itm;
1226 int rid;
1227 int i;
1228 struct resource *r = NULL;
1229 int error;
1230 u_long irq = 0;
1231 driver_intr_t *intr = NULL;
1232
1233 /*
1234 * In sys/pci/pcireg.h, PCIR_COMMAND must be separated
1235 * PCI_COMMAND_REG(0x04) and PCI_STATUS_REG(0x06).
1236 * Takeshi Shibagaki(shiba@jp.freebsd.org).
1237 */
1238 command = pci_read_config(dev, PCIR_COMMAND, 4);
1239 command |= PCIM_CMD_PORTEN | PCIM_CMD_MEMEN;
1240 pci_write_config(dev, PCIR_COMMAND, command, 4);
1241
1242 sc = (struct pcic_softc *) device_get_softc(dev);
1243 sp = &sc->slots[0];
1244 sp->sc = sc;
1245 sockbase = pci_read_config(dev, 0x10, 4);
1246 if (sockbase & 0x1) {
1247 sc->iorid = CB_PCI_SOCKET_BASE;
1248 sc->iores = bus_alloc_resource(dev, SYS_RES_IOPORT,
1249 &sc->iorid, 0, ~0, 1, RF_ACTIVE | RF_SHAREABLE);
1250 if (sc->iores == NULL)
1251 return (ENOMEM);
1252
1253 sc->flags = PCIC_PD_POWER;
1254 itm = pcic_pci_lookup(device_id, &pcic_pci_devs[0]);
1255 for (i = 0; i < 2; i++) {
1256 sp[i].bst = rman_get_bustag(sc->iores);
1257 sp[i].bsh = rman_get_bushandle(sc->iores);
1258 sp[i].sc = sc;
1259 sp[i].revision = 0;
1260 sp[i].getb = pcic_getb_io;
1261 sp[i].putb = pcic_putb_io;
1262 sp[i].offset = i * PCIC_SLOT_SIZE;
1263 sp[i].controller = itm ? itm->type : PCIC_PD6729;
1264 if ((sp[i].getb(&sp[i], PCIC_ID_REV) & 0xc0) == 0x80)
1265 sp[i].slt = (struct slot *) 1;
1266 }
1267 sc->csc_route = sc->func_route = pcic_pd6729_intr_path;
1268 if (itm)
1269 sc->flags = itm->flags;
1270 /*
1271 * We have to use the ISA interrupt routine for status
1272 * changes since we don't have any "yenta" pci registers.
1273 * We have to do this even when we're using pci type
1274 * interrupts because on these cards the interrupts are
1275 * cleared in the same way that the ISA cards clear them.
1276 */
1277 intr = pcic_isa_intr;
1278 } else {
1279 sc->memrid = CB_PCI_SOCKET_BASE;
1280 sc->memres = bus_alloc_resource(dev, SYS_RES_MEMORY,
1281 &sc->memrid, 0, ~0, 1, RF_ACTIVE);
1282 if (sc->memres == NULL && pcic_pci_get_memory(dev) != 0)
1283 return (ENOMEM);
1284 sp->getb = pcic_pci_getb2;
1285 sp->putb = pcic_pci_putb2;
1286 sp->offset = CB_EXCA_OFFSET;
1287 sp->bst = rman_get_bustag(sc->memres);
1288 sp->bsh = rman_get_bushandle(sc->memres);
1289 itm = pcic_pci_lookup(device_id, &pcic_pci_devs[0]);
1290 if (itm != NULL) {
1291 sp->controller = itm->type;
1292 sp->revision = 0;
1293 sc->flags = itm->flags;
1294 } else {
1295 /* By default, assume we're a D step compatible */
1296 sp->controller = PCIC_I82365SL_DF;
1297 sp->revision = 0;
1298 sc->flags = PCIC_CARDBUS_POWER;
1299 }
1300 /* All memory mapped cardbus bridges have these registers */
1301 sc->flags |= PCIC_YENTA_HIGH_MEMORY;
1302 sp->slt = (struct slot *) 1;
1303 sc->csc_route = pcic_intr_path;
1304 sc->func_route = pcic_intr_path;
1305 stat = bus_space_read_4(sp->bst, sp->bsh, CB_SOCKET_STATE);
1306 sc->cd_present = (stat & CB_SS_CD) == 0;
1307 }
1308 sc->dev = dev;
1309 if (itm)
1310 sc->chip = itm->chip;
1311 else
1312 sc->chip = &pcic_pci_generic_chip;
1313
1314 if (sc->csc_route == pcic_iw_pci) {
1315 rid = 0;
1316 r = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1,
1317 RF_ACTIVE | RF_SHAREABLE);
1318 if (r == NULL) {
1319 sc->csc_route = pcic_iw_isa;
1320 sc->func_route = pcic_iw_isa;
1321 device_printf(dev,
1322 "No PCI interrupt routed, trying ISA.\n");
1323 } else {
1324 if (intr == NULL)
1325 intr = pcic_pci_intr;
1326 irq = rman_get_start(r);
1327 }
1328 }
1329 if (sc->csc_route == pcic_iw_isa) {
1330 rid = 0;
1331 irq = pcic_override_irq;
1332 if (irq != 0) {
1333 r = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, irq,
1334 irq, 1, RF_ACTIVE);
1335 if (r == NULL) {
1336 device_printf(dev,
1337 "Can't route ISA CSC interrupt.\n");
1338 pcic_dealloc(dev);
1339 return (ENXIO);
1340 }
1341 device_printf(dev,
1342 "Management interrupt on ISA IRQ %ld\n", irq);
1343 if (intr == NULL)
1344 intr = pcic_isa_intr;
1345 } else {
1346 sc->slot_poll = pcic_timeout;
1347 sc->timeout_ch = timeout(sc->slot_poll, sc, hz/2);
1348 device_printf(dev, "Polling mode\n");
1349 intr = NULL;
1350 }
1351 }
1352
1353 /*
1354 * Initialize AFTER we figure out what kind of interrupt we're
1355 * going to be using, if any.
1356 */
1357 if (!sc->chip)
1358 panic("Bug: sc->chip not set!\n");
1359 sc->chip->init(dev);
1360
1361 /*
1362 * Now install the interrupt handler, if necessary.
1363 */
1364 sc->irqrid = rid;
1365 sc->irqres = r;
1366 sc->irq = irq;
1367 if (intr) {
1368 error = bus_setup_intr(dev, r, INTR_TYPE_AV, intr, sc, &sc->ih);
1369 if (error) {
1370 pcic_dealloc(dev);
1371 return (error);
1372 }
1373 }
1374 if (bootverbose)
1375 pcic_pci_print_config(dev);
1376 return (pcic_attach(dev));
1377 }
1378
1379 static int
1380 pcic_pci_detach(device_t dev)
1381 {
1382 return (EBUSY); /* Can't detach this device */
1383 }
1384
1385 /*
1386 * The PCI bus should do this for us. However, it doesn't quite yet, so
1387 * we cope by doing it ourselves. If it ever does, this code can go quietly
1388 * into that good night.
1389 */
1390 static int
1391 pcic_pci_get_memory(device_t dev)
1392 {
1393 struct pcic_softc *sc;
1394 u_int32_t sockbase;
1395
1396 sc = (struct pcic_softc *) device_get_softc(dev);
1397 sockbase = pci_read_config(dev, sc->memrid, 4);
1398 if (sockbase >= 0x100000 && sockbase < 0xfffffff0) {
1399 device_printf(dev, "Could not map register memory 0x%x\n",
1400 sockbase);
1401 return (ENOMEM);
1402 }
1403 pci_write_config(dev, sc->memrid, 0xffffffff, 4);
1404 sockbase = pci_read_config(dev, sc->memrid, 4);
1405 sockbase = (sockbase & 0xfffffff0) & -(sockbase & 0xfffffff0);
1406 #define CARDBUS_SYS_RES_MEMORY_START 0x88000000
1407 #define CARDBUS_SYS_RES_MEMORY_END 0xFFFFFFFF
1408 sc->memres = bus_generic_alloc_resource(device_get_parent(dev),
1409 dev, SYS_RES_MEMORY, &sc->memrid,
1410 CARDBUS_SYS_RES_MEMORY_START, CARDBUS_SYS_RES_MEMORY_END,
1411 sockbase, RF_ACTIVE | rman_make_alignment_flags(sockbase));
1412 if (sc->memres == NULL) {
1413 device_printf(dev, "Could not grab register memory\n");
1414 return (ENOMEM);
1415 }
1416 sockbase = rman_get_start(sc->memres);
1417 pci_write_config(dev, sc->memrid, sockbase, 4);
1418 device_printf(dev, "PCI Memory allocated: 0x%08x\n", sockbase);
1419 return (0);
1420 }
1421
1422 static int
1423 pcic_pci_gen_mapirq(struct pcic_slot *sp, int irq)
1424 {
1425 /*
1426 * If we're doing ISA interrupt routing, then just go to the
1427 * generic ISA routine. Also, irq 0 means turn off the interrupts
1428 * at the bridge.
1429 */
1430 if (sp->sc->func_route == pcic_iw_isa || irq == 0)
1431 return (pcic_isa_mapirq(sp, irq));
1432
1433 /*
1434 * Ohterwise we're doing PCI interrupts. For those cardbus bridges
1435 * that follow yenta (and the one pcmcia bridge that does), we don't
1436 * do a thing to get the IRQ mapped into the system. However,
1437 * for other controllers that are PCI, but not yetna compliant, we
1438 * need to do some special mapping.
1439 *
1440 * XXX Maybe we shouldn't assume INTA#, but rather as the function
1441 * XXX what Intline to use.
1442 */
1443 if (sp->controller == PCIC_PD6729) {
1444 /*
1445 * INTA - 3
1446 * INTB - 4
1447 * INTC - 5
1448 * INTD - 7
1449 */
1450 sp->putb(sp, PCIC_INT_GEN, /* Assume INTA# */
1451 (sp->getb(sp, PCIC_INT_GEN) & 0xF0) | 3);
1452 return (0);
1453 }
1454 return (0);
1455 }
1456
1457 static void
1458 pcic_pci_func_intr(void *arg)
1459 {
1460 struct pcic_softc *sc = (struct pcic_softc *) arg;
1461 struct pcic_slot *sp = &sc->slots[0];
1462 u_int32_t stat;
1463 int doit = 0;
1464
1465 /*
1466 * The 6729 controller is a weird one, and we have to use
1467 * the ISA registers to check to see if the card is there.
1468 * Otherwise we look at the PCI state register to find out
1469 * if the card is there.
1470 */
1471 if (sp->controller == PCIC_PD6729) {
1472 if ((sp->getb(sp, PCIC_STATUS) & PCIC_CD) == PCIC_CD)
1473 doit = 1;
1474 }
1475 else {
1476 stat = bus_space_read_4(sp->bst, sp->bsh, CB_SOCKET_STATE);
1477 if ((stat & CB_SS_CD) == 0 && sc->func_intr != 0)
1478 doit = 1;
1479 }
1480 if (doit && sc->func_intr != NULL)
1481 sc->func_intr(sc->func_arg);
1482 }
1483
1484 static int
1485 pcic_pci_setup_intr(device_t dev, device_t child, struct resource *irq,
1486 int flags, driver_intr_t *intr, void *arg, void **cookiep)
1487 {
1488 struct pcic_softc *sc = device_get_softc(dev);
1489 struct pcic_slot *sp = &sc->slots[0];
1490 int err;
1491
1492 if (sc->func_route == pcic_iw_isa)
1493 return(pcic_setup_intr(dev, child, irq, flags, intr, arg,
1494 cookiep));
1495
1496 #if __FreeBSD_version >= 500000
1497 if ((flags & INTR_FAST) != 0)
1498 #else
1499 if ((flags & INTR_TYPE_FAST) != 0)
1500 #endif
1501 return (EINVAL);
1502 if (sc->func_intr != NULL) {
1503 device_printf(child, "Can't establish another ISR\n");
1504 return (EINVAL);
1505 }
1506
1507 err = bus_generic_setup_intr(dev, child, irq, flags,
1508 pcic_pci_func_intr, sc, cookiep);
1509 if (err != 0)
1510 return (err);
1511 sc->chip->map_irq(sp, rman_get_start(irq));
1512 sc->func_intr = intr;
1513 sc->func_arg = arg;
1514 return (0);
1515 }
1516
1517 static int
1518 pcic_pci_teardown_intr(device_t dev, device_t child, struct resource *irq,
1519 void *cookie)
1520 {
1521 struct pcic_softc *sc = device_get_softc(dev);
1522
1523 if (sc->func_route == pcic_iw_isa)
1524 return (pcic_teardown_intr(dev, child, irq, cookie));
1525 sc->func_intr = NULL;
1526 return (bus_generic_teardown_intr(dev, child, irq, cookie));
1527 }
1528
1529 static int
1530 pcic_pci_resume(device_t dev)
1531 {
1532 struct pcic_softc *sc = device_get_softc(dev);
1533
1534 /*
1535 * Some BIOSes will not save the BARs for the pci chips, so we
1536 * must do it ourselves. If the BAR is reset to 0 for an I/O
1537 * device, it will read back as 0x1, so no explicit test for
1538 * memory devices are needed.
1539 *
1540 * Note: The PCI bus code should do this automatically for us on
1541 * suspend/resume, but until it does, we have to cope.
1542 */
1543 if (pci_read_config(dev, CB_PCI_SOCKET_BASE, 4) == 0)
1544 pci_write_config(dev, CB_PCI_SOCKET_BASE,
1545 rman_get_start(sc->memres), 4);
1546 return (bus_generic_resume(dev));
1547 }
1548
1549 static device_method_t pcic_pci_methods[] = {
1550 /* Device interface */
1551 DEVMETHOD(device_probe, pcic_pci_probe),
1552 DEVMETHOD(device_attach, pcic_pci_attach),
1553 DEVMETHOD(device_detach, pcic_pci_detach),
1554 DEVMETHOD(device_suspend, bus_generic_suspend),
1555 DEVMETHOD(device_resume, pcic_pci_resume),
1556 DEVMETHOD(device_shutdown, pcic_pci_shutdown),
1557
1558 /* Bus interface */
1559 DEVMETHOD(bus_print_child, bus_generic_print_child),
1560 DEVMETHOD(bus_alloc_resource, pcic_alloc_resource),
1561 DEVMETHOD(bus_release_resource, bus_generic_release_resource),
1562 DEVMETHOD(bus_activate_resource, pcic_activate_resource),
1563 DEVMETHOD(bus_deactivate_resource, pcic_deactivate_resource),
1564 DEVMETHOD(bus_setup_intr, pcic_pci_setup_intr),
1565 DEVMETHOD(bus_teardown_intr, pcic_pci_teardown_intr),
1566
1567 /* Card interface */
1568 DEVMETHOD(card_set_res_flags, pcic_set_res_flags),
1569 DEVMETHOD(card_get_res_flags, pcic_get_res_flags),
1570 DEVMETHOD(card_set_memory_offset, pcic_set_memory_offset),
1571 DEVMETHOD(card_get_memory_offset, pcic_get_memory_offset),
1572
1573 {0, 0}
1574 };
1575
1576 static driver_t pcic_pci_driver = {
1577 "pcic",
1578 pcic_pci_methods,
1579 sizeof(struct pcic_softc)
1580 };
1581
1582 DRIVER_MODULE(pcic, pci, pcic_pci_driver, pcic_devclass, 0, 0);
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