FreeBSD/Linux Kernel Cross Reference
sys/pccard/pcic_pci.c
1 /*
2 * Copyright (c) 2001 M. Warner Losh. All Rights Reserved.
3 * Copyright (c) 1997 Ted Faber All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * 1. Redistributions of source code must retain the above copyright
10 * notice immediately at the beginning of the file, without modification,
11 * this list of conditions, and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. Absolutely no warranty of function or purpose is made by the author
16 * Ted Faber.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 *
29 * $FreeBSD: releng/5.0/sys/pccard/pcic_pci.c 104607 2002-10-07 07:02:48Z imp $
30 */
31
32 #include <sys/param.h>
33 #include <sys/bus.h>
34 #include <sys/kernel.h>
35 #include <sys/module.h>
36 #include <sys/sysctl.h>
37 #include <sys/systm.h>
38
39 #if __FreeBSD_version < 500000
40 #include <pci/pcireg.h>
41 #include <pci/pcivar.h>
42 #else
43 #include <dev/pci/pcireg.h>
44 #include <dev/pci/pcivar.h>
45 #endif
46
47 #include <pccard/pcic_pci.h>
48 #include <pccard/i82365.h>
49 #include <pccard/cardinfo.h>
50 #include <pccard/slot.h>
51 #include <pccard/pcicvar.h>
52
53 #include <dev/pccard/pccardvar.h>
54 #include "card_if.h"
55
56 #define PRVERB(x) do { \
57 if (bootverbose) { device_printf x; } \
58 } while (0)
59
60 static int pcic_pci_get_memory(device_t dev);
61
62 SYSCTL_DECL(_hw_pcic);
63
64 static int pcic_ignore_function_1 = 0;
65 TUNABLE_INT("hw.pcic.ignore_function_1", &pcic_ignore_function_1);
66 SYSCTL_INT(_hw_pcic, OID_AUTO, ignore_function_1, CTLFLAG_RD,
67 &pcic_ignore_function_1, 0,
68 "When set, driver ignores pci function 1 of the bridge. This option\n\
69 is obsolete and will be deleted before FreeBSD 4.8.");
70
71 /*
72 * The following should be a hint, so we can do it on a per device
73 * instance, but this is convenient. Do not set this unless pci
74 * routing doesn't work. It is purposely vague and undocumented
75 * at the moment. Sadly, this seems to be needed way too often.
76 */
77 static int pcic_intr_path = (int)pcic_iw_pci;
78 TUNABLE_INT("hw.pcic.intr_path", &pcic_intr_path);
79 SYSCTL_INT(_hw_pcic, OID_AUTO, intr_path, CTLFLAG_RD, &pcic_intr_path, 0,
80 "Which path to send the interrupts over. Normally interrupts for\n\
81 cardbus bridges are routed over the PCI bus (2). However, some laptops\n\
82 will hang when using PCI interrupts due to bugs in this code. Those\n\
83 bugs can be worked around by forcings ISA interrupts (1).");
84
85 static int pcic_init_routing = 0;
86 TUNABLE_INT("hw.pcic.init_routing", &pcic_init_routing);
87 SYSCTL_INT(_hw_pcic, OID_AUTO, init_routing, CTLFLAG_RD,
88 &pcic_init_routing, 0,
89 "Force the interrupt routing to be initialized on those bridges where\n\
90 doing so will cause probelms. This is very rare and generally is not\n\
91 needed. The default of 0 is almost always appropriate. Only set to 1 if\n\
92 instructed to do so for debugging. Only TI bridges are affected by this\n\
93 option, and what the code does is of dubious value. This option is obsolete\n\
94 and will be deleted before FreeBSD 4.8.");
95
96 static int pcic_ignore_pci = 0;
97 TUNABLE_INT("hw.pcic.ignore_pci", &pcic_ignore_pci);
98 SYSCTL_INT(_hw_pcic, OID_AUTO, ignore_pci, CTLFLAG_RD,
99 &pcic_ignore_pci, 0,
100 "When set, driver ignores pci cardbus bridges it would otherwise claim.\n\
101 Generally speaking, this option is not needed for anything other than as an\n\
102 aid in debugging.");
103
104 static int pcic_pd6729_intr_path = (int)pcic_iw_isa;
105 TUNABLE_INT("hw.pcic.pd6729_intr_path", &pcic_pd6729_intr_path);
106 SYSCTL_INT(_hw_pcic, OID_AUTO, pd6729_intr_path, CTLFLAG_RD,
107 &pcic_pd6729_intr_path, 0,
108 "Determine the interrupt path or method for Cirrus Logic PD6729 and\n\
109 similar I/O space based pcmcia bridge. Chips on a PCI expansion card need\n\
110 a value of 2, while chips installed in a laptop need a value of 1 (which is\n\
111 also the default). This is similar to hw.pcic.intr_path, but separate so\n\
112 that it can default to ISA when intr_path defaults to PCI.");
113
114 static void pcic_pci_cardbus_init(device_t);
115 static pcic_intr_way_t pcic_pci_gen_func;
116 static pcic_intr_way_t pcic_pci_gen_csc;
117 static pcic_intr_mapirq_t pcic_pci_gen_mapirq;
118
119 static pcic_intr_way_t pcic_pci_oz67xx_func;
120 static pcic_intr_way_t pcic_pci_oz67xx_csc;
121 static pcic_init_t pcic_pci_oz67xx_init;
122
123 static pcic_intr_way_t pcic_pci_oz68xx_func;
124 static pcic_intr_way_t pcic_pci_oz68xx_csc;
125 static pcic_init_t pcic_pci_oz68xx_init;
126
127 static pcic_intr_way_t pcic_pci_pd67xx_func;
128 static pcic_intr_way_t pcic_pci_pd67xx_csc;
129 static pcic_init_t pcic_pci_pd67xx_init;
130
131 static pcic_intr_way_t pcic_pci_pd68xx_func;
132 static pcic_intr_way_t pcic_pci_pd68xx_csc;
133 static pcic_init_t pcic_pci_pd68xx_init;
134
135 static pcic_intr_way_t pcic_pci_ricoh_func;
136 static pcic_intr_way_t pcic_pci_ricoh_csc;
137 static pcic_init_t pcic_pci_ricoh_init;
138
139 static pcic_intr_way_t pcic_pci_ti113x_func;
140 static pcic_intr_way_t pcic_pci_ti113x_csc;
141 static pcic_init_t pcic_pci_ti_init;
142
143 static pcic_intr_way_t pcic_pci_ti12xx_func;
144 static pcic_intr_way_t pcic_pci_ti12xx_csc;
145
146 static pcic_intr_way_t pcic_pci_topic_func;
147 static pcic_intr_way_t pcic_pci_topic_csc;
148 static pcic_init_t pcic_pci_topic_init;
149
150 static struct pcic_chip pcic_pci_oz67xx_chip = {
151 pcic_pci_oz67xx_func,
152 pcic_pci_oz67xx_csc,
153 pcic_pci_gen_mapirq,
154 pcic_pci_oz67xx_init
155 };
156
157 static struct pcic_chip pcic_pci_oz68xx_chip = {
158 pcic_pci_oz68xx_func,
159 pcic_pci_oz68xx_csc,
160 pcic_pci_gen_mapirq,
161 pcic_pci_oz68xx_init
162 };
163
164 static struct pcic_chip pcic_pci_pd67xx_chip = {
165 pcic_pci_pd67xx_func,
166 pcic_pci_pd67xx_csc,
167 pcic_pci_gen_mapirq,
168 pcic_pci_pd67xx_init
169 };
170
171 static struct pcic_chip pcic_pci_pd68xx_chip = {
172 pcic_pci_pd68xx_func,
173 pcic_pci_pd68xx_csc,
174 pcic_pci_gen_mapirq,
175 pcic_pci_pd68xx_init
176 };
177
178 static struct pcic_chip pcic_pci_ricoh_chip = {
179 pcic_pci_ricoh_func,
180 pcic_pci_ricoh_csc,
181 pcic_pci_gen_mapirq,
182 pcic_pci_ricoh_init
183 };
184
185 static struct pcic_chip pcic_pci_ti113x_chip = {
186 pcic_pci_ti113x_func,
187 pcic_pci_ti113x_csc,
188 pcic_pci_gen_mapirq,
189 pcic_pci_ti_init
190 };
191
192 static struct pcic_chip pcic_pci_ti12xx_chip = {
193 pcic_pci_ti12xx_func,
194 pcic_pci_ti12xx_csc,
195 pcic_pci_gen_mapirq,
196 pcic_pci_ti_init
197 };
198
199 static struct pcic_chip pcic_pci_topic_chip = {
200 pcic_pci_topic_func,
201 pcic_pci_topic_csc,
202 pcic_pci_gen_mapirq,
203 pcic_pci_topic_init
204 };
205
206 static struct pcic_chip pcic_pci_generic_chip = {
207 pcic_pci_gen_func,
208 pcic_pci_gen_csc,
209 pcic_pci_gen_mapirq,
210 pcic_pci_cardbus_init
211 };
212
213 /* Chipset specific flags */
214 #define TI_NO_MFUNC 0x10000
215
216 struct pcic_pci_table
217 {
218 u_int32_t devid;
219 const char *descr;
220 int type;
221 u_int32_t flags;
222 struct pcic_chip *chip;
223 } pcic_pci_devs[] = {
224 { PCIC_ID_OMEGA_82C094, "Omega 82C094G",
225 PCIC_I82365, PCIC_DF_POWER, &pcic_pci_pd67xx_chip },
226 { PCIC_ID_CLPD6729, "Cirrus Logic PD6729/6730 PCI-PCMCIA Bridge",
227 PCIC_PD6729, PCIC_PD_POWER, &pcic_pci_pd67xx_chip },
228 { PCIC_ID_CLPD6832, "Cirrus Logic PD6832 PCI-CardBus Bridge",
229 PCIC_PD673X, PCIC_CARDBUS_POWER, &pcic_pci_pd68xx_chip },
230 { PCIC_ID_CLPD6833, "Cirrus Logic PD6833 PCI-CardBus Bridge",
231 PCIC_PD673X, PCIC_CARDBUS_POWER, &pcic_pci_pd68xx_chip },
232 { PCIC_ID_CLPD6834, "Cirrus Logic PD6834 PCI-CardBus Bridge",
233 PCIC_PD673X, PCIC_CARDBUS_POWER, &pcic_pci_pd68xx_chip },
234 { PCIC_ID_OZ6729, "O2micro OZ6729 PC-Card Bridge",
235 PCIC_I82365, PCIC_AB_POWER, &pcic_pci_oz67xx_chip },
236 { PCIC_ID_OZ6730, "O2micro OZ6730 PC-Card Bridge",
237 PCIC_I82365, PCIC_AB_POWER, &pcic_pci_oz67xx_chip },
238 { PCIC_ID_OZ6832, "O2micro 6832/6833 PCI-Cardbus Bridge",
239 PCIC_I82365, PCIC_CARDBUS_POWER, &pcic_pci_oz68xx_chip },
240 { PCIC_ID_OZ6860, "O2micro 6836/6860 PCI-Cardbus Bridge",
241 PCIC_I82365, PCIC_CARDBUS_POWER, &pcic_pci_oz68xx_chip },
242 { PCIC_ID_OZ6872, "O2micro 6812/6872 PCI-Cardbus Bridge",
243 PCIC_I82365, PCIC_CARDBUS_POWER, &pcic_pci_oz68xx_chip },
244 { PCIC_ID_OZ6912, "O2micro 6912 PCI-Cardbus Bridge",
245 PCIC_I82365, PCIC_CARDBUS_POWER, &pcic_pci_oz68xx_chip },
246 { PCIC_ID_OZ6922, "O2micro 6922 PCI-Cardbus Bridge",
247 PCIC_I82365, PCIC_AB_POWER, &pcic_pci_oz68xx_chip },
248 { PCIC_ID_OZ6933, "O2micro 6933 PCI-Cardbus Bridge",
249 PCIC_I82365, PCIC_AB_POWER, &pcic_pci_oz68xx_chip },
250 { PCIC_ID_RICOH_RL5C465, "Ricoh RL5C465 PCI-CardBus Bridge",
251 PCIC_RF5C296, PCIC_CARDBUS_POWER, &pcic_pci_ricoh_chip },
252 { PCIC_ID_RICOH_RL5C475, "Ricoh RL5C475 PCI-CardBus Bridge",
253 PCIC_RF5C296, PCIC_CARDBUS_POWER, &pcic_pci_ricoh_chip },
254 { PCIC_ID_RICOH_RL5C476, "Ricoh RL5C476 PCI-CardBus Bridge",
255 PCIC_RF5C296, PCIC_CARDBUS_POWER, &pcic_pci_ricoh_chip },
256 { PCIC_ID_RICOH_RL5C477, "Ricoh RL5C477 PCI-CardBus Bridge",
257 PCIC_RF5C296, PCIC_CARDBUS_POWER, &pcic_pci_ricoh_chip },
258 { PCIC_ID_RICOH_RL5C478, "Ricoh RL5C478 PCI-CardBus Bridge",
259 PCIC_RF5C296, PCIC_CARDBUS_POWER, &pcic_pci_ricoh_chip },
260 { PCIC_ID_TI1031, "TI PCI-1031 PCI-PCMCIA Bridge",
261 PCIC_I82365SL_DF, PCIC_CARDBUS_POWER, &pcic_pci_ti113x_chip },
262 { PCIC_ID_TI1130, "TI PCI-1130 PCI-CardBus Bridge",
263 PCIC_I82365SL_DF, PCIC_CARDBUS_POWER, &pcic_pci_ti113x_chip },
264 { PCIC_ID_TI1131, "TI PCI-1131 PCI-CardBus Bridge",
265 PCIC_I82365SL_DF, PCIC_CARDBUS_POWER, &pcic_pci_ti113x_chip },
266 { PCIC_ID_TI1210, "TI PCI-1210 PCI-CardBus Bridge",
267 PCIC_I82365SL_DF, PCIC_CARDBUS_POWER, &pcic_pci_ti12xx_chip },
268 { PCIC_ID_TI1211, "TI PCI-1211 PCI-CardBus Bridge",
269 PCIC_I82365SL_DF, PCIC_CARDBUS_POWER, &pcic_pci_ti12xx_chip },
270 { PCIC_ID_TI1220, "TI PCI-1220 PCI-CardBus Bridge",
271 PCIC_I82365SL_DF, PCIC_CARDBUS_POWER, &pcic_pci_ti12xx_chip },
272 { PCIC_ID_TI1221, "TI PCI-1221 PCI-CardBus Bridge",
273 PCIC_I82365SL_DF, PCIC_CARDBUS_POWER, &pcic_pci_ti12xx_chip },
274 { PCIC_ID_TI1225, "TI PCI-1225 PCI-CardBus Bridge",
275 PCIC_I82365SL_DF, PCIC_CARDBUS_POWER, &pcic_pci_ti12xx_chip },
276 { PCIC_ID_TI1250, "TI PCI-1250 PCI-CardBus Bridge",
277 PCIC_I82365SL_DF, PCIC_CARDBUS_POWER | TI_NO_MFUNC,
278 &pcic_pci_ti12xx_chip },
279 { PCIC_ID_TI1251, "TI PCI-1251 PCI-CardBus Bridge",
280 PCIC_I82365SL_DF, PCIC_CARDBUS_POWER | TI_NO_MFUNC,
281 &pcic_pci_ti12xx_chip },
282 { PCIC_ID_TI1251B, "TI PCI-1251B PCI-CardBus Bridge",
283 PCIC_I82365SL_DF, PCIC_CARDBUS_POWER | TI_NO_MFUNC,
284 &pcic_pci_ti12xx_chip },
285 { PCIC_ID_TI1260, "TI PCI-1260 PCI-CardBus Bridge",
286 PCIC_I82365SL_DF, PCIC_CARDBUS_POWER, &pcic_pci_ti12xx_chip },
287 { PCIC_ID_TI1260B, "TI PCI-1260B PCI-CardBus Bridge",
288 PCIC_I82365SL_DF, PCIC_CARDBUS_POWER, &pcic_pci_ti12xx_chip },
289 { PCIC_ID_TI1410, "TI PCI-1410 PCI-CardBus Bridge",
290 PCIC_I82365SL_DF, PCIC_CARDBUS_POWER, &pcic_pci_ti12xx_chip },
291 { PCIC_ID_TI1420, "TI PCI-1420 PCI-CardBus Bridge",
292 PCIC_I82365SL_DF, PCIC_CARDBUS_POWER, &pcic_pci_ti12xx_chip },
293 { PCIC_ID_TI1421, "TI PCI-1421 PCI-CardBus Bridge",
294 PCIC_I82365SL_DF, PCIC_CARDBUS_POWER, &pcic_pci_ti12xx_chip },
295 { PCIC_ID_TI1450, "TI PCI-1450 PCI-CardBus Bridge",
296 PCIC_I82365SL_DF, PCIC_CARDBUS_POWER | TI_NO_MFUNC,
297 &pcic_pci_ti12xx_chip },
298 { PCIC_ID_TI1451, "TI PCI-1451 PCI-CardBus Bridge",
299 PCIC_I82365SL_DF, PCIC_CARDBUS_POWER, &pcic_pci_ti12xx_chip },
300 { PCIC_ID_TI1510, "TI PCI-1510 PCI-CardBus Bridge",
301 PCIC_I82365SL_DF, PCIC_CARDBUS_POWER, &pcic_pci_ti12xx_chip },
302 { PCIC_ID_TI1520, "TI PCI-1520 PCI-CardBus Bridge",
303 PCIC_I82365SL_DF, PCIC_CARDBUS_POWER, &pcic_pci_ti12xx_chip },
304 { PCIC_ID_TI4410, "TI PCI-4410 PCI-CardBus Bridge",
305 PCIC_I82365SL_DF, PCIC_CARDBUS_POWER, &pcic_pci_ti12xx_chip },
306 { PCIC_ID_TI4450, "TI PCI-4450 PCI-CardBus Bridge",
307 PCIC_I82365SL_DF, PCIC_CARDBUS_POWER, &pcic_pci_ti12xx_chip },
308 { PCIC_ID_TI4451, "TI PCI-4451 PCI-CardBus Bridge",
309 PCIC_I82365SL_DF, PCIC_CARDBUS_POWER, &pcic_pci_ti12xx_chip },
310 { PCIC_ID_TI4510, "TI PCI-4510 PCI-CardBus Bridge",
311 PCIC_I82365SL_DF, PCIC_CARDBUS_POWER, &pcic_pci_ti12xx_chip },
312 { PCIC_ID_TOPIC95, "Toshiba ToPIC95 PCI-CardBus Bridge",
313 PCIC_I82365, PCIC_CARDBUS_POWER, &pcic_pci_topic_chip },
314 { PCIC_ID_TOPIC95B, "Toshiba ToPIC95B PCI-CardBus Bridge",
315 PCIC_I82365, PCIC_CARDBUS_POWER, &pcic_pci_topic_chip },
316 { PCIC_ID_TOPIC97, "Toshiba ToPIC97 PCI-CardBus Bridge",
317 PCIC_I82365, PCIC_CARDBUS_POWER, &pcic_pci_topic_chip },
318 { PCIC_ID_TOPIC100, "Toshiba ToPIC100 PCI-CardBus Bridge",
319 PCIC_I82365, PCIC_CARDBUS_POWER, &pcic_pci_topic_chip },
320 { 0, NULL, 0, 0, NULL }
321 };
322
323 /*
324 * Read a register from the PCIC.
325 */
326 static unsigned char
327 pcic_pci_getb2(struct pcic_slot *sp, int reg)
328 {
329 return (bus_space_read_1(sp->bst, sp->bsh, sp->offset + reg));
330 }
331
332 /*
333 * Write a register on the PCIC
334 */
335 static void
336 pcic_pci_putb2(struct pcic_slot *sp, int reg, unsigned char val)
337 {
338 bus_space_write_1(sp->bst, sp->bsh, sp->offset + reg, val);
339 }
340
341 /*
342 * lookup inside the table
343 */
344 static struct pcic_pci_table *
345 pcic_pci_lookup(u_int32_t devid, struct pcic_pci_table *tbl)
346 {
347 while (tbl->devid) {
348 if (tbl->devid == devid)
349 return (tbl);
350 tbl++;
351 }
352 return (NULL);
353 }
354
355 /*
356 * The standard way to control fuction interrupts is via bit 7 in the BCR
357 * register. Some data sheets indicate that this is just for "intterupts"
358 * while others are clear that it is for function interrupts. When this
359 * bit is set, function interrupts are routed via the ExCA register. When
360 * this bit is clear, they are routed via the PCI bus, usually via the int
361 * in the INTPIN register.
362 */
363 static int
364 pcic_pci_gen_func(struct pcic_slot *sp, enum pcic_intr_way way)
365 {
366 u_int16_t bcr;
367
368 bcr = pci_read_config(sp->sc->dev, CB_PCI_BRIDGE_CTRL, 2);
369 if (way == pcic_iw_pci)
370 bcr &= ~CB_BCR_INT_EXCA;
371 else
372 bcr |= CB_BCR_INT_EXCA;
373 pci_write_config(sp->sc->dev, CB_PCI_BRIDGE_CTRL, bcr, 2);
374 return (0);
375 }
376
377 static int
378 pcic_pci_gen_csc(struct pcic_slot *sp, enum pcic_intr_way way)
379 {
380 return (0);
381 }
382
383 /*
384 * The O2micro OZ67xx chips functions.
385 */
386 static int
387 pcic_pci_oz67xx_func(struct pcic_slot *sp, enum pcic_intr_way way)
388 {
389 return (pcic_pci_gen_func(sp, way));
390 }
391
392 static int
393 pcic_pci_oz67xx_csc(struct pcic_slot *sp, enum pcic_intr_way way)
394 {
395 /*
396 * Need datasheet to find out what's going on. However, the
397 * 68xx datasheets are so vague that it is hard to know what
398 * the right thing to do is.
399 */
400 /* XXX */
401 return (0);
402 }
403
404
405 static void
406 pcic_pci_oz67xx_init(device_t dev)
407 {
408 device_printf(dev, "Warning: O2micro OZ67xx chips may not work\n");
409 pcic_pci_cardbus_init(dev);
410 }
411
412 /*
413 * The O2micro OZ68xx chips functions.
414 */
415 static int
416 pcic_pci_oz68xx_func(struct pcic_slot *sp, enum pcic_intr_way way)
417 {
418 return (pcic_pci_gen_func(sp, way));
419 }
420
421 static int
422 pcic_pci_oz68xx_csc(struct pcic_slot *sp, enum pcic_intr_way way)
423 {
424 /*
425 * The 68xx datasheets make it hard to know what the right thing
426 * to do here is. We do what we know, which is nothing, and
427 * hope for the best.
428 */
429 /* XXX */
430 return (0);
431 }
432
433 static void
434 pcic_pci_oz68xx_init(device_t dev)
435 {
436 /*
437 * This is almost certainly incomplete.
438 */
439 device_printf(dev, "Warning: O2micro OZ68xx chips may not work\n");
440 pcic_pci_cardbus_init(dev);
441 }
442
443 /*
444 * The Cirrus Logic PD6729/30. These are weird beasts, so be careful.
445 * They are ISA parts glued to the PCI bus and do not follow the yenta
446 * specification for cardbus bridges. They seem to be similar to the
447 * intel parts that were also cloned by o2micro and maybe others, but
448 * they are so much more common that the author doesn't have experience
449 * with them to know for sure.
450 */
451 static int
452 pcic_pci_pd67xx_func(struct pcic_slot *sp, enum pcic_intr_way way)
453 {
454 /*
455 * For pci interrupts, we need to set bit 3 of extension register
456 * 3 to 1. For ISA interrupts, we need to clear it.
457 */
458 sp->putb(sp, PCIC_EXT_IND, PCIC_EXTCTRL1);
459 if (way == pcic_iw_pci)
460 pcic_setb(sp, PCIC_EXTENDED, PCIC_EC1_CARD_IRQ_INV);
461 else
462 pcic_clrb(sp, PCIC_EXTENDED, PCIC_EC1_CARD_IRQ_INV);
463
464 return (0);
465 }
466
467 static int
468 pcic_pci_pd67xx_csc(struct pcic_slot *sp, enum pcic_intr_way way)
469 {
470 /*
471 * For pci interrupts, we need to set bit 4 of extension register
472 * 3 to 1. For ISA interrupts, we need to clear it.
473 */
474 sp->putb(sp, PCIC_EXT_IND, PCIC_EXTCTRL1);
475 if (way == pcic_iw_pci)
476 pcic_setb(sp, PCIC_EXTENDED, PCIC_EC1_CSC_IRQ_INV);
477 else
478 pcic_clrb(sp, PCIC_EXTENDED, PCIC_EC1_CSC_IRQ_INV);
479
480 return (0);
481 }
482
483
484 static void
485 pcic_pci_pd67xx_init(device_t dev)
486 {
487 struct pcic_softc *sc = device_get_softc(dev);
488
489 if (sc->csc_route == pcic_iw_pci || sc->func_route == pcic_iw_pci)
490 device_printf(dev, "PD67xx maybe broken for PCI routing.\n");
491 }
492
493 /*
494 * Set up the CL-PD6832, 6833 and 6834.
495 */
496 static int
497 pcic_pci_pd68xx_func(struct pcic_slot *sp, enum pcic_intr_way way)
498 {
499 return (pcic_pci_gen_func(sp, way));
500 }
501
502 static int
503 pcic_pci_pd68xx_csc(struct pcic_slot *sp, enum pcic_intr_way way)
504 {
505 struct pcic_softc *sc = sp->sc;
506 device_t dev = sc->dev;
507 u_int32_t device_id = pci_get_devid(dev);
508 u_long bcr;
509 u_long cm1;
510
511 /*
512 * CLPD6832 management interrupt enable bit is bit 11
513 * (MGMT_IRQ_ENA) in bridge control register(offset 0x3d).
514 * When on, card status interrupts are ISA controlled by
515 * the ExCA register 0x05.
516 *
517 * The CLPD6833 does things differently. It doesn't have bit
518 * 11 in the bridge control register. Instead, this
519 * functionality appears to be in the "Configuration
520 * Miscellaneous 1" register bit 1.
521 *
522 * I'm assuming that the CLPD6834 does things like the '33
523 */
524 if (device_id == PCIC_ID_CLPD6832) {
525 bcr = pci_read_config(dev, CB_PCI_BRIDGE_CTRL, 2);
526 if (way == pcic_iw_pci)
527 bcr &= ~CLPD6832_BCR_MGMT_IRQ_ENA;
528 else
529 bcr |= CLPD6832_BCR_MGMT_IRQ_ENA;
530 pci_write_config(dev, CB_PCI_BRIDGE_CTRL, bcr, 2);
531 }
532 if (device_id != PCIC_ID_CLPD6832) {
533 cm1 = pci_read_config(dev, CLPD6833_CFG_MISC_1, 4);
534 if (way == pcic_iw_pci)
535 cm1 &= ~CLPD6833_CM1_MGMT_EXCA_ENA;
536 else
537 cm1 |= CLPD6833_CM1_MGMT_EXCA_ENA;
538 pci_write_config(dev, CLPD6833_CFG_MISC_1, cm1, 4);
539 }
540 return (0);
541 }
542
543 static void
544 pcic_pci_pd68xx_init(device_t dev)
545 {
546 pcic_pci_cardbus_init(dev);
547 }
548
549 static int
550 pcic_pci_ricoh_func(struct pcic_slot *sp, enum pcic_intr_way way)
551 {
552 return (pcic_pci_gen_func(sp, way));
553 }
554
555 static int
556 pcic_pci_ricoh_csc(struct pcic_slot *sp, enum pcic_intr_way way)
557 {
558 struct pcic_softc *sc = sp->sc;
559 device_t dev = sc->dev;
560 u_int16_t mcr2;
561
562 /*
563 * For CSC interrupts via ISA, we can't do that exactly.
564 * However, we can disable INT# routing, which is usually what
565 * we want. This is bit 7 in the field. Note, bit 6 looks
566 * interesting, but appears to be unnecessary.
567 */
568 mcr2 = pci_read_config(dev, R5C47X_MISC_CONTROL_REGISTER_2, 2);
569 if (way == pcic_iw_pci)
570 mcr2 &= ~R5C47X_MCR2_CSC_TO_INTX_DISABLE;
571 else
572 mcr2 |= R5C47X_MCR2_CSC_TO_INTX_DISABLE;
573 pci_write_config(dev, R5C47X_MISC_CONTROL_REGISTER_2, mcr2, 2);
574
575 return (0);
576 }
577
578 static void
579 pcic_pci_ricoh_init(device_t dev)
580 {
581 u_int16_t brgcntl;
582 u_int32_t device_id = pci_get_devid(dev);
583
584 switch (device_id) {
585 case PCIC_ID_RICOH_RL5C465:
586 case PCIC_ID_RICOH_RL5C466:
587 /*
588 * Ricoh chips have a legacy bridge enable different than most
589 * Code cribbed from NEWBUS's bridge code since I can't find a
590 * datasheet for them that has register definitions.
591 */
592 brgcntl = pci_read_config(dev, CB_PCI_BRIDGE_CTRL, 2);
593 brgcntl &= ~(CB_BCR_RL_3E2_EN | CB_BCR_RL_3E0_EN);
594 pci_write_config(dev, CB_PCI_BRIDGE_CTRL, brgcntl, 2);
595 break;
596 }
597 pcic_pci_cardbus_init(dev);
598 }
599
600 /*
601 * TI 1030, 1130, and 1131.
602 */
603 static int
604 pcic_pci_ti113x_func(struct pcic_slot *sp, enum pcic_intr_way way)
605 {
606 u_int32_t cardcntl;
607 device_t dev = sp->sc->dev;
608
609 /*
610 * The TI-1130 (and 1030 and 1131) have a different interrupt
611 * routing control than the newer cards. assume we're not
612 * routing PCI, but enable as necessary when we find someone
613 * uses PCI interrupts. In order to get any pci interrupts,
614 * PCI_IRQ_ENA (bit 5) must be set. If either PCI_IREQ (bit
615 * 4) or PCI_CSC (bit 3) are set, then set bit 5 at the same
616 * time, since setting them enables the PCI interrupt routing.
617 *
618 * It also appears necessary to set the function routing bit
619 * in the bridge control register, but cardbus_init does that
620 * for us.
621 */
622 cardcntl = pci_read_config(dev, TI113X_PCI_CARD_CONTROL, 1);
623 if (way == pcic_iw_pci)
624 cardcntl |= TI113X_CARDCNTL_PCI_IREQ;
625 else
626 cardcntl &= ~TI113X_CARDCNTL_PCI_IREQ;
627 if (cardcntl & (TI113X_CARDCNTL_PCI_IREQ | TI113X_CARDCNTL_PCI_CSC))
628 cardcntl |= TI113X_CARDCNTL_PCI_IRQ_ENA;
629 else
630 cardcntl &= ~TI113X_CARDCNTL_PCI_IRQ_ENA;
631 pci_write_config(dev, TI113X_PCI_CARD_CONTROL, cardcntl, 1);
632
633 return (pcic_pci_gen_func(sp, way));
634 }
635
636 static int
637 pcic_pci_ti113x_csc(struct pcic_slot *sp, enum pcic_intr_way way)
638 {
639 u_int32_t cardcntl;
640 device_t dev = sp->sc->dev;
641
642 /*
643 * The TI-1130 (and 1030 and 1131) have a different interrupt
644 * routing control than the newer cards. assume we're not
645 * routing PCI, but enable as necessary when we find someone
646 * uses PCI interrupts. In order to get any pci interrupts,
647 * PCI_IRQ_ENA (bit 5) must be set. If either PCI_IREQ (bit
648 * 4) or PCI_CSC (bit 3) are set, then set bit 5 at the same
649 * time, since setting them enables the PCI interrupt routing.
650 *
651 * It also appears necessary to set the function routing bit
652 * in the bridge control register, but cardbus_init does that
653 * for us.
654 */
655 cardcntl = pci_read_config(dev, TI113X_PCI_CARD_CONTROL, 1);
656 if (way == pcic_iw_pci)
657 cardcntl |= TI113X_CARDCNTL_PCI_CSC;
658 else
659 cardcntl &= ~TI113X_CARDCNTL_PCI_CSC;
660 if (cardcntl & (TI113X_CARDCNTL_PCI_IREQ | TI113X_CARDCNTL_PCI_CSC))
661 cardcntl |= TI113X_CARDCNTL_PCI_IRQ_ENA;
662 else
663 cardcntl &= ~TI113X_CARDCNTL_PCI_IRQ_ENA;
664 pci_write_config(dev, TI113X_PCI_CARD_CONTROL, cardcntl, 1);
665
666 return (0);
667 }
668
669 static int
670 pcic_pci_ti12xx_func(struct pcic_slot *sp, enum pcic_intr_way way)
671 {
672 u_int32_t syscntl, devcntl, cardcntl, mfunc;
673 device_t dev = sp->sc->dev;
674
675 syscntl = pci_read_config(dev, TI113X_PCI_SYSTEM_CONTROL, 4);
676 devcntl = pci_read_config(dev, TI113X_PCI_DEVICE_CONTROL, 1);
677 cardcntl = pci_read_config(dev, TI113X_PCI_CARD_CONTROL, 1);
678
679 /*
680 * Special code for the Orinoco cards (and a few others). They
681 * seem to need this special code to make them work only over pci
682 * interrupts. Sadly, doing this code also causes problems for
683 * many laptops, so we have to make it controlled by a tunable.
684 * Actually, experience has shown that this rarely, if ever,
685 * helps.
686 */
687 if (way == pcic_iw_pci) {
688 /*
689 * pcic_init_routing seems to do nothing useful towards
690 * fixing the hang problems. I plan on removing it in
691 * 4.8 or so.
692 */
693 if (pcic_init_routing) {
694 devcntl &= ~TI113X_DEVCNTL_INTR_MASK;
695 pci_write_config(dev, TI113X_PCI_DEVICE_CONTROL,
696 devcntl, 1);
697 syscntl |= TI113X_SYSCNTL_INTRTIE;
698 }
699 #if 0
700 /*
701 * I've had reports that we need the pci clock enabled,
702 * but I'm unsure how wise this is in general, so it
703 * is ifdef'd out at the moment
704 */
705 syscntl |= TI12XX_SYSCNTL_PCI_CLOCK;
706 pci_write_config(dev, TI113X_PCI_SYSTEM_CONTROL, syscntl, 4);
707
708 #endif
709 /*
710 * Some PCI add-in cards don't have good EEPROMs on them,
711 * so they get this MUX register wrong. The MUX register
712 * defaults to 0, which is usually wrong for this register,
713 * so we initialize it to make sense.
714 *
715 * We don't bother to turn it off in the ISA case since it
716 * is an initialization issue.
717 *
718 * A few weird TI bridges don't have MFUNC, so filter
719 * those out too.
720 */
721 if ((sp->sc->flags & TI_NO_MFUNC) == 0) {
722 mfunc = pci_read_config(dev, TI12XX_PCI_MFUNC, 4);
723 if (mfunc == 0) {
724 mfunc = (mfunc & ~TI12XX_MFUNC_PIN0) |
725 TI12XX_MFUNC_PIN0_INTA;
726 if ((syscntl & TI113X_SYSCNTL_INTRTIE) == 0)
727 mfunc = (mfunc & ~TI12XX_MFUNC_PIN1) |
728 TI12XX_MFUNC_PIN1_INTB;
729 pci_write_config(dev, TI12XX_PCI_MFUNC, mfunc,
730 4);
731 }
732 }
733
734 }
735 return (pcic_pci_gen_func(sp, way));
736 }
737
738 static int
739 pcic_pci_ti12xx_csc(struct pcic_slot *sp, enum pcic_intr_way way)
740 {
741 /*
742 * Nothing happens here. The TI12xx parts will route the
743 * CSC interrupt via PCI if ExCA register tells it to use
744 * interrupt 0. And via IRQ otherwise (except for reserved
745 * values which may or may not do anything).
746 *
747 * We just hope for the best here that doing nothing is the
748 * right thing to do.
749 */
750 return (0);
751 }
752
753 /*
754 * TI PCI-CardBus Host Adapter specific function code.
755 * This function is separated from pcic_pci_attach().
756 * Takeshi Shibagaki(shiba@jp.freebsd.org).
757 */
758 static void
759 pcic_pci_ti_init(device_t dev)
760 {
761 u_int32_t syscntl, diagctl, devcntl, cardcntl;
762 u_int32_t device_id = pci_get_devid(dev);
763 int ti113x = (device_id == PCIC_ID_TI1031) ||
764 (device_id == PCIC_ID_TI1130) ||
765 (device_id == PCIC_ID_TI1131);
766
767 syscntl = pci_read_config(dev, TI113X_PCI_SYSTEM_CONTROL, 4);
768 devcntl = pci_read_config(dev, TI113X_PCI_DEVICE_CONTROL, 1);
769 cardcntl = pci_read_config(dev, TI113X_PCI_CARD_CONTROL, 1);
770
771 if (ti113x) {
772 device_printf(dev, "TI113X PCI Config Reg: ");
773 if (syscntl & TI113X_SYSCNTL_CLKRUN_ENA) {
774 if (syscntl & TI113X_SYSCNTL_CLKRUN_SEL)
775 printf("[clkrun irq 12]");
776 else
777 printf("[clkrun irq 10]");
778 }
779 } else {
780 device_printf(dev, "TI12XX PCI Config Reg: ");
781
782 /*
783 * Turn on async CSC interrupts. This appears to
784 * be the default, but the old, pre pci-aware, code
785 * did this and it appears PAO does as well.
786 */
787 diagctl = pci_read_config(dev, TI12XX_PCI_DIAGNOSTIC, 1);
788 diagctl |= TI12XX_DIAG_CSC_INTR;
789 pci_write_config(dev, TI12XX_PCI_DIAGNOSTIC, diagctl, 1);
790
791 /*
792 * Turn off Zoom Video. Some cards have this enabled,
793 * some do not but it causes problems when enabled. This
794 * register doesn't exist on the 1130 (and likely the 1131,
795 * but without a datasheet it is impossible to know).
796 * Some 12xx chips may not have it, but setting it is
797 * believed to be harmless on those models.
798 */
799 pci_write_config(dev, TI12XX_PCI_MULTIMEDIA_CONTROL, 0, 4);
800 }
801 if (cardcntl & TI113X_CARDCNTL_RING_ENA)
802 printf("[ring enable]");
803 if (cardcntl & TI113X_CARDCNTL_SPKR_ENA)
804 printf("[speaker enable]");
805 if (syscntl & TI113X_SYSCNTL_PWRSAVINGS)
806 printf("[pwr save]");
807 switch(devcntl & TI113X_DEVCNTL_INTR_MASK){
808 case TI113X_DEVCNTL_INTR_ISA :
809 printf("[CSC parallel isa irq]");
810 break;
811 case TI113X_DEVCNTL_INTR_SERIAL :
812 printf("[CSC serial isa irq]");
813 break;
814 case TI113X_DEVCNTL_INTR_NONE :
815 printf("[pci only]");
816 break;
817 case TI12XX_DEVCNTL_INTR_ALLSERIAL :
818 printf("[FUNC pci int + CSC serial isa irq]");
819 break;
820 }
821 printf("\n");
822 pcic_pci_cardbus_init(dev);
823 }
824
825 /*
826 * Code for TOPIC chips
827 */
828 static int
829 pcic_pci_topic_func(struct pcic_slot *sp, enum pcic_intr_way way)
830 {
831 #ifdef THIS_BRAEKS_THINGS
832 device_t dev = sp->sc->dev;
833 u_int32_t scr;
834
835 scr = pci_read_config(dev, TOPIC_SOCKET_CTRL, 4);
836 if (way == pcic_iw_pci)
837 scr |= TOPIC_SOCKET_CTRL_SCR_IRQSEL;
838 else
839 scr &= ~TOPIC_SOCKET_CTRL_SCR_IRQSEL;
840 pci_write_config(dev, TOPIC_SLOT_CTRL, scr, 4);
841 #endif
842 return (pcic_pci_gen_func(sp, way));
843 }
844
845 static int
846 pcic_pci_topic_csc(struct pcic_slot *sp, enum pcic_intr_way way)
847 {
848 device_t dev = sp->sc->dev;
849 u_int32_t scr;
850 u_int32_t device_id;
851
852 device_id = pci_get_devid(dev);
853 if (device_id == PCIC_ID_TOPIC100 || device_id == PCIC_ID_TOPIC97) {
854 scr = pci_read_config(dev, TOPIC_SLOT_CTRL, 4);
855 if (way == pcic_iw_pci)
856 scr |= TOPIC97_SLOT_CTRL_PCIINT;
857 else
858 scr &= ~TOPIC97_SLOT_CTRL_PCIINT;
859 pci_write_config(dev, TOPIC_SLOT_CTRL, scr, 4);
860 }
861
862 return (0);
863 }
864
865 static void
866 pcic_pci_topic_init(device_t dev)
867 {
868 struct pcic_softc *sc = device_get_softc(dev);
869 u_int32_t reg;
870 u_int32_t device_id;
871
872 device_id = pci_get_devid(dev);
873 reg = pci_read_config(dev, TOPIC_SLOT_CTRL, 4);
874 reg |= (TOPIC_SLOT_CTRL_SLOTON | TOPIC_SLOT_CTRL_SLOTEN |
875 TOPIC_SLOT_CTRL_ID_LOCK | TOPIC_SLOT_CTRL_CARDBUS);
876 reg &= ~TOPIC_SLOT_CTRL_SWDETECT;
877 if (device_id == PCIC_ID_TOPIC100 || device_id == PCIC_ID_TOPIC97) {
878 reg |= TOPIC97_SLOT_CTRL_PCIINT;
879 reg &= ~(TOPIC97_SLOT_CTRL_STSIRQP | TOPIC97_SLOT_CTRL_IRQP);
880 }
881 pci_write_config(dev, TOPIC_SLOT_CTRL, reg, 4);
882 pcic_pci_cardbus_init(dev);
883
884 if (device_id == PCIC_ID_TOPIC100 || device_id == PCIC_ID_TOPIC97) {
885 /*
886 * We need to enable voltage sense and 3V cards explicitly
887 * in the bridge. The datasheets I have for both the
888 * ToPIC 97 and 100 both lists these ports. Without
889 * datasheets for the ToPIC95s, I can't tell if we need
890 * to do it there or not.
891 */
892 pcic_setb(&sc->slots[0], PCIC_TOPIC_FCR,
893 PCIC_FCR_3V_EN | PCIC_FCR_VS_EN);
894 }
895 }
896
897 static void
898 pcic_pci_cardbus_init(device_t dev)
899 {
900 struct pcic_softc *sc = device_get_softc(dev);
901 u_int16_t brgcntl;
902 int unit;
903
904 unit = device_get_unit(dev);
905
906 brgcntl = pci_read_config(dev, CB_PCI_BRIDGE_CTRL, 2);
907 brgcntl |= CB_BCR_WRITE_POST_EN | CB_BCR_MASTER_ABORT;
908 pci_write_config(dev, CB_PCI_BRIDGE_CTRL, brgcntl, 2);
909
910 /* Turn off legacy address */
911 pci_write_config(dev, CB_PCI_LEGACY16_IOADDR, 0, 2);
912
913 /*
914 * Write zeros into the remaining memory I/O windows. This
915 * seems to turn off the pci configuration of these things and
916 * make the cardbus bridge use the values for memory
917 * programmed into the pcic registers.
918 */
919 pci_write_config(dev, CB_PCI_MEMBASE0, 0, 4);
920 pci_write_config(dev, CB_PCI_MEMLIMIT0, 0, 4);
921 pci_write_config(dev, CB_PCI_MEMBASE1, 0, 4);
922 pci_write_config(dev, CB_PCI_MEMLIMIT1, 0, 4);
923 pci_write_config(dev, CB_PCI_IOBASE0, 0, 4);
924 pci_write_config(dev, CB_PCI_IOLIMIT0, 0, 4);
925 pci_write_config(dev, CB_PCI_IOBASE1, 0, 4);
926 pci_write_config(dev, CB_PCI_IOLIMIT1, 0, 4);
927
928 /*
929 * Tell the chip to do its routing thing.
930 */
931 sc->chip->func_intr_way(&sc->slots[0], sc->func_route);
932 sc->chip->csc_intr_way(&sc->slots[0], sc->csc_route);
933
934 return;
935 }
936
937 static const char *
938 pcic_pci_cardtype(u_int32_t stat)
939 {
940 if (stat & CB_SS_NOTCARD)
941 return ("unrecognized by bridge");
942 if ((stat & (CB_SS_16BIT | CB_SS_CB)) == (CB_SS_16BIT | CB_SS_CB))
943 return ("16-bit and 32-bit (can't happen)");
944 if (stat & CB_SS_16BIT)
945 return ("16-bit pccard");
946 if (stat & CB_SS_CB)
947 return ("32-bit cardbus");
948 return ("none (can't happen)");
949 }
950
951 /*
952 * Card insertion and removal code. The insertion events need to be
953 * debounced so that the noisy insertion/removal events don't result
954 * in the hardware being initialized many times, only to be torn down
955 * as well. This may also cause races with pccardd. Instead, we wait
956 * for the insertion signal to be stable for 0.5 seconds before we declare
957 * it to be a real insertion event. Removal is also debounced. We turn
958 * off interrupt servicing during the settling time to prevent infinite
959 * loops in the driver.
960 *
961 * Note: We only handle the card detect change events. We don't handle
962 * power events and status change events.
963 */
964 static void
965 pcic_cd_change(void *arg)
966 {
967 struct pcic_softc *sc = (struct pcic_softc *) arg;
968 struct pcic_slot *sp = &sc->slots[0];
969 u_int32_t stat;
970
971 sc->cd_pending = 0;
972 stat = bus_space_read_4(sp->bst, sp->bsh, CB_SOCKET_STATE);
973
974 /* Status changed while present; remove the card from the system. */
975 if (sc->cd_present) {
976 sc->cd_present = 0;
977 pccard_event(sp->slt, card_removed);
978 }
979 /* Nothing to do if the debounced state is 'not present'. */
980 if ((stat & CB_SS_CD) != 0)
981 return;
982
983 sc->cd_present = 1;
984 if (bootverbose && (stat & CB_SS_BADVCC) != 0)
985 device_printf(sc->dev, "BAD Vcc request: 0x%x\n", stat);
986 if ((stat & CB_SS_16BIT) == 0)
987 device_printf(sp->sc->dev, "Card type %s is unsupported\n",
988 pcic_pci_cardtype(stat));
989 else
990 pccard_event(sp->slt, card_inserted);
991 }
992
993 static void
994 pcic_pci_intr(void *arg)
995 {
996 struct pcic_softc *sc = (struct pcic_softc *) arg;
997 struct pcic_slot *sp = &sc->slots[0];
998 u_int32_t event;
999
1000 event = bus_space_read_4(sp->bst, sp->bsh, CB_SOCKET_EVENT);
1001 if (event != 0) {
1002 if (bootverbose)
1003 device_printf(sc->dev, "Event mask 0x%x\n", event);
1004
1005 /*
1006 * Treat all card-detect signal transitions the same way
1007 * since we can't reliably tell if this is an insert or a
1008 * remove event. Stop the card from getting interrupts and
1009 * defer the insert/remove event until the CB_SOCKET_STATE
1010 * signals have had time to settle.
1011 */
1012 if ((event & CB_SE_CD) != 0) {
1013 if (sc->cd_pending) {
1014 untimeout(pcic_cd_change, arg, sc->cd_ch);
1015 sc->cd_pending = 0;
1016 }
1017 sc->cd_pending = 1;
1018 sc->cd_ch = timeout(pcic_cd_change, arg, hz/2);
1019 sc->func_intr = NULL;
1020 }
1021
1022 /* Ack the interrupt */
1023 bus_space_write_4(sp->bst, sp->bsh, 0, event);
1024 }
1025
1026 /*
1027 * Some TI chips also require us to read the old ExCA register for
1028 * card status change when we route CSC via PCI! So, we go ahead
1029 * and read it to clear the bits. Maybe we should check the status
1030 * ala the ISA interrupt handler, but those changes should be caught
1031 * in the CD change.
1032 *
1033 * We have to check it every interrupt because these bits can sometimes
1034 * show up indepentently of the CB_SOCKET_EVENT register above.
1035 */
1036 sp->getb(sp, PCIC_STAT_CHG);
1037 }
1038
1039 /*
1040 * Return the ID string for the controller if the vendor/product id
1041 * matches, NULL otherwise.
1042 */
1043 static int
1044 pcic_pci_probe(device_t dev)
1045 {
1046 u_int8_t subclass;
1047 u_int8_t progif;
1048 const char *desc;
1049 u_int32_t device_id;
1050 struct pcic_pci_table *itm;
1051 struct resource *res;
1052 int rid;
1053
1054 if (pcic_ignore_pci)
1055 return (ENXIO);
1056 device_id = pci_get_devid(dev);
1057 desc = NULL;
1058 itm = pcic_pci_lookup(device_id, &pcic_pci_devs[0]);
1059 if (pcic_ignore_function_1 && pci_get_function(dev) == 1) {
1060 if (itm != NULL)
1061 PRVERB((dev, "Ignoring function 1\n"));
1062 return (ENXIO);
1063 }
1064 if (itm != NULL)
1065 desc = itm->descr;
1066 if (desc == NULL && pci_get_class(dev) == PCIC_BRIDGE) {
1067 subclass = pci_get_subclass(dev);
1068 progif = pci_get_progif(dev);
1069 if (subclass == PCIS_BRIDGE_PCMCIA && progif == 0)
1070 desc = "Generic PCI-PCMCIA Bridge";
1071 if (subclass == PCIS_BRIDGE_CARDBUS && progif == 0)
1072 desc = "YENTA PCI-CardBus Bridge";
1073 if (bootverbose && desc)
1074 printf("Found unknown %s devid 0x%x\n", desc, device_id);
1075 }
1076 if (desc == NULL)
1077 return (ENXIO);
1078 device_set_desc(dev, desc);
1079
1080 /*
1081 * Take us out of power down mode, if necessary. It also
1082 * appears that even reading the power register is enough on
1083 * some systems to cause correct behavior.
1084 */
1085 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
1086 /* Reset the power state. */
1087 device_printf(dev, "chip is in D%d power mode "
1088 "-- setting to D0\n", pci_get_powerstate(dev));
1089 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
1090 }
1091
1092 /*
1093 * Allocated/deallocate interrupt. This forces the PCI BIOS or
1094 * other MD method to route the interrupts to this card.
1095 * This so we get the interrupt number in the probe message.
1096 * We only need to route interrupts when we're doing pci
1097 * parallel interrupt routing.
1098 *
1099 * We use two different variables for the memory based and I/O
1100 * based cards, so the check here is a little more complex than
1101 * one would otherwise hope.
1102 *
1103 * XXX The bus code for PCI really should do this for us.
1104 */
1105 if ((pcic_intr_path == pcic_iw_pci &&
1106 device_id != PCIC_ID_CLPD6729) ||
1107 (pcic_pd6729_intr_path == pcic_iw_pci &&
1108 device_id == PCIC_ID_CLPD6729)) {
1109 rid = 0;
1110 #ifdef __i386__
1111 /*
1112 * IRQ 0 is invalid on x86, but not other platforms.
1113 * If we have irq 0, then write 255 to force a new, non-
1114 * bogus one to be assigned. I think that in -current
1115 * the code in this ifdef may be obsolete with the new
1116 * invalid mapping that we're doing in the pci layer -- imp
1117 */
1118 if (pci_get_irq(dev) == 0) {
1119 pci_set_irq(dev, 255);
1120 pci_write_config(dev, PCIR_INTLINE, 255, 1);
1121 }
1122 #endif
1123 res = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1,
1124 RF_ACTIVE);
1125 if (res)
1126 bus_release_resource(dev, SYS_RES_IRQ, rid, res);
1127 }
1128
1129 return (0);
1130 }
1131
1132 static void
1133 pcic_pci_shutdown(device_t dev)
1134 {
1135 /*
1136 * More reports of things working w/o this code than with it.
1137 */
1138 #if 0
1139 struct pcic_softc *sc;
1140 struct pcic_slot *sp;
1141
1142 sc = (struct pcic_softc *) device_get_softc(dev);
1143 sp = &sc->slots[0];
1144
1145 /*
1146 * Turn off the power to the slot in an attempt to
1147 * keep the system from hanging on reboot. We also turn off
1148 * card interrupts in an attempt to control interrupt storms.
1149 * on some (all?) this has the effect of also turning off
1150 * card status change interrupts. A side effect of writing 0
1151 * to INT_GEN is that the card is placed into "reset" mode
1152 * where nothing happens until it is taken out of "reset"
1153 * mode.
1154 *
1155 * Also, turn off the generation of status interrupts too.
1156 */
1157 sp->putb(sp, PCIC_INT_GEN, 0);
1158 sp->putb(sp, PCIC_STAT_INT, 0);
1159 sp->putb(sp, PCIC_POWER, 0);
1160 DELAY(4000);
1161
1162 /*
1163 * Writing to INT_GEN can cause an interrupt, so we blindly
1164 * ack all possible interrupts here. Reading the stat change
1165 * shouldn't be necessary, but some TI chipsets need it in the
1166 * normal course of operations, so we do it here too. We can't
1167 * lose any interrupts after this point, so go ahead and ack
1168 * everything. The bits in INT_GEN clear upon reading them.
1169 * We also set the interrupt mask to 0, in an effort to avoid
1170 * getting further interrupts.
1171 */
1172 bus_space_write_4(sp->bst, sp->bsh, CB_SOCKET_MASK, 0);
1173 bus_space_write_4(sp->bst, sp->bsh, CB_SOCKET_EVENT, 0xffffffff);
1174 sp->getb(sp, PCIC_STAT_CHG);
1175 #endif
1176 }
1177
1178 /*
1179 * Print out the config space
1180 */
1181 static void
1182 pcic_pci_print_config(device_t dev)
1183 {
1184 int i;
1185
1186 device_printf(dev, "PCI Configuration space:");
1187 for (i = 0; i < 256; i += 4) {
1188 if (i % 16 == 0)
1189 printf("\n 0x%02x: ", i);
1190 printf("0x%08x ", pci_read_config(dev, i, 4));
1191 }
1192 printf("\n");
1193 }
1194
1195 /*
1196 * Generic pci interrupt attach routine. It tries to understand all parts,
1197 * and do sane things for those parts it does not understand.
1198 */
1199 static int
1200 pcic_pci_attach(device_t dev)
1201 {
1202 u_int32_t device_id = pci_get_devid(dev);
1203 u_long command;
1204 struct pcic_slot *sp;
1205 struct pcic_softc *sc;
1206 u_int32_t sockbase;
1207 u_int32_t stat;
1208 struct pcic_pci_table *itm;
1209 int rid;
1210 int i;
1211 struct resource *r = NULL;
1212 int error;
1213 u_long irq = 0;
1214 driver_intr_t *intr = NULL;
1215
1216 /*
1217 * In sys/pci/pcireg.h, PCIR_COMMAND must be separated
1218 * PCI_COMMAND_REG(0x04) and PCI_STATUS_REG(0x06).
1219 * Takeshi Shibagaki(shiba@jp.freebsd.org).
1220 */
1221 command = pci_read_config(dev, PCIR_COMMAND, 4);
1222 command |= PCIM_CMD_PORTEN | PCIM_CMD_MEMEN;
1223 pci_write_config(dev, PCIR_COMMAND, command, 4);
1224
1225 sc = (struct pcic_softc *) device_get_softc(dev);
1226 sp = &sc->slots[0];
1227 sp->sc = sc;
1228 sockbase = pci_read_config(dev, 0x10, 4);
1229 if (sockbase & 0x1) {
1230 sc->iorid = CB_PCI_SOCKET_BASE;
1231 sc->iores = bus_alloc_resource(dev, SYS_RES_IOPORT,
1232 &sc->iorid, 0, ~0, 1, RF_ACTIVE | RF_SHAREABLE);
1233 if (sc->iores == NULL)
1234 return (ENOMEM);
1235
1236 sc->flags = PCIC_PD_POWER;
1237 itm = pcic_pci_lookup(device_id, &pcic_pci_devs[0]);
1238 for (i = 0; i < 2; i++) {
1239 sp[i].bst = rman_get_bustag(sc->iores);
1240 sp[i].bsh = rman_get_bushandle(sc->iores);
1241 sp[i].sc = sc;
1242 sp[i].revision = 0;
1243 sp[i].getb = pcic_getb_io;
1244 sp[i].putb = pcic_putb_io;
1245 sp[i].offset = i * PCIC_SLOT_SIZE;
1246 sp[i].controller = itm ? itm->type : PCIC_PD6729;
1247 if ((sp[i].getb(&sp[i], PCIC_ID_REV) & 0xc0) == 0x80)
1248 sp[i].slt = (struct slot *) 1;
1249 }
1250 sc->csc_route = sc->func_route = pcic_pd6729_intr_path;
1251 if (itm)
1252 sc->flags = itm->flags;
1253 /*
1254 * We have to use the ISA interrupt routine for status
1255 * changes since we don't have any "yenta" pci registers.
1256 * We have to do this even when we're using pci type
1257 * interrupts because on these cards the interrupts are
1258 * cleared in the same way that the ISA cards clear them.
1259 */
1260 intr = pcic_isa_intr;
1261 } else {
1262 sc->memrid = CB_PCI_SOCKET_BASE;
1263 sc->memres = bus_alloc_resource(dev, SYS_RES_MEMORY,
1264 &sc->memrid, 0, ~0, 1, RF_ACTIVE);
1265 if (sc->memres == NULL && pcic_pci_get_memory(dev) != 0)
1266 return (ENOMEM);
1267 sp->getb = pcic_pci_getb2;
1268 sp->putb = pcic_pci_putb2;
1269 sp->offset = CB_EXCA_OFFSET;
1270 sp->bst = rman_get_bustag(sc->memres);
1271 sp->bsh = rman_get_bushandle(sc->memres);
1272 itm = pcic_pci_lookup(device_id, &pcic_pci_devs[0]);
1273 if (itm != NULL) {
1274 sp->controller = itm->type;
1275 sp->revision = 0;
1276 sc->flags = itm->flags;
1277 } else {
1278 /* By default, assume we're a D step compatible */
1279 sp->controller = PCIC_I82365SL_DF;
1280 sp->revision = 0;
1281 sc->flags = PCIC_CARDBUS_POWER;
1282 }
1283 /* All memory mapped cardbus bridges have these registers */
1284 sc->flags |= PCIC_YENTA_HIGH_MEMORY;
1285 sp->slt = (struct slot *) 1;
1286 sc->csc_route = pcic_intr_path;
1287 sc->func_route = pcic_intr_path;
1288 stat = bus_space_read_4(sp->bst, sp->bsh, CB_SOCKET_STATE);
1289 sc->cd_present = (stat & CB_SS_CD) == 0;
1290 }
1291 sc->dev = dev;
1292 if (itm)
1293 sc->chip = itm->chip;
1294 else
1295 sc->chip = &pcic_pci_generic_chip;
1296
1297 if (sc->csc_route == pcic_iw_pci) {
1298 rid = 0;
1299 r = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1,
1300 RF_ACTIVE | RF_SHAREABLE);
1301 if (r == NULL) {
1302 sc->csc_route = pcic_iw_isa;
1303 sc->func_route = pcic_iw_isa;
1304 device_printf(dev,
1305 "No PCI interrupt routed, trying ISA.\n");
1306 } else {
1307 if (intr == NULL)
1308 intr = pcic_pci_intr;
1309 irq = rman_get_start(r);
1310 }
1311 }
1312 if (sc->csc_route == pcic_iw_isa) {
1313 rid = 0;
1314 irq = pcic_override_irq;
1315 if (irq != 0) {
1316 r = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, irq,
1317 irq, 1, RF_ACTIVE);
1318 if (r == NULL) {
1319 device_printf(dev,
1320 "Can't route ISA CSC interrupt.\n");
1321 pcic_dealloc(dev);
1322 return (ENXIO);
1323 }
1324 device_printf(dev,
1325 "Management interrupt on ISA IRQ %ld\n", irq);
1326 if (intr == NULL)
1327 intr = pcic_isa_intr;
1328 } else {
1329 sc->slot_poll = pcic_timeout;
1330 sc->timeout_ch = timeout(sc->slot_poll, sc, hz/2);
1331 device_printf(dev, "Polling mode\n");
1332 intr = NULL;
1333 }
1334 }
1335
1336 /*
1337 * Initialize AFTER we figure out what kind of interrupt we're
1338 * going to be using, if any.
1339 */
1340 if (!sc->chip)
1341 panic("Bug: sc->chip not set!\n");
1342 sc->chip->init(dev);
1343
1344 /*
1345 * Now install the interrupt handler, if necessary.
1346 */
1347 sc->irqrid = rid;
1348 sc->irqres = r;
1349 sc->irq = irq;
1350 if (intr) {
1351 error = bus_setup_intr(dev, r, INTR_TYPE_AV, intr, sc, &sc->ih);
1352 if (error) {
1353 pcic_dealloc(dev);
1354 return (error);
1355 }
1356 }
1357 if (bootverbose)
1358 pcic_pci_print_config(dev);
1359 return (pcic_attach(dev));
1360 }
1361
1362 static int
1363 pcic_pci_detach(device_t dev)
1364 {
1365 return (EBUSY); /* Can't detach this device */
1366 }
1367
1368 /*
1369 * The PCI bus should do this for us. However, it doesn't quite yet, so
1370 * we cope by doing it ourselves. If it ever does, this code can go quietly
1371 * into that good night.
1372 */
1373 static int
1374 pcic_pci_get_memory(device_t dev)
1375 {
1376 struct pcic_softc *sc;
1377 u_int32_t sockbase;
1378
1379 sc = (struct pcic_softc *) device_get_softc(dev);
1380 sockbase = pci_read_config(dev, sc->memrid, 4);
1381 if (sockbase >= 0x100000 && sockbase < 0xfffffff0) {
1382 device_printf(dev, "Could not map register memory\n");
1383 return (ENOMEM);
1384 }
1385 pci_write_config(dev, sc->memrid, 0xffffffff, 4);
1386 sockbase = pci_read_config(dev, sc->memrid, 4);
1387 sockbase = (sockbase & 0xfffffff0) & -(sockbase & 0xfffffff0);
1388 #define CARDBUS_SYS_RES_MEMORY_START 0x88000000
1389 #define CARDBUS_SYS_RES_MEMORY_END 0xFFFFFFFF
1390 sc->memres = bus_generic_alloc_resource(device_get_parent(dev),
1391 dev, SYS_RES_MEMORY, &sc->memrid,
1392 CARDBUS_SYS_RES_MEMORY_START, CARDBUS_SYS_RES_MEMORY_END,
1393 sockbase, RF_ACTIVE | rman_make_alignment_flags(sockbase));
1394 if (sc->memres == NULL) {
1395 device_printf(dev, "Could not grab register memory\n");
1396 return (ENOMEM);
1397 }
1398 sockbase = rman_get_start(sc->memres);
1399 pci_write_config(dev, sc->memrid, sockbase, 4);
1400 device_printf(dev, "PCI Memory allocated: 0x%08x\n", sockbase);
1401 return (0);
1402 }
1403
1404 static int
1405 pcic_pci_gen_mapirq(struct pcic_slot *sp, int irq)
1406 {
1407 /*
1408 * If we're doing ISA interrupt routing, then just go to the
1409 * generic ISA routine. Also, irq 0 means turn off the interrupts
1410 * at the bridge.
1411 */
1412 if (sp->sc->func_route == pcic_iw_isa || irq == 0)
1413 return (pcic_isa_mapirq(sp, irq));
1414
1415 /*
1416 * Ohterwise we're doing PCI interrupts. For those cardbus bridges
1417 * that follow yenta (and the one pcmcia bridge that does), we don't
1418 * do a thing to get the IRQ mapped into the system. However,
1419 * for other controllers that are PCI, but not yetna compliant, we
1420 * need to do some special mapping.
1421 *
1422 * XXX Maybe we shouldn't assume INTA#, but rather as the function
1423 * XXX what Intline to use.
1424 */
1425 if (sp->controller == PCIC_PD6729) {
1426 /*
1427 * INTA - 3
1428 * INTB - 4
1429 * INTC - 5
1430 * INTD - 7
1431 */
1432 sp->putb(sp, PCIC_INT_GEN, /* Assume INTA# */
1433 (sp->getb(sp, PCIC_INT_GEN) & 0xF0) | 3);
1434 return (0);
1435 }
1436 return (0);
1437 }
1438
1439 static void
1440 pcic_pci_func_intr(void *arg)
1441 {
1442 struct pcic_softc *sc = (struct pcic_softc *) arg;
1443 struct pcic_slot *sp = &sc->slots[0];
1444 u_int32_t stat;
1445 int doit = 0;
1446
1447 /*
1448 * The 6729 controller is a weird one, and we have to use
1449 * the ISA registers to check to see if the card is there.
1450 * Otherwise we look at the PCI state register to find out
1451 * if the card is there.
1452 */
1453 if (sp->controller == PCIC_PD6729) {
1454 if ((sp->getb(sp, PCIC_STATUS) & PCIC_CD) == PCIC_CD)
1455 doit = 1;
1456 }
1457 else {
1458 stat = bus_space_read_4(sp->bst, sp->bsh, CB_SOCKET_STATE);
1459 if ((stat & CB_SS_CD) == 0 && sc->func_intr != 0)
1460 doit = 1;
1461 }
1462 if (doit && sc->func_intr != NULL)
1463 sc->func_intr(sc->func_arg);
1464 }
1465
1466 static int
1467 pcic_pci_setup_intr(device_t dev, device_t child, struct resource *irq,
1468 int flags, driver_intr_t *intr, void *arg, void **cookiep)
1469 {
1470 struct pcic_softc *sc = device_get_softc(dev);
1471 struct pcic_slot *sp = &sc->slots[0];
1472 int err;
1473
1474 if (sc->func_route == pcic_iw_isa)
1475 return(pcic_setup_intr(dev, child, irq, flags, intr, arg,
1476 cookiep));
1477
1478 #if __FreeBSD_version >= 500000
1479 if ((flags & INTR_FAST) != 0)
1480 #else
1481 if ((flags & INTR_TYPE_FAST) != 0)
1482 #endif
1483 return (EINVAL);
1484 if (sc->func_intr != NULL) {
1485 device_printf(child, "Can't establish another ISR\n");
1486 return (EINVAL);
1487 }
1488
1489 err = bus_generic_setup_intr(dev, child, irq, flags,
1490 pcic_pci_func_intr, sc, cookiep);
1491 if (err != 0)
1492 return (err);
1493 sc->chip->map_irq(sp, rman_get_start(irq));
1494 sc->func_intr = intr;
1495 sc->func_arg = arg;
1496 return (0);
1497 }
1498
1499 static int
1500 pcic_pci_teardown_intr(device_t dev, device_t child, struct resource *irq,
1501 void *cookie)
1502 {
1503 struct pcic_softc *sc = device_get_softc(dev);
1504
1505 if (sc->func_route == pcic_iw_isa)
1506 return (pcic_teardown_intr(dev, child, irq, cookie));
1507 sc->func_intr = NULL;
1508 return (bus_generic_teardown_intr(dev, child, irq, cookie));
1509 }
1510
1511 static int
1512 pcic_pci_resume(device_t dev)
1513 {
1514 struct pcic_softc *sc = device_get_softc(dev);
1515
1516 /*
1517 * Some BIOSes will not save the BARs for the pci chips, so we
1518 * must do it ourselves. If the BAR is reset to 0 for an I/O
1519 * device, it will read back as 0x1, so no explicit test for
1520 * memory devices are needed.
1521 *
1522 * Note: The PCI bus code should do this automatically for us on
1523 * suspend/resume, but until it does, we have to cope.
1524 */
1525 if (pci_read_config(dev, CB_PCI_SOCKET_BASE, 4) == 0)
1526 pci_write_config(dev, CB_PCI_SOCKET_BASE,
1527 rman_get_start(sc->memres), 4);
1528 return (bus_generic_resume(dev));
1529 }
1530
1531 static device_method_t pcic_pci_methods[] = {
1532 /* Device interface */
1533 DEVMETHOD(device_probe, pcic_pci_probe),
1534 DEVMETHOD(device_attach, pcic_pci_attach),
1535 DEVMETHOD(device_detach, pcic_pci_detach),
1536 DEVMETHOD(device_suspend, bus_generic_suspend),
1537 DEVMETHOD(device_resume, pcic_pci_resume),
1538 DEVMETHOD(device_shutdown, pcic_pci_shutdown),
1539
1540 /* Bus interface */
1541 DEVMETHOD(bus_print_child, bus_generic_print_child),
1542 DEVMETHOD(bus_alloc_resource, pcic_alloc_resource),
1543 DEVMETHOD(bus_release_resource, bus_generic_release_resource),
1544 DEVMETHOD(bus_activate_resource, pcic_activate_resource),
1545 DEVMETHOD(bus_deactivate_resource, pcic_deactivate_resource),
1546 DEVMETHOD(bus_setup_intr, pcic_pci_setup_intr),
1547 DEVMETHOD(bus_teardown_intr, pcic_pci_teardown_intr),
1548
1549 /* Card interface */
1550 DEVMETHOD(card_set_res_flags, pcic_set_res_flags),
1551 DEVMETHOD(card_get_res_flags, pcic_get_res_flags),
1552 DEVMETHOD(card_set_memory_offset, pcic_set_memory_offset),
1553 DEVMETHOD(card_get_memory_offset, pcic_get_memory_offset),
1554
1555 {0, 0}
1556 };
1557
1558 static driver_t pcic_pci_driver = {
1559 "pcic",
1560 pcic_pci_methods,
1561 sizeof(struct pcic_softc)
1562 };
1563
1564 DRIVER_MODULE(pcic, pci, pcic_pci_driver, pcic_devclass, 0, 0);
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