FreeBSD/Linux Kernel Cross Reference
sys/pccard/pcic_pci.c
1 /*
2 * Copyright (c) 2000, 2002 M. Warner Losh. All Rights Reserved.
3 * Copyright (c) 1997 Ted Faber All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * 1. Redistributions of source code must retain the above copyright
10 * notice immediately at the beginning of the file, without modification,
11 * this list of conditions, and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. Absolutely no warranty of function or purpose is made by the author
16 * Ted Faber.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 *
29 * $FreeBSD: releng/5.2/sys/pccard/pcic_pci.c 121307 2003-10-21 18:28:36Z silby $
30 */
31
32 #define OBSOLETE_IN_6
33
34 #include <sys/param.h>
35 #include <sys/bus.h>
36 #include <sys/kernel.h>
37 #include <sys/module.h>
38 #include <sys/sysctl.h>
39 #include <sys/systm.h>
40
41 #if __FreeBSD_version < 500000
42 #include <pci/pcireg.h>
43 #include <pci/pcivar.h>
44 #else
45 #include <dev/pci/pcireg.h>
46 #include <dev/pci/pcivar.h>
47 #endif
48
49 #include <pccard/pcic_pci.h>
50 #include <pccard/i82365.h>
51 #include <pccard/cardinfo.h>
52 #include <pccard/slot.h>
53 #include <pccard/pcicvar.h>
54
55 #include <dev/pccard/pccardvar.h>
56 #include "card_if.h"
57
58 #define PRVERB(x) do { \
59 if (bootverbose) { device_printf x; } \
60 } while (0)
61
62 static int pcic_pci_get_memory(device_t dev);
63
64 SYSCTL_DECL(_hw_pcic);
65
66 static int pcic_ignore_function_1 = 0;
67 TUNABLE_INT("hw.pcic.ignore_function_1", &pcic_ignore_function_1);
68 SYSCTL_INT(_hw_pcic, OID_AUTO, ignore_function_1, CTLFLAG_RDTUN,
69 &pcic_ignore_function_1, 0,
70 "When set, driver ignores pci function 1 of the bridge. This option\n\
71 is obsolete and will be deleted before FreeBSD 4.8.");
72
73 /*
74 * The following should be a hint, so we can do it on a per device
75 * instance, but this is convenient. Do not set this unless pci
76 * routing doesn't work. It is purposely vague and undocumented
77 * at the moment. Sadly, this seems to be needed way too often.
78 */
79 static int pcic_intr_path = (int)pcic_iw_pci;
80 TUNABLE_INT("hw.pcic.intr_path", &pcic_intr_path);
81 SYSCTL_INT(_hw_pcic, OID_AUTO, intr_path, CTLFLAG_RDTUN, &pcic_intr_path, 0,
82 "Which path to send the interrupts over. Normally interrupts for\n\
83 cardbus bridges are routed over the PCI bus (2). However, some laptops\n\
84 will hang when using PCI interrupts due to bugs in this code. Those\n\
85 bugs can be worked around by forcings ISA interrupts (1).");
86
87 static int pcic_init_routing = 0;
88 TUNABLE_INT("hw.pcic.init_routing", &pcic_init_routing);
89 SYSCTL_INT(_hw_pcic, OID_AUTO, init_routing, CTLFLAG_RDTUN,
90 &pcic_init_routing, 0,
91 "Force the interrupt routing to be initialized on those bridges where\n\
92 doing so will cause probelms. This is very rare and generally is not\n\
93 needed. The default of 0 is almost always appropriate. Only set to 1 if\n\
94 instructed to do so for debugging. Only TI bridges are affected by this\n\
95 option, and what the code does is of dubious value. This option is obsolete\n\
96 and will be deleted before FreeBSD 4.8.");
97
98 static int pcic_ignore_pci = 0;
99 TUNABLE_INT("hw.pcic.ignore_pci", &pcic_ignore_pci);
100 SYSCTL_INT(_hw_pcic, OID_AUTO, ignore_pci, CTLFLAG_RDTUN,
101 &pcic_ignore_pci, 0,
102 "When set, driver ignores pci cardbus bridges it would otherwise claim.\n\
103 Generally speaking, this option is not needed for anything other than as an\n\
104 aid in debugging.");
105
106 static int pcic_pd6729_intr_path = (int)pcic_iw_isa;
107 TUNABLE_INT("hw.pcic.pd6729_intr_path", &pcic_pd6729_intr_path);
108 SYSCTL_INT(_hw_pcic, OID_AUTO, pd6729_intr_path, CTLFLAG_RDTUN,
109 &pcic_pd6729_intr_path, 0,
110 "Determine the interrupt path or method for Cirrus Logic PD6729 and\n\
111 similar I/O space based pcmcia bridge. Chips on a PCI expansion card need\n\
112 a value of 2, while chips installed in a laptop need a value of 1 (which is\n\
113 also the default). This is similar to hw.pcic.intr_path, but separate so\n\
114 that it can default to ISA when intr_path defaults to PCI.");
115
116 static int pcic_ti12xx_enable_pci_clock = 0;
117 TUNABLE_INT("hw.pcic.ti12xx_enable_pci_clock", &pcic_ti12xx_enable_pci_clock);
118 SYSCTL_INT(_hw_pcic, OID_AUTO, ti12xx_enable_pci_clock, CTLFLAG_RDTUN,
119 &pcic_ti12xx_enable_pci_clock, 0,
120 "Some TI-12xx parts need to have the PCI clock enabled. These designs do\n\
121 not provide a clock themselves. Most of the reference boards have the\n\
122 required oscillator parts, so the number of machines that needs this to be\n\
123 set is vanishingly small.");
124
125 static void pcic_pci_cardbus_init(device_t);
126 static pcic_intr_way_t pcic_pci_gen_func;
127 static pcic_intr_way_t pcic_pci_gen_csc;
128 static pcic_intr_mapirq_t pcic_pci_gen_mapirq;
129
130 static pcic_intr_way_t pcic_pci_oz67xx_func;
131 static pcic_intr_way_t pcic_pci_oz67xx_csc;
132 static pcic_init_t pcic_pci_oz67xx_init;
133
134 static pcic_intr_way_t pcic_pci_oz68xx_func;
135 static pcic_intr_way_t pcic_pci_oz68xx_csc;
136 static pcic_init_t pcic_pci_oz68xx_init;
137
138 static pcic_intr_way_t pcic_pci_pd6729_func;
139 static pcic_intr_way_t pcic_pci_pd6729_csc;
140 static pcic_init_t pcic_pci_pd6729_init;
141
142 static pcic_intr_way_t pcic_pci_pd68xx_func;
143 static pcic_intr_way_t pcic_pci_pd68xx_csc;
144 static pcic_init_t pcic_pci_pd68xx_init;
145
146 static pcic_intr_way_t pcic_pci_ricoh_func;
147 static pcic_intr_way_t pcic_pci_ricoh_csc;
148 static pcic_init_t pcic_pci_ricoh_init;
149
150 static pcic_intr_way_t pcic_pci_ti113x_func;
151 static pcic_intr_way_t pcic_pci_ti113x_csc;
152 static pcic_init_t pcic_pci_ti_init;
153
154 static pcic_intr_way_t pcic_pci_ti12xx_func;
155 static pcic_intr_way_t pcic_pci_ti12xx_csc;
156
157 static pcic_intr_way_t pcic_pci_topic_func;
158 static pcic_intr_way_t pcic_pci_topic_csc;
159 static pcic_init_t pcic_pci_topic_init;
160
161 static struct pcic_chip pcic_pci_oz67xx_chip = {
162 pcic_pci_oz67xx_func,
163 pcic_pci_oz67xx_csc,
164 pcic_pci_gen_mapirq,
165 pcic_pci_oz67xx_init
166 };
167
168 static struct pcic_chip pcic_pci_oz68xx_chip = {
169 pcic_pci_oz68xx_func,
170 pcic_pci_oz68xx_csc,
171 pcic_pci_gen_mapirq,
172 pcic_pci_oz68xx_init
173 };
174
175 static struct pcic_chip pcic_pci_pd6729_chip = {
176 pcic_pci_pd6729_func,
177 pcic_pci_pd6729_csc,
178 pcic_pci_gen_mapirq,
179 pcic_pci_pd6729_init
180 };
181
182 static struct pcic_chip pcic_pci_pd68xx_chip = {
183 pcic_pci_pd68xx_func,
184 pcic_pci_pd68xx_csc,
185 pcic_pci_gen_mapirq,
186 pcic_pci_pd68xx_init
187 };
188
189 static struct pcic_chip pcic_pci_ricoh_chip = {
190 pcic_pci_ricoh_func,
191 pcic_pci_ricoh_csc,
192 pcic_pci_gen_mapirq,
193 pcic_pci_ricoh_init
194 };
195
196 static struct pcic_chip pcic_pci_ti113x_chip = {
197 pcic_pci_ti113x_func,
198 pcic_pci_ti113x_csc,
199 pcic_pci_gen_mapirq,
200 pcic_pci_ti_init
201 };
202
203 static struct pcic_chip pcic_pci_ti12xx_chip = {
204 pcic_pci_ti12xx_func,
205 pcic_pci_ti12xx_csc,
206 pcic_pci_gen_mapirq,
207 pcic_pci_ti_init
208 };
209
210 static struct pcic_chip pcic_pci_topic_chip = {
211 pcic_pci_topic_func,
212 pcic_pci_topic_csc,
213 pcic_pci_gen_mapirq,
214 pcic_pci_topic_init
215 };
216
217 static struct pcic_chip pcic_pci_generic_chip = {
218 pcic_pci_gen_func,
219 pcic_pci_gen_csc,
220 pcic_pci_gen_mapirq,
221 pcic_pci_cardbus_init
222 };
223
224 /* Chipset specific flags */
225 #define TI_NO_MFUNC 0x10000
226
227 struct pcic_pci_table
228 {
229 u_int32_t devid;
230 const char *descr;
231 int type;
232 u_int32_t flags;
233 struct pcic_chip *chip;
234 } pcic_pci_devs[] = {
235 { PCIC_ID_OMEGA_82C094, "Omega 82C094G",
236 PCIC_I82365, PCIC_DF_POWER, &pcic_pci_pd6729_chip },
237 { PCIC_ID_CLPD6729, "Cirrus Logic PD6729/6730 PCI-PCMCIA Bridge",
238 PCIC_PD6729, PCIC_PD_POWER, &pcic_pci_pd6729_chip },
239 { PCIC_ID_CLPD6832, "Cirrus Logic PD6832 PCI-CardBus Bridge",
240 PCIC_PD673X, PCIC_CARDBUS_POWER, &pcic_pci_pd68xx_chip },
241 { PCIC_ID_CLPD6833, "Cirrus Logic PD6833 PCI-CardBus Bridge",
242 PCIC_PD673X, PCIC_CARDBUS_POWER, &pcic_pci_pd68xx_chip },
243 { PCIC_ID_CLPD6834, "Cirrus Logic PD6834 PCI-CardBus Bridge",
244 PCIC_PD673X, PCIC_CARDBUS_POWER, &pcic_pci_pd68xx_chip },
245 { PCIC_ID_OZ6729, "O2micro OZ6729 PC-Card Bridge",
246 PCIC_I82365, PCIC_AB_POWER, &pcic_pci_oz67xx_chip },
247 { PCIC_ID_OZ6730, "O2micro OZ6730 PC-Card Bridge",
248 PCIC_I82365, PCIC_AB_POWER, &pcic_pci_oz67xx_chip },
249 { PCIC_ID_OZ6832, "O2micro 6832/6833 PCI-Cardbus Bridge",
250 PCIC_I82365, PCIC_CARDBUS_POWER, &pcic_pci_oz68xx_chip },
251 { PCIC_ID_OZ6860, "O2micro 6836/6860 PCI-Cardbus Bridge",
252 PCIC_I82365, PCIC_CARDBUS_POWER, &pcic_pci_oz68xx_chip },
253 { PCIC_ID_OZ6872, "O2micro 6812/6872 PCI-Cardbus Bridge",
254 PCIC_I82365, PCIC_CARDBUS_POWER, &pcic_pci_oz68xx_chip },
255 { PCIC_ID_OZ6912, "O2micro 6912 PCI-Cardbus Bridge",
256 PCIC_I82365, PCIC_CARDBUS_POWER, &pcic_pci_oz68xx_chip },
257 { PCIC_ID_OZ6922, "O2micro 6922 PCI-Cardbus Bridge",
258 PCIC_I82365, PCIC_AB_POWER, &pcic_pci_oz68xx_chip },
259 { PCIC_ID_OZ6933, "O2micro 6933 PCI-Cardbus Bridge",
260 PCIC_I82365, PCIC_AB_POWER, &pcic_pci_oz68xx_chip },
261 { PCIC_ID_RICOH_RL5C465, "Ricoh RL5C465 PCI-CardBus Bridge",
262 PCIC_RF5C296, PCIC_CARDBUS_POWER, &pcic_pci_ricoh_chip },
263 { PCIC_ID_RICOH_RL5C475, "Ricoh RL5C475 PCI-CardBus Bridge",
264 PCIC_RF5C296, PCIC_CARDBUS_POWER, &pcic_pci_ricoh_chip },
265 { PCIC_ID_RICOH_RL5C476, "Ricoh RL5C476 PCI-CardBus Bridge",
266 PCIC_RF5C296, PCIC_CARDBUS_POWER, &pcic_pci_ricoh_chip },
267 { PCIC_ID_RICOH_RL5C477, "Ricoh RL5C477 PCI-CardBus Bridge",
268 PCIC_RF5C296, PCIC_CARDBUS_POWER, &pcic_pci_ricoh_chip },
269 { PCIC_ID_RICOH_RL5C478, "Ricoh RL5C478 PCI-CardBus Bridge",
270 PCIC_RF5C296, PCIC_CARDBUS_POWER, &pcic_pci_ricoh_chip },
271 { PCIC_ID_SMC_34C90, "SMC 34C90 PCI-CardBus Bridge",
272 PCIC_RF5C296, PCIC_CARDBUS_POWER, &pcic_pci_generic_chip },
273 { PCIC_ID_TI1031, "TI PCI-1031 PCI-PCMCIA Bridge",
274 PCIC_I82365SL_DF, PCIC_CARDBUS_POWER, &pcic_pci_ti113x_chip },
275 { PCIC_ID_TI1130, "TI PCI-1130 PCI-CardBus Bridge",
276 PCIC_I82365SL_DF, PCIC_CARDBUS_POWER, &pcic_pci_ti113x_chip },
277 { PCIC_ID_TI1131, "TI PCI-1131 PCI-CardBus Bridge",
278 PCIC_I82365SL_DF, PCIC_CARDBUS_POWER, &pcic_pci_ti113x_chip },
279 { PCIC_ID_TI1210, "TI PCI-1210 PCI-CardBus Bridge",
280 PCIC_I82365SL_DF, PCIC_CARDBUS_POWER, &pcic_pci_ti12xx_chip },
281 { PCIC_ID_TI1211, "TI PCI-1211 PCI-CardBus Bridge",
282 PCIC_I82365SL_DF, PCIC_CARDBUS_POWER, &pcic_pci_ti12xx_chip },
283 { PCIC_ID_TI1220, "TI PCI-1220 PCI-CardBus Bridge",
284 PCIC_I82365SL_DF, PCIC_CARDBUS_POWER, &pcic_pci_ti12xx_chip },
285 { PCIC_ID_TI1221, "TI PCI-1221 PCI-CardBus Bridge",
286 PCIC_I82365SL_DF, PCIC_CARDBUS_POWER, &pcic_pci_ti12xx_chip },
287 { PCIC_ID_TI1225, "TI PCI-1225 PCI-CardBus Bridge",
288 PCIC_I82365SL_DF, PCIC_CARDBUS_POWER, &pcic_pci_ti12xx_chip },
289 { PCIC_ID_TI1250, "TI PCI-1250 PCI-CardBus Bridge",
290 PCIC_I82365SL_DF, PCIC_CARDBUS_POWER | TI_NO_MFUNC,
291 &pcic_pci_ti12xx_chip },
292 { PCIC_ID_TI1251, "TI PCI-1251 PCI-CardBus Bridge",
293 PCIC_I82365SL_DF, PCIC_CARDBUS_POWER | TI_NO_MFUNC,
294 &pcic_pci_ti12xx_chip },
295 { PCIC_ID_TI1251B, "TI PCI-1251B PCI-CardBus Bridge",
296 PCIC_I82365SL_DF, PCIC_CARDBUS_POWER | TI_NO_MFUNC,
297 &pcic_pci_ti12xx_chip },
298 { PCIC_ID_TI1260, "TI PCI-1260 PCI-CardBus Bridge",
299 PCIC_I82365SL_DF, PCIC_CARDBUS_POWER, &pcic_pci_ti12xx_chip },
300 { PCIC_ID_TI1260B, "TI PCI-1260B PCI-CardBus Bridge",
301 PCIC_I82365SL_DF, PCIC_CARDBUS_POWER, &pcic_pci_ti12xx_chip },
302 { PCIC_ID_TI1410, "TI PCI-1410 PCI-CardBus Bridge",
303 PCIC_I82365SL_DF, PCIC_CARDBUS_POWER, &pcic_pci_ti12xx_chip },
304 { PCIC_ID_TI1420, "TI PCI-1420 PCI-CardBus Bridge",
305 PCIC_I82365SL_DF, PCIC_CARDBUS_POWER, &pcic_pci_ti12xx_chip },
306 { PCIC_ID_TI1421, "TI PCI-1421 PCI-CardBus Bridge",
307 PCIC_I82365SL_DF, PCIC_CARDBUS_POWER, &pcic_pci_ti12xx_chip },
308 { PCIC_ID_TI1450, "TI PCI-1450 PCI-CardBus Bridge",
309 PCIC_I82365SL_DF, PCIC_CARDBUS_POWER | TI_NO_MFUNC,
310 &pcic_pci_ti12xx_chip },
311 { PCIC_ID_TI1451, "TI PCI-1451 PCI-CardBus Bridge",
312 PCIC_I82365SL_DF, PCIC_CARDBUS_POWER, &pcic_pci_ti12xx_chip },
313 { PCIC_ID_TI1510, "TI PCI-1510 PCI-CardBus Bridge",
314 PCIC_I82365SL_DF, PCIC_CARDBUS_POWER, &pcic_pci_ti12xx_chip },
315 { PCIC_ID_TI1520, "TI PCI-1520 PCI-CardBus Bridge",
316 PCIC_I82365SL_DF, PCIC_CARDBUS_POWER, &pcic_pci_ti12xx_chip },
317 { PCIC_ID_TI4410, "TI PCI-4410 PCI-CardBus Bridge",
318 PCIC_I82365SL_DF, PCIC_CARDBUS_POWER, &pcic_pci_ti12xx_chip },
319 { PCIC_ID_TI4450, "TI PCI-4450 PCI-CardBus Bridge",
320 PCIC_I82365SL_DF, PCIC_CARDBUS_POWER, &pcic_pci_ti12xx_chip },
321 { PCIC_ID_TI4451, "TI PCI-4451 PCI-CardBus Bridge",
322 PCIC_I82365SL_DF, PCIC_CARDBUS_POWER, &pcic_pci_ti12xx_chip },
323 { PCIC_ID_TI4510, "TI PCI-4510 PCI-CardBus Bridge",
324 PCIC_I82365SL_DF, PCIC_CARDBUS_POWER, &pcic_pci_ti12xx_chip },
325 { PCIC_ID_TOPIC95, "Toshiba ToPIC95 PCI-CardBus Bridge",
326 PCIC_I82365, PCIC_CARDBUS_POWER, &pcic_pci_topic_chip },
327 { PCIC_ID_TOPIC95B, "Toshiba ToPIC95B PCI-CardBus Bridge",
328 PCIC_I82365, PCIC_CARDBUS_POWER, &pcic_pci_topic_chip },
329 { PCIC_ID_TOPIC97, "Toshiba ToPIC97 PCI-CardBus Bridge",
330 PCIC_I82365, PCIC_CARDBUS_POWER, &pcic_pci_topic_chip },
331 { PCIC_ID_TOPIC100, "Toshiba ToPIC100 PCI-CardBus Bridge",
332 PCIC_I82365, PCIC_CARDBUS_POWER, &pcic_pci_topic_chip },
333 { 0, NULL, 0, 0, NULL }
334 };
335
336 /*
337 * Read a register from the PCIC.
338 */
339 static unsigned char
340 pcic_pci_getb2(struct pcic_slot *sp, int reg)
341 {
342 return (bus_space_read_1(sp->bst, sp->bsh, sp->offset + reg));
343 }
344
345 /*
346 * Write a register on the PCIC
347 */
348 static void
349 pcic_pci_putb2(struct pcic_slot *sp, int reg, unsigned char val)
350 {
351 bus_space_write_1(sp->bst, sp->bsh, sp->offset + reg, val);
352 }
353
354 /*
355 * lookup inside the table
356 */
357 static struct pcic_pci_table *
358 pcic_pci_lookup(u_int32_t devid, struct pcic_pci_table *tbl)
359 {
360 while (tbl->devid) {
361 if (tbl->devid == devid)
362 return (tbl);
363 tbl++;
364 }
365 return (NULL);
366 }
367
368 /*
369 * The standard way to control fuction interrupts is via bit 7 in the BCR
370 * register. Some data sheets indicate that this is just for "intterupts"
371 * while others are clear that it is for function interrupts. When this
372 * bit is set, function interrupts are routed via the ExCA register. When
373 * this bit is clear, they are routed via the PCI bus, usually via the int
374 * in the INTPIN register.
375 */
376 static int
377 pcic_pci_gen_func(struct pcic_slot *sp, enum pcic_intr_way way)
378 {
379 u_int16_t bcr;
380
381 bcr = pci_read_config(sp->sc->dev, CB_PCI_BRIDGE_CTRL, 2);
382 if (way == pcic_iw_pci)
383 bcr &= ~CB_BCR_INT_EXCA;
384 else
385 bcr |= CB_BCR_INT_EXCA;
386 pci_write_config(sp->sc->dev, CB_PCI_BRIDGE_CTRL, bcr, 2);
387 return (0);
388 }
389
390 static int
391 pcic_pci_gen_csc(struct pcic_slot *sp, enum pcic_intr_way way)
392 {
393 return (0);
394 }
395
396 /*
397 * The O2micro OZ67xx chips functions.
398 */
399 static int
400 pcic_pci_oz67xx_func(struct pcic_slot *sp, enum pcic_intr_way way)
401 {
402 return (pcic_pci_gen_func(sp, way));
403 }
404
405 static int
406 pcic_pci_oz67xx_csc(struct pcic_slot *sp, enum pcic_intr_way way)
407 {
408 /*
409 * Need datasheet to find out what's going on. However, the
410 * 68xx datasheets are so vague that it is hard to know what
411 * the right thing to do is.
412 */
413 /* XXX */
414 return (0);
415 }
416
417
418 static void
419 pcic_pci_oz67xx_init(device_t dev)
420 {
421 device_printf(dev, "Warning: O2micro OZ67xx chips may not work\n");
422 pcic_pci_cardbus_init(dev);
423 }
424
425 /*
426 * The O2micro OZ68xx chips functions.
427 */
428 static int
429 pcic_pci_oz68xx_func(struct pcic_slot *sp, enum pcic_intr_way way)
430 {
431 return (pcic_pci_gen_func(sp, way));
432 }
433
434 static int
435 pcic_pci_oz68xx_csc(struct pcic_slot *sp, enum pcic_intr_way way)
436 {
437 /*
438 * The 68xx datasheets make it hard to know what the right thing
439 * to do here is. We do what we know, which is nothing, and
440 * hope for the best.
441 *
442 * XXX NEWCARD may have some useful code here.
443 */
444 /* XXX */
445 return (0);
446 }
447
448 static void
449 pcic_pci_oz68xx_init(device_t dev)
450 {
451 /*
452 * This is almost certainly incomplete.
453 */
454 device_printf(dev, "Warning: O2micro OZ68xx chips may not work\n");
455 pcic_pci_cardbus_init(dev);
456 }
457
458 /*
459 * The Cirrus Logic PD6729/30. These are weird beasts, so be careful.
460 * They are ISA parts glued to the PCI bus and do not follow the yenta
461 * specification for cardbus bridges. They seem to be similar to the
462 * intel parts that were also cloned by o2micro and maybe others, but
463 * they are so much more common that the author doesn't have experience
464 * with them to know for sure.
465 */
466 static int
467 pcic_pci_pd6729_func(struct pcic_slot *sp, enum pcic_intr_way way)
468 {
469 /*
470 * For pci interrupts, we need to set bit 3 of extension register
471 * 3 to 1. For ISA interrupts, we need to clear it.
472 */
473 sp->putb(sp, PCIC_EXT_IND, PCIC_EXTCTRL1);
474 if (way == pcic_iw_pci)
475 pcic_setb(sp, PCIC_EXTENDED, PCIC_EC1_CARD_IRQ_INV);
476 else
477 pcic_clrb(sp, PCIC_EXTENDED, PCIC_EC1_CARD_IRQ_INV);
478
479 return (0);
480 }
481
482 static int
483 pcic_pci_pd6729_csc(struct pcic_slot *sp, enum pcic_intr_way way)
484 {
485 /*
486 * For pci interrupts, we need to set bit 4 of extension register
487 * 3 to 1. For ISA interrupts, we need to clear it.
488 */
489 sp->putb(sp, PCIC_EXT_IND, PCIC_EXTCTRL1);
490 if (way == pcic_iw_pci)
491 pcic_setb(sp, PCIC_EXTENDED, PCIC_EC1_CSC_IRQ_INV);
492 else
493 pcic_clrb(sp, PCIC_EXTENDED, PCIC_EC1_CSC_IRQ_INV);
494
495 return (0);
496 }
497
498
499 static void
500 pcic_pci_pd6729_init(device_t dev)
501 {
502 struct pcic_softc *sc = device_get_softc(dev);
503
504 /*
505 * Tell the chip to do its routing thing.
506 */
507 pcic_pci_pd6729_func(&sc->slots[0], sc->func_route);
508 pcic_pci_pd6729_csc(&sc->slots[0], sc->csc_route);
509 }
510
511 /*
512 * Set up the CL-PD6832, 6833 and 6834.
513 */
514 static int
515 pcic_pci_pd68xx_func(struct pcic_slot *sp, enum pcic_intr_way way)
516 {
517 return (pcic_pci_gen_func(sp, way));
518 }
519
520 static int
521 pcic_pci_pd68xx_csc(struct pcic_slot *sp, enum pcic_intr_way way)
522 {
523 struct pcic_softc *sc = sp->sc;
524 device_t dev = sc->dev;
525 u_int32_t device_id = pci_get_devid(dev);
526 u_long bcr;
527 u_long cm1;
528
529 /*
530 * CLPD6832 management interrupt enable bit is bit 11
531 * (MGMT_IRQ_ENA) in bridge control register(offset 0x3d).
532 * When on, card status interrupts are ISA controlled by
533 * the ExCA register 0x05.
534 *
535 * The CLPD6833 does things differently. It doesn't have bit
536 * 11 in the bridge control register. Instead, this
537 * functionality appears to be in the "Configuration
538 * Miscellaneous 1" register bit 1.
539 *
540 * I'm assuming that the CLPD6834 does things like the '33
541 */
542 if (device_id == PCIC_ID_CLPD6832) {
543 bcr = pci_read_config(dev, CB_PCI_BRIDGE_CTRL, 2);
544 if (way == pcic_iw_pci)
545 bcr &= ~CLPD6832_BCR_MGMT_IRQ_ENA;
546 else
547 bcr |= CLPD6832_BCR_MGMT_IRQ_ENA;
548 pci_write_config(dev, CB_PCI_BRIDGE_CTRL, bcr, 2);
549 }
550 if (device_id != PCIC_ID_CLPD6832) {
551 cm1 = pci_read_config(dev, CLPD6833_CFG_MISC_1, 4);
552 if (way == pcic_iw_pci)
553 cm1 &= ~CLPD6833_CM1_MGMT_EXCA_ENA;
554 else
555 cm1 |= CLPD6833_CM1_MGMT_EXCA_ENA;
556 pci_write_config(dev, CLPD6833_CFG_MISC_1, cm1, 4);
557 }
558 return (0);
559 }
560
561 static void
562 pcic_pci_pd68xx_init(device_t dev)
563 {
564 pcic_pci_cardbus_init(dev);
565 }
566
567 static int
568 pcic_pci_ricoh_func(struct pcic_slot *sp, enum pcic_intr_way way)
569 {
570 return (pcic_pci_gen_func(sp, way));
571 }
572
573 static int
574 pcic_pci_ricoh_csc(struct pcic_slot *sp, enum pcic_intr_way way)
575 {
576 struct pcic_softc *sc = sp->sc;
577 device_t dev = sc->dev;
578 u_int16_t mcr2;
579
580 /*
581 * For CSC interrupts via ISA, we can't do that exactly.
582 * However, we can disable INT# routing, which is usually what
583 * we want. This is bit 7 in the field. Note, bit 6 looks
584 * interesting, but appears to be unnecessary.
585 */
586 mcr2 = pci_read_config(dev, R5C47X_MISC_CONTROL_REGISTER_2, 2);
587 if (way == pcic_iw_pci)
588 mcr2 &= ~R5C47X_MCR2_CSC_TO_INTX_DISABLE;
589 else
590 mcr2 |= R5C47X_MCR2_CSC_TO_INTX_DISABLE;
591 pci_write_config(dev, R5C47X_MISC_CONTROL_REGISTER_2, mcr2, 2);
592
593 return (0);
594 }
595
596 static void
597 pcic_pci_ricoh_init(device_t dev)
598 {
599 u_int16_t brgcntl;
600 u_int32_t device_id = pci_get_devid(dev);
601
602 switch (device_id) {
603 case PCIC_ID_RICOH_RL5C465:
604 case PCIC_ID_RICOH_RL5C466:
605 /*
606 * Ricoh chips have a legacy bridge enable different than most
607 * Code cribbed from NEWBUS's bridge code since I can't find a
608 * datasheet for them that has register definitions.
609 */
610 brgcntl = pci_read_config(dev, CB_PCI_BRIDGE_CTRL, 2);
611 brgcntl &= ~(CB_BCR_RL_3E2_EN | CB_BCR_RL_3E0_EN);
612 pci_write_config(dev, CB_PCI_BRIDGE_CTRL, brgcntl, 2);
613 break;
614 }
615 pcic_pci_cardbus_init(dev);
616 }
617
618 /*
619 * TI 1030, 1130, and 1131.
620 */
621 static int
622 pcic_pci_ti113x_func(struct pcic_slot *sp, enum pcic_intr_way way)
623 {
624 u_int32_t cardcntl;
625 device_t dev = sp->sc->dev;
626
627 /*
628 * The TI-1130 (and 1030 and 1131) have a different interrupt
629 * routing control than the newer chips. assume we're not
630 * routing either csc or func interrupts via PCI, but enable
631 * as necessary when we find someone uses PCI interrupts. In
632 * order to get any pci interrupts, PCI_IRQ_ENA (bit 5) must
633 * be set. If either PCI_IREQ (bit 4) or PCI_CSC (bit 3) are
634 * set, then set bit 5 at the same time, since setting them
635 * enables the PCI interrupt routing.
636 *
637 * It also appears necessary to set the function routing bit
638 * in the bridge control register, but cardbus_init does that
639 * for us.
640 */
641 cardcntl = pci_read_config(dev, TI113X_PCI_CARD_CONTROL, 1);
642 if (way == pcic_iw_pci)
643 cardcntl |= TI113X_CARDCNTL_PCI_IREQ;
644 else
645 cardcntl &= ~TI113X_CARDCNTL_PCI_IREQ;
646 if (cardcntl & (TI113X_CARDCNTL_PCI_IREQ | TI113X_CARDCNTL_PCI_CSC))
647 cardcntl |= TI113X_CARDCNTL_PCI_IRQ_ENA;
648 else
649 cardcntl &= ~TI113X_CARDCNTL_PCI_IRQ_ENA;
650 pci_write_config(dev, TI113X_PCI_CARD_CONTROL, cardcntl, 1);
651
652 return (pcic_pci_gen_func(sp, way));
653 }
654
655 static int
656 pcic_pci_ti113x_csc(struct pcic_slot *sp, enum pcic_intr_way way)
657 {
658 u_int32_t cardcntl;
659 device_t dev = sp->sc->dev;
660
661 /*
662 * The TI-1130 (and 1030 and 1131) have a different interrupt
663 * routing control than the newer cards. assume we're not
664 * routing PCI, but enable as necessary when we find someone
665 * uses PCI interrupts. In order to get any pci interrupts,
666 * PCI_IRQ_ENA (bit 5) must be set. If either PCI_IREQ (bit
667 * 4) or PCI_CSC (bit 3) are set, then set bit 5 at the same
668 * time, since setting them enables the PCI interrupt routing.
669 *
670 * It also appears necessary to set the function routing bit
671 * in the bridge control register, but cardbus_init does that
672 * for us.
673 */
674 cardcntl = pci_read_config(dev, TI113X_PCI_CARD_CONTROL, 1);
675 if (way == pcic_iw_pci)
676 cardcntl |= TI113X_CARDCNTL_PCI_CSC;
677 else
678 cardcntl &= ~TI113X_CARDCNTL_PCI_CSC;
679 if (cardcntl & (TI113X_CARDCNTL_PCI_IREQ | TI113X_CARDCNTL_PCI_CSC))
680 cardcntl |= TI113X_CARDCNTL_PCI_IRQ_ENA;
681 else
682 cardcntl &= ~TI113X_CARDCNTL_PCI_IRQ_ENA;
683 pci_write_config(dev, TI113X_PCI_CARD_CONTROL, cardcntl, 1);
684
685 return (0);
686 }
687
688 static int
689 pcic_pci_ti12xx_func(struct pcic_slot *sp, enum pcic_intr_way way)
690 {
691 u_int32_t syscntl, devcntl, cardcntl, mfunc;
692 device_t dev = sp->sc->dev;
693
694 syscntl = pci_read_config(dev, TI113X_PCI_SYSTEM_CONTROL, 4);
695 devcntl = pci_read_config(dev, TI113X_PCI_DEVICE_CONTROL, 1);
696 cardcntl = pci_read_config(dev, TI113X_PCI_CARD_CONTROL, 1);
697
698 /*
699 * Special code for the Orinoco cards (and a few others). They
700 * seem to need this special code to make them work only over pci
701 * interrupts. Sadly, doing this code also causes problems for
702 * many laptops, so we have to make it controlled by a tunable.
703 * Actually, experience has shown that this rarely, if ever,
704 * helps.
705 */
706 if (way == pcic_iw_pci) {
707 /*
708 * pcic_init_routing seems to do nothing useful towards
709 * fixing the hang problems. I plan on removing it in
710 * 4.8 or so.
711 */
712 if (pcic_init_routing) {
713 devcntl &= ~TI113X_DEVCNTL_INTR_MASK;
714 pci_write_config(dev, TI113X_PCI_DEVICE_CONTROL,
715 devcntl, 1);
716 syscntl |= TI113X_SYSCNTL_INTRTIE;
717 }
718
719 /*
720 * I've had reports that we need the pci clock enabled,
721 * provide a hook to do so. The number of cards that
722 * require this is quite small.
723 */
724 if (pcic_ti12xx_enable_pci_clock) {
725 syscntl |= TI12XX_SYSCNTL_PCI_CLOCK;
726 pci_write_config(dev, TI113X_PCI_SYSTEM_CONTROL,
727 syscntl, 4);
728 }
729
730 /*
731 * Some PCI add-in cards don't have good EEPROMs on them,
732 * so they get this MUX register wrong. The MUX register
733 * defaults to 0, which is usually wrong for this register,
734 * so we initialize it to make sense.
735 *
736 * We don't bother to turn it off in the ISA case since it
737 * is an initialization issue.
738 *
739 * A few weird TI bridges don't have MFUNC, so filter
740 * those out too.
741 */
742 if ((sp->sc->flags & TI_NO_MFUNC) == 0) {
743 mfunc = pci_read_config(dev, TI12XX_PCI_MFUNC, 4);
744 if (mfunc == 0) {
745 mfunc = (mfunc & ~TI12XX_MFUNC_PIN0) |
746 TI12XX_MFUNC_PIN0_INTA;
747 if ((syscntl & TI113X_SYSCNTL_INTRTIE) == 0)
748 mfunc = (mfunc & ~TI12XX_MFUNC_PIN1) |
749 TI12XX_MFUNC_PIN1_INTB;
750 pci_write_config(dev, TI12XX_PCI_MFUNC, mfunc,
751 4);
752 }
753 }
754
755 }
756 return (pcic_pci_gen_func(sp, way));
757 }
758
759 static int
760 pcic_pci_ti12xx_csc(struct pcic_slot *sp, enum pcic_intr_way way)
761 {
762 /*
763 * Nothing happens here. The TI12xx parts will route the
764 * CSC interrupt via PCI if ExCA register tells it to use
765 * interrupt 0. And via IRQ otherwise (except for reserved
766 * values which may or may not do anything).
767 *
768 * We just hope for the best here that doing nothing is the
769 * right thing to do.
770 */
771 return (0);
772 }
773
774 /*
775 * TI PCI-CardBus Host Adapter specific function code.
776 * This function is separated from pcic_pci_attach().
777 * Takeshi Shibagaki(shiba@jp.freebsd.org).
778 */
779 static void
780 pcic_pci_ti_init(device_t dev)
781 {
782 u_int32_t syscntl, diagctl, devcntl, cardcntl;
783 u_int32_t device_id = pci_get_devid(dev);
784 int ti113x = (device_id == PCIC_ID_TI1031) ||
785 (device_id == PCIC_ID_TI1130) ||
786 (device_id == PCIC_ID_TI1131);
787
788 syscntl = pci_read_config(dev, TI113X_PCI_SYSTEM_CONTROL, 4);
789 devcntl = pci_read_config(dev, TI113X_PCI_DEVICE_CONTROL, 1);
790 cardcntl = pci_read_config(dev, TI113X_PCI_CARD_CONTROL, 1);
791
792 if (ti113x) {
793 device_printf(dev, "TI113X PCI Config Reg: ");
794 if (syscntl & TI113X_SYSCNTL_CLKRUN_ENA) {
795 if (syscntl & TI113X_SYSCNTL_CLKRUN_SEL)
796 printf("[clkrun irq 12]");
797 else
798 printf("[clkrun irq 10]");
799 }
800 } else {
801 device_printf(dev, "TI12XX PCI Config Reg: ");
802
803 /*
804 * Turn on async CSC interrupts. This appears to
805 * be the default, but the old, pre pci-aware, code
806 * did this and it appears PAO does as well.
807 */
808 diagctl = pci_read_config(dev, TI12XX_PCI_DIAGNOSTIC, 1);
809 diagctl |= TI12XX_DIAG_CSC_INTR;
810 pci_write_config(dev, TI12XX_PCI_DIAGNOSTIC, diagctl, 1);
811
812 /*
813 * Turn off Zoom Video. Some cards have this enabled,
814 * some do not but it causes problems when enabled. This
815 * register doesn't exist on the 1130 (and likely the 1131,
816 * but without a datasheet it is impossible to know).
817 * Some 12xx chips may not have it, but setting it is
818 * believed to be harmless on those models.
819 */
820 pci_write_config(dev, TI12XX_PCI_MULTIMEDIA_CONTROL, 0, 4);
821 }
822 if (cardcntl & TI113X_CARDCNTL_RING_ENA)
823 printf("[ring enable]");
824 if (cardcntl & TI113X_CARDCNTL_SPKR_ENA)
825 printf("[speaker enable]");
826 if (syscntl & TI113X_SYSCNTL_PWRSAVINGS)
827 printf("[pwr save]");
828 switch(devcntl & TI113X_DEVCNTL_INTR_MASK){
829 case TI113X_DEVCNTL_INTR_ISA :
830 printf("[CSC parallel isa irq]");
831 break;
832 case TI113X_DEVCNTL_INTR_SERIAL :
833 printf("[CSC serial isa irq]");
834 break;
835 case TI113X_DEVCNTL_INTR_NONE :
836 printf("[pci only]");
837 break;
838 case TI12XX_DEVCNTL_INTR_ALLSERIAL :
839 printf("[FUNC pci int + CSC serial isa irq]");
840 break;
841 }
842 printf("\n");
843 pcic_pci_cardbus_init(dev);
844 }
845
846 /*
847 * Code for TOPIC chips
848 */
849 static int
850 pcic_pci_topic_func(struct pcic_slot *sp, enum pcic_intr_way way)
851 {
852 #ifdef THIS_BRAEKS_THINGS
853 device_t dev = sp->sc->dev;
854 u_int32_t scr;
855
856 scr = pci_read_config(dev, TOPIC_SOCKET_CTRL, 4);
857 if (way == pcic_iw_pci)
858 scr |= TOPIC_SOCKET_CTRL_SCR_IRQSEL;
859 else
860 scr &= ~TOPIC_SOCKET_CTRL_SCR_IRQSEL;
861 pci_write_config(dev, TOPIC_SLOT_CTRL, scr, 4);
862 #endif
863 return (pcic_pci_gen_func(sp, way));
864 }
865
866 static int
867 pcic_pci_topic_csc(struct pcic_slot *sp, enum pcic_intr_way way)
868 {
869 device_t dev = sp->sc->dev;
870 u_int32_t scr;
871 u_int32_t device_id;
872
873 device_id = pci_get_devid(dev);
874 if (device_id == PCIC_ID_TOPIC100 || device_id == PCIC_ID_TOPIC97) {
875 scr = pci_read_config(dev, TOPIC_SLOT_CTRL, 4);
876 if (way == pcic_iw_pci)
877 scr |= TOPIC97_SLOT_CTRL_PCIINT;
878 else
879 scr &= ~TOPIC97_SLOT_CTRL_PCIINT;
880 pci_write_config(dev, TOPIC_SLOT_CTRL, scr, 4);
881 }
882
883 return (0);
884 }
885
886 static void
887 pcic_pci_topic_init(device_t dev)
888 {
889 struct pcic_softc *sc = device_get_softc(dev);
890 u_int32_t reg;
891 u_int32_t device_id;
892
893 device_id = pci_get_devid(dev);
894 reg = pci_read_config(dev, TOPIC_SLOT_CTRL, 4);
895 reg |= (TOPIC_SLOT_CTRL_SLOTON | TOPIC_SLOT_CTRL_SLOTEN |
896 TOPIC_SLOT_CTRL_ID_LOCK | TOPIC_SLOT_CTRL_CARDBUS);
897 reg &= ~TOPIC_SLOT_CTRL_SWDETECT;
898 if (device_id == PCIC_ID_TOPIC100 || device_id == PCIC_ID_TOPIC97) {
899 reg |= TOPIC97_SLOT_CTRL_PCIINT;
900 reg &= ~(TOPIC97_SLOT_CTRL_STSIRQP | TOPIC97_SLOT_CTRL_IRQP);
901 }
902 pci_write_config(dev, TOPIC_SLOT_CTRL, reg, 4);
903 pcic_pci_cardbus_init(dev);
904
905 if (device_id == PCIC_ID_TOPIC100 || device_id == PCIC_ID_TOPIC97) {
906 /*
907 * We need to enable voltage sense and 3V cards explicitly
908 * in the bridge. The datasheets I have for both the
909 * ToPIC 97 and 100 both lists these ports. Without
910 * datasheets for the ToPIC95s, I can't tell if we need
911 * to do it there or not.
912 */
913 pcic_setb(&sc->slots[0], PCIC_TOPIC_FCR,
914 PCIC_FCR_3V_EN | PCIC_FCR_VS_EN);
915 }
916 }
917
918 static void
919 pcic_pci_cardbus_init(device_t dev)
920 {
921 struct pcic_softc *sc = device_get_softc(dev);
922 u_int16_t brgcntl;
923 int unit;
924
925 unit = device_get_unit(dev);
926
927 brgcntl = pci_read_config(dev, CB_PCI_BRIDGE_CTRL, 2);
928 brgcntl |= CB_BCR_WRITE_POST_EN | CB_BCR_MASTER_ABORT;
929 pci_write_config(dev, CB_PCI_BRIDGE_CTRL, brgcntl, 2);
930
931 /* Turn off legacy address */
932 pci_write_config(dev, CB_PCI_LEGACY16_IOADDR, 0, 2);
933
934 /*
935 * Write zeros into the remaining memory I/O windows. This
936 * seems to turn off the pci configuration of these things and
937 * make the cardbus bridge use the values for memory
938 * programmed into the pcic registers.
939 */
940 pci_write_config(dev, CB_PCI_MEMBASE0, 0, 4);
941 pci_write_config(dev, CB_PCI_MEMLIMIT0, 0, 4);
942 pci_write_config(dev, CB_PCI_MEMBASE1, 0, 4);
943 pci_write_config(dev, CB_PCI_MEMLIMIT1, 0, 4);
944 pci_write_config(dev, CB_PCI_IOBASE0, 0, 4);
945 pci_write_config(dev, CB_PCI_IOLIMIT0, 0, 4);
946 pci_write_config(dev, CB_PCI_IOBASE1, 0, 4);
947 pci_write_config(dev, CB_PCI_IOLIMIT1, 0, 4);
948
949 /*
950 * Tell the chip to do its routing thing.
951 */
952 sc->chip->func_intr_way(&sc->slots[0], sc->func_route);
953 sc->chip->csc_intr_way(&sc->slots[0], sc->csc_route);
954
955 return;
956 }
957
958 static const char *
959 pcic_pci_cardtype(u_int32_t stat)
960 {
961 if (stat & CB_SS_NOTCARD)
962 return ("unrecognized by bridge");
963 if ((stat & (CB_SS_16BIT | CB_SS_CB)) == (CB_SS_16BIT | CB_SS_CB))
964 return ("16-bit and 32-bit (can't happen)");
965 if (stat & CB_SS_16BIT)
966 return ("16-bit pccard");
967 if (stat & CB_SS_CB)
968 return ("32-bit cardbus");
969 return ("none (can't happen)");
970 }
971
972 /*
973 * Card insertion and removal code. The insertion events need to be
974 * debounced so that the noisy insertion/removal events don't result
975 * in the hardware being initialized many times, only to be torn down
976 * as well. This may also cause races with pccardd. Instead, we wait
977 * for the insertion signal to be stable for 0.5 seconds before we declare
978 * it to be a real insertion event. Removal is also debounced. We turn
979 * off interrupt servicing during the settling time to prevent infinite
980 * loops in the driver.
981 *
982 * Note: We only handle the card detect change events. We don't handle
983 * power events and status change events.
984 */
985 static void
986 pcic_cd_change(void *arg)
987 {
988 struct pcic_softc *sc = (struct pcic_softc *) arg;
989 struct pcic_slot *sp = &sc->slots[0];
990 u_int32_t stat;
991
992 sc->cd_pending = 0;
993 stat = bus_space_read_4(sp->bst, sp->bsh, CB_SOCKET_STATE);
994
995 /* Status changed while present; remove the card from the system. */
996 if (sc->cd_present) {
997 sc->cd_present = 0;
998 pccard_event(sp->slt, card_removed);
999 }
1000 /* Nothing to do if the debounced state is 'not present'. */
1001 if ((stat & CB_SS_CD) != 0)
1002 return;
1003
1004 sc->cd_present = 1;
1005 if (bootverbose && (stat & CB_SS_BADVCC) != 0)
1006 device_printf(sc->dev, "BAD Vcc request: 0x%x\n", stat);
1007 if ((stat & CB_SS_16BIT) == 0)
1008 device_printf(sp->sc->dev, "Card type %s is unsupported\n",
1009 pcic_pci_cardtype(stat));
1010 else
1011 pccard_event(sp->slt, card_inserted);
1012 }
1013
1014 static void
1015 pcic_pci_intr(void *arg)
1016 {
1017 struct pcic_softc *sc = (struct pcic_softc *) arg;
1018 struct pcic_slot *sp = &sc->slots[0];
1019 u_int32_t event;
1020
1021 event = bus_space_read_4(sp->bst, sp->bsh, CB_SOCKET_EVENT);
1022 if (event != 0) {
1023 if (bootverbose)
1024 device_printf(sc->dev, "Event mask 0x%x\n", event);
1025
1026 /*
1027 * Treat all card-detect signal transitions the same way
1028 * since we can't reliably tell if this is an insert or a
1029 * remove event. Stop the card from getting interrupts and
1030 * defer the insert/remove event until the CB_SOCKET_STATE
1031 * signals have had time to settle.
1032 */
1033 if ((event & CB_SE_CD) != 0) {
1034 if (sc->cd_pending) {
1035 untimeout(pcic_cd_change, arg, sc->cd_ch);
1036 sc->cd_pending = 0;
1037 }
1038 sc->cd_pending = 1;
1039 sc->cd_ch = timeout(pcic_cd_change, arg, hz/2);
1040 sc->func_intr = NULL;
1041 }
1042
1043 /* Ack the interrupt */
1044 bus_space_write_4(sp->bst, sp->bsh, 0, event);
1045 }
1046
1047 /*
1048 * Some TI chips also require us to read the old ExCA register for
1049 * card status change when we route CSC via PCI! So, we go ahead
1050 * and read it to clear the bits. Maybe we should check the status
1051 * ala the ISA interrupt handler, but those changes should be caught
1052 * in the CD change.
1053 *
1054 * We have to check it every interrupt because these bits can sometimes
1055 * show up indepentently of the CB_SOCKET_EVENT register above.
1056 */
1057 sp->getb(sp, PCIC_STAT_CHG);
1058 }
1059
1060 /*
1061 * Return the ID string for the controller if the vendor/product id
1062 * matches, NULL otherwise.
1063 */
1064 static int
1065 pcic_pci_probe(device_t dev)
1066 {
1067 u_int8_t subclass;
1068 u_int8_t progif;
1069 const char *desc;
1070 u_int32_t device_id;
1071 struct pcic_pci_table *itm;
1072 struct resource *res;
1073 int rid;
1074
1075 if (pcic_ignore_pci)
1076 return (ENXIO);
1077 device_id = pci_get_devid(dev);
1078 desc = NULL;
1079 itm = pcic_pci_lookup(device_id, &pcic_pci_devs[0]);
1080 if (pcic_ignore_function_1 && pci_get_function(dev) == 1) {
1081 if (itm != NULL)
1082 PRVERB((dev, "Ignoring function 1\n"));
1083 return (ENXIO);
1084 }
1085 if (itm != NULL)
1086 desc = itm->descr;
1087 if (desc == NULL && pci_get_class(dev) == PCIC_BRIDGE) {
1088 subclass = pci_get_subclass(dev);
1089 progif = pci_get_progif(dev);
1090 if (subclass == PCIS_BRIDGE_PCMCIA && progif == 0)
1091 desc = "Generic PCI-PCMCIA Bridge";
1092 if (subclass == PCIS_BRIDGE_CARDBUS && progif == 0)
1093 desc = "YENTA PCI-CardBus Bridge";
1094 if (bootverbose && desc)
1095 printf("Found unknown %s devid 0x%x\n", desc, device_id);
1096 }
1097 if (desc == NULL)
1098 return (ENXIO);
1099 device_set_desc(dev, desc);
1100
1101 /*
1102 * Take us out of power down mode, if necessary. It also
1103 * appears that even reading the power register is enough on
1104 * some systems to cause correct behavior.
1105 */
1106 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
1107 /* Reset the power state. */
1108 device_printf(dev, "chip is in D%d power mode "
1109 "-- setting to D0\n", pci_get_powerstate(dev));
1110 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
1111 }
1112
1113 /*
1114 * Allocated/deallocate interrupt. This forces the PCI BIOS or
1115 * other MD method to route the interrupts to this card.
1116 * This so we get the interrupt number in the probe message.
1117 * We only need to route interrupts when we're doing pci
1118 * parallel interrupt routing.
1119 *
1120 * We use two different variables for the memory based and I/O
1121 * based cards, so the check here is a little more complex than
1122 * one would otherwise hope.
1123 *
1124 * XXX The bus code for PCI really should do this for us.
1125 */
1126 if ((pcic_intr_path == pcic_iw_pci &&
1127 device_id != PCIC_ID_CLPD6729) ||
1128 (pcic_pd6729_intr_path == pcic_iw_pci &&
1129 device_id == PCIC_ID_CLPD6729)) {
1130 rid = 0;
1131 #ifdef __i386__
1132 /*
1133 * IRQ 0 is invalid on x86, but not other platforms.
1134 * If we have irq 0, then write 255 to force a new, non-
1135 * bogus one to be assigned. I think that in -current
1136 * the code in this ifdef may be obsolete with the new
1137 * invalid mapping that we're doing in the pci layer -- imp
1138 */
1139 if (pci_get_irq(dev) == 0) {
1140 pci_set_irq(dev, 255);
1141 pci_write_config(dev, PCIR_INTLINE, 255, 1);
1142 }
1143 #endif
1144 res = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1,
1145 RF_ACTIVE);
1146 if (res)
1147 bus_release_resource(dev, SYS_RES_IRQ, rid, res);
1148 }
1149
1150 return (0);
1151 }
1152
1153 static void
1154 pcic_pci_shutdown(device_t dev)
1155 {
1156 /*
1157 * More reports of things working w/o this code than with it.
1158 */
1159 #if 0
1160 struct pcic_softc *sc;
1161 struct pcic_slot *sp;
1162
1163 sc = (struct pcic_softc *) device_get_softc(dev);
1164 sp = &sc->slots[0];
1165
1166 /*
1167 * Turn off the power to the slot in an attempt to
1168 * keep the system from hanging on reboot. We also turn off
1169 * card interrupts in an attempt to control interrupt storms.
1170 * on some (all?) this has the effect of also turning off
1171 * card status change interrupts. A side effect of writing 0
1172 * to INT_GEN is that the card is placed into "reset" mode
1173 * where nothing happens until it is taken out of "reset"
1174 * mode.
1175 *
1176 * Also, turn off the generation of status interrupts too.
1177 */
1178 sp->putb(sp, PCIC_INT_GEN, 0);
1179 sp->putb(sp, PCIC_STAT_INT, 0);
1180 sp->putb(sp, PCIC_POWER, 0);
1181 DELAY(4000);
1182
1183 /*
1184 * Writing to INT_GEN can cause an interrupt, so we blindly
1185 * ack all possible interrupts here. Reading the stat change
1186 * shouldn't be necessary, but some TI chipsets need it in the
1187 * normal course of operations, so we do it here too. We can't
1188 * lose any interrupts after this point, so go ahead and ack
1189 * everything. The bits in INT_GEN clear upon reading them.
1190 * We also set the interrupt mask to 0, in an effort to avoid
1191 * getting further interrupts.
1192 */
1193 bus_space_write_4(sp->bst, sp->bsh, CB_SOCKET_MASK, 0);
1194 bus_space_write_4(sp->bst, sp->bsh, CB_SOCKET_EVENT, 0xffffffff);
1195 sp->getb(sp, PCIC_STAT_CHG);
1196 #endif
1197 }
1198
1199 /*
1200 * Print out the config space
1201 */
1202 static void
1203 pcic_pci_print_config(device_t dev)
1204 {
1205 int i;
1206
1207 device_printf(dev, "PCI Configuration space:");
1208 for (i = 0; i < 256; i += 4) {
1209 if (i % 16 == 0)
1210 printf("\n 0x%02x: ", i);
1211 printf("0x%08x ", pci_read_config(dev, i, 4));
1212 }
1213 printf("\n");
1214 }
1215
1216 /*
1217 * Generic pci interrupt attach routine. It tries to understand all parts,
1218 * and do sane things for those parts it does not understand.
1219 */
1220 static int
1221 pcic_pci_attach(device_t dev)
1222 {
1223 u_int32_t device_id = pci_get_devid(dev);
1224 u_long command;
1225 struct pcic_slot *sp;
1226 struct pcic_softc *sc;
1227 u_int32_t sockbase;
1228 u_int32_t stat;
1229 struct pcic_pci_table *itm;
1230 int rid;
1231 int i;
1232 struct resource *r = NULL;
1233 int error;
1234 u_long irq = 0;
1235 driver_intr_t *intr = NULL;
1236
1237 /*
1238 * In sys/pci/pcireg.h, PCIR_COMMAND must be separated
1239 * PCI_COMMAND_REG(0x04) and PCI_STATUS_REG(0x06).
1240 * Takeshi Shibagaki(shiba@jp.freebsd.org).
1241 */
1242 command = pci_read_config(dev, PCIR_COMMAND, 4);
1243 command |= PCIM_CMD_PORTEN | PCIM_CMD_MEMEN;
1244 pci_write_config(dev, PCIR_COMMAND, command, 4);
1245
1246 sc = (struct pcic_softc *) device_get_softc(dev);
1247 sp = &sc->slots[0];
1248 sp->sc = sc;
1249 sockbase = pci_read_config(dev, 0x10, 4);
1250 if (sockbase & 0x1) {
1251 sc->iorid = CB_PCI_SOCKET_BASE;
1252 sc->iores = bus_alloc_resource(dev, SYS_RES_IOPORT,
1253 &sc->iorid, 0, ~0, 1, RF_ACTIVE | RF_SHAREABLE);
1254 if (sc->iores == NULL)
1255 return (ENOMEM);
1256
1257 sc->flags = PCIC_PD_POWER;
1258 itm = pcic_pci_lookup(device_id, &pcic_pci_devs[0]);
1259 for (i = 0; i < 2; i++) {
1260 sp[i].bst = rman_get_bustag(sc->iores);
1261 sp[i].bsh = rman_get_bushandle(sc->iores);
1262 sp[i].sc = sc;
1263 sp[i].revision = 0;
1264 sp[i].getb = pcic_getb_io;
1265 sp[i].putb = pcic_putb_io;
1266 sp[i].offset = i * PCIC_SLOT_SIZE;
1267 sp[i].controller = itm ? itm->type : PCIC_PD6729;
1268 if ((sp[i].getb(&sp[i], PCIC_ID_REV) & 0xc0) == 0x80)
1269 sp[i].slt = (struct slot *) 1;
1270 }
1271 sc->csc_route = sc->func_route = pcic_pd6729_intr_path;
1272 if (itm)
1273 sc->flags = itm->flags;
1274 /*
1275 * We have to use the ISA interrupt routine for status
1276 * changes since we don't have any "yenta" pci registers.
1277 * We have to do this even when we're using pci type
1278 * interrupts because on these cards the interrupts are
1279 * cleared in the same way that the ISA cards clear them.
1280 */
1281 intr = pcic_isa_intr;
1282 } else {
1283 sc->memrid = CB_PCI_SOCKET_BASE;
1284 sc->memres = bus_alloc_resource(dev, SYS_RES_MEMORY,
1285 &sc->memrid, 0, ~0, 1, RF_ACTIVE);
1286 if (sc->memres == NULL && pcic_pci_get_memory(dev) != 0)
1287 return (ENOMEM);
1288 sp->getb = pcic_pci_getb2;
1289 sp->putb = pcic_pci_putb2;
1290 sp->offset = CB_EXCA_OFFSET;
1291 sp->bst = rman_get_bustag(sc->memres);
1292 sp->bsh = rman_get_bushandle(sc->memres);
1293 itm = pcic_pci_lookup(device_id, &pcic_pci_devs[0]);
1294 if (itm != NULL) {
1295 sp->controller = itm->type;
1296 sp->revision = 0;
1297 sc->flags = itm->flags;
1298 } else {
1299 /* By default, assume we're a D step compatible */
1300 sp->controller = PCIC_I82365SL_DF;
1301 sp->revision = 0;
1302 sc->flags = PCIC_CARDBUS_POWER;
1303 }
1304 /* All memory mapped cardbus bridges have these registers */
1305 sc->flags |= PCIC_YENTA_HIGH_MEMORY;
1306 sp->slt = (struct slot *) 1;
1307 sc->csc_route = pcic_intr_path;
1308 sc->func_route = pcic_intr_path;
1309 stat = bus_space_read_4(sp->bst, sp->bsh, CB_SOCKET_STATE);
1310 sc->cd_present = (stat & CB_SS_CD) == 0;
1311 }
1312 sc->dev = dev;
1313 if (itm)
1314 sc->chip = itm->chip;
1315 else
1316 sc->chip = &pcic_pci_generic_chip;
1317
1318 if (sc->csc_route == pcic_iw_pci) {
1319 rid = 0;
1320 r = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1,
1321 RF_ACTIVE | RF_SHAREABLE);
1322 if (r == NULL) {
1323 sc->csc_route = pcic_iw_isa;
1324 sc->func_route = pcic_iw_isa;
1325 device_printf(dev,
1326 "No PCI interrupt routed, trying ISA.\n");
1327 } else {
1328 if (intr == NULL)
1329 intr = pcic_pci_intr;
1330 irq = rman_get_start(r);
1331 }
1332 }
1333 if (sc->csc_route == pcic_iw_isa) {
1334 rid = 0;
1335 irq = pcic_override_irq;
1336 if (irq != 0) {
1337 r = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, irq,
1338 irq, 1, RF_ACTIVE);
1339 if (r == NULL) {
1340 device_printf(dev,
1341 "Can't route ISA CSC interrupt.\n");
1342 pcic_dealloc(dev);
1343 return (ENXIO);
1344 }
1345 device_printf(dev,
1346 "Management interrupt on ISA IRQ %ld\n", irq);
1347 if (intr == NULL)
1348 intr = pcic_isa_intr;
1349 } else {
1350 sc->slot_poll = pcic_timeout;
1351 sc->timeout_ch = timeout(sc->slot_poll, sc, hz/2);
1352 device_printf(dev, "Polling mode\n");
1353 intr = NULL;
1354 }
1355 }
1356
1357 /*
1358 * Initialize AFTER we figure out what kind of interrupt we're
1359 * going to be using, if any.
1360 */
1361 if (!sc->chip)
1362 panic("Bug: sc->chip not set!\n");
1363 sc->chip->init(dev);
1364
1365 /*
1366 * Now install the interrupt handler, if necessary.
1367 */
1368 sc->irqrid = rid;
1369 sc->irqres = r;
1370 sc->irq = irq;
1371 if (intr) {
1372 error = bus_setup_intr(dev, r, INTR_TYPE_AV, intr, sc, &sc->ih);
1373 if (error) {
1374 pcic_dealloc(dev);
1375 return (error);
1376 }
1377 }
1378 if (bootverbose)
1379 pcic_pci_print_config(dev);
1380 return (pcic_attach(dev));
1381 }
1382
1383 static int
1384 pcic_pci_detach(device_t dev)
1385 {
1386 return (EBUSY); /* Can't detach this device */
1387 }
1388
1389 /*
1390 * The PCI bus should do this for us. However, it doesn't quite yet, so
1391 * we cope by doing it ourselves. If it ever does, this code can go quietly
1392 * into that good night.
1393 */
1394 static int
1395 pcic_pci_get_memory(device_t dev)
1396 {
1397 struct pcic_softc *sc;
1398 u_int32_t sockbase;
1399
1400 sc = (struct pcic_softc *) device_get_softc(dev);
1401 sockbase = pci_read_config(dev, sc->memrid, 4);
1402 if (sockbase >= 0x100000 && sockbase < 0xfffffff0) {
1403 device_printf(dev, "Could not map register memory 0x%x\n",
1404 sockbase);
1405 return (ENOMEM);
1406 }
1407 pci_write_config(dev, sc->memrid, 0xffffffff, 4);
1408 sockbase = pci_read_config(dev, sc->memrid, 4);
1409 sockbase = (sockbase & 0xfffffff0) & -(sockbase & 0xfffffff0);
1410 #define CARDBUS_SYS_RES_MEMORY_START 0x88000000
1411 #define CARDBUS_SYS_RES_MEMORY_END 0xFFFFFFFF
1412 sc->memres = bus_generic_alloc_resource(device_get_parent(dev),
1413 dev, SYS_RES_MEMORY, &sc->memrid,
1414 CARDBUS_SYS_RES_MEMORY_START, CARDBUS_SYS_RES_MEMORY_END,
1415 sockbase, RF_ACTIVE | rman_make_alignment_flags(sockbase));
1416 if (sc->memres == NULL) {
1417 device_printf(dev, "Could not grab register memory\n");
1418 return (ENOMEM);
1419 }
1420 sockbase = rman_get_start(sc->memres);
1421 pci_write_config(dev, sc->memrid, sockbase, 4);
1422 device_printf(dev, "PCI Memory allocated: 0x%08x\n", sockbase);
1423 return (0);
1424 }
1425
1426 static int
1427 pcic_pci_gen_mapirq(struct pcic_slot *sp, int irq)
1428 {
1429 /*
1430 * If we're doing ISA interrupt routing, then just go to the
1431 * generic ISA routine. Also, irq 0 means turn off the interrupts
1432 * at the bridge.
1433 */
1434 if (sp->sc->func_route == pcic_iw_isa || irq == 0)
1435 return (pcic_isa_mapirq(sp, irq));
1436
1437 /*
1438 * Ohterwise we're doing PCI interrupts. For those cardbus bridges
1439 * that follow yenta (and the one pcmcia bridge that does), we don't
1440 * do a thing to get the IRQ mapped into the system. However,
1441 * for other controllers that are PCI, but not yetna compliant, we
1442 * need to do some special mapping.
1443 *
1444 * XXX Maybe we shouldn't assume INTA#, but rather as the function
1445 * XXX what Intline to use.
1446 */
1447 if (sp->controller == PCIC_PD6729) {
1448 /*
1449 * INTA - 3
1450 * INTB - 4
1451 * INTC - 5
1452 * INTD - 7
1453 */
1454 sp->putb(sp, PCIC_INT_GEN, /* Assume INTA# */
1455 (sp->getb(sp, PCIC_INT_GEN) & 0xF0) | 3);
1456 return (0);
1457 }
1458 return (0);
1459 }
1460
1461 static void
1462 pcic_pci_func_intr(void *arg)
1463 {
1464 struct pcic_softc *sc = (struct pcic_softc *) arg;
1465 struct pcic_slot *sp = &sc->slots[0];
1466 u_int32_t stat;
1467 int doit = 0;
1468
1469 /*
1470 * The 6729 controller is a weird one, and we have to use
1471 * the ISA registers to check to see if the card is there.
1472 * Otherwise we look at the PCI state register to find out
1473 * if the card is there.
1474 */
1475 if (sp->controller == PCIC_PD6729) {
1476 if ((sp->getb(sp, PCIC_STATUS) & PCIC_CD) == PCIC_CD)
1477 doit = 1;
1478 }
1479 else {
1480 stat = bus_space_read_4(sp->bst, sp->bsh, CB_SOCKET_STATE);
1481 if ((stat & CB_SS_CD) == 0 && sc->func_intr != 0)
1482 doit = 1;
1483 }
1484 if (doit && sc->func_intr != NULL)
1485 sc->func_intr(sc->func_arg);
1486 }
1487
1488 static int
1489 pcic_pci_setup_intr(device_t dev, device_t child, struct resource *irq,
1490 int flags, driver_intr_t *intr, void *arg, void **cookiep)
1491 {
1492 struct pcic_softc *sc = device_get_softc(dev);
1493 struct pcic_slot *sp = &sc->slots[0];
1494 int err;
1495
1496 if (sc->func_route == pcic_iw_isa)
1497 return(pcic_setup_intr(dev, child, irq, flags, intr, arg,
1498 cookiep));
1499
1500 #if __FreeBSD_version >= 500000
1501 if ((flags & INTR_FAST) != 0)
1502 #else
1503 if ((flags & INTR_TYPE_FAST) != 0)
1504 #endif
1505 return (EINVAL);
1506 if (sc->func_intr != NULL) {
1507 device_printf(child, "Can't establish another ISR\n");
1508 return (EINVAL);
1509 }
1510
1511 err = bus_generic_setup_intr(dev, child, irq, flags,
1512 pcic_pci_func_intr, sc, cookiep);
1513 if (err != 0)
1514 return (err);
1515 sc->chip->map_irq(sp, rman_get_start(irq));
1516 sc->func_intr = intr;
1517 sc->func_arg = arg;
1518 return (0);
1519 }
1520
1521 static int
1522 pcic_pci_teardown_intr(device_t dev, device_t child, struct resource *irq,
1523 void *cookie)
1524 {
1525 struct pcic_softc *sc = device_get_softc(dev);
1526
1527 if (sc->func_route == pcic_iw_isa)
1528 return (pcic_teardown_intr(dev, child, irq, cookie));
1529 sc->func_intr = NULL;
1530 return (bus_generic_teardown_intr(dev, child, irq, cookie));
1531 }
1532
1533 static int
1534 pcic_pci_resume(device_t dev)
1535 {
1536 struct pcic_softc *sc = device_get_softc(dev);
1537
1538 /*
1539 * Some BIOSes will not save the BARs for the pci chips, so we
1540 * must do it ourselves. If the BAR is reset to 0 for an I/O
1541 * device, it will read back as 0x1, so no explicit test for
1542 * memory devices are needed.
1543 *
1544 * Note: The PCI bus code should do this automatically for us on
1545 * suspend/resume, but until it does, we have to cope.
1546 */
1547 if (pci_read_config(dev, CB_PCI_SOCKET_BASE, 4) == 0)
1548 pci_write_config(dev, CB_PCI_SOCKET_BASE,
1549 rman_get_start(sc->memres), 4);
1550 return (bus_generic_resume(dev));
1551 }
1552
1553 static device_method_t pcic_pci_methods[] = {
1554 /* Device interface */
1555 DEVMETHOD(device_probe, pcic_pci_probe),
1556 DEVMETHOD(device_attach, pcic_pci_attach),
1557 DEVMETHOD(device_detach, pcic_pci_detach),
1558 DEVMETHOD(device_suspend, bus_generic_suspend),
1559 DEVMETHOD(device_resume, pcic_pci_resume),
1560 DEVMETHOD(device_shutdown, pcic_pci_shutdown),
1561
1562 /* Bus interface */
1563 DEVMETHOD(bus_print_child, bus_generic_print_child),
1564 DEVMETHOD(bus_alloc_resource, pcic_alloc_resource),
1565 DEVMETHOD(bus_release_resource, bus_generic_release_resource),
1566 DEVMETHOD(bus_activate_resource, pcic_activate_resource),
1567 DEVMETHOD(bus_deactivate_resource, pcic_deactivate_resource),
1568 DEVMETHOD(bus_setup_intr, pcic_pci_setup_intr),
1569 DEVMETHOD(bus_teardown_intr, pcic_pci_teardown_intr),
1570
1571 /* Card interface */
1572 DEVMETHOD(card_set_res_flags, pcic_set_res_flags),
1573 DEVMETHOD(card_get_res_flags, pcic_get_res_flags),
1574 DEVMETHOD(card_set_memory_offset, pcic_set_memory_offset),
1575 DEVMETHOD(card_get_memory_offset, pcic_get_memory_offset),
1576
1577 {0, 0}
1578 };
1579
1580 static driver_t pcic_pci_driver = {
1581 "pcic",
1582 pcic_pci_methods,
1583 sizeof(struct pcic_softc)
1584 };
1585
1586 DRIVER_MODULE(pcic, pci, pcic_pci_driver, pcic_devclass, 0, 0);
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