The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


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FreeBSD/Linux Kernel Cross Reference
sys/pccard/pcic_pci.h

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    1 /*-
    2  * Copyright (c) 2001 M. Warner Losh. All rights reserved.
    3  * Copyright (c) 1997 Ted Faber. All rights reserved.
    4  *
    5  * Redistribution and use in source and binary forms, with or without
    6  * modification, are permitted provided that the following conditions
    7  * are met:
    8  *
    9  * 1. Redistributions of source code must retain the above copyright
   10  *    notice immediately at the beginning of the file, without modification,
   11  *    this list of conditions, and the following disclaimer.
   12  * 2. Redistributions in binary form must reproduce the above copyright
   13  *    notice, this list of conditions and the following disclaimer in the
   14  *    documentation and/or other materials provided with the distribution.
   15  * 3. Absolutely no warranty of function or purpose is made by the author
   16  *    Ted Faber.
   17  *
   18  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
   19  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
   20  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
   21  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
   22  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
   23  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
   24  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
   25  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
   26  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
   27  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
   28  *
   29  * $FreeBSD: src/sys/pccard/pcic_pci.h,v 1.36.8.1 2005/01/31 23:26:49 imp Exp $
   30  */
   31 
   32 /* Share the devid database with NEWCARD */
   33 #include <dev/pccbb/pccbbdevid.h>
   34 
   35 /* CL-PD683x CardBus defines */
   36 #define CLPD6833_CFG_MISC_1             0x98
   37 
   38 /* Configuration constants */
   39 #define CLPD6832_BCR_MGMT_IRQ_ENA       0x0800
   40 #define CLPD6833_CM1_MGMT_EXCA_ENA      0x0001  /* Set ExCA, Clr PCI */
   41 
   42 /* End of CL-PD6832 defines */
   43 /* Texas Instruments PCI-1130/1131 CardBus Controller */
   44 #define TI113X_PCI_SYSTEM_CONTROL       0x80    /* System Control */
   45 #define TI12XX_PCI_MULTIMEDIA_CONTROL   0x84    /* Zoom Video */
   46 #define TI12XX_PCI_MFUNC                0x8c    /* multifunction pins */
   47 #define TI113X_PCI_RETRY_STATUS         0x90    /* Retry Status */
   48 #define TI113X_PCI_CARD_CONTROL         0x91    /* Card Control */
   49 #define TI113X_PCI_DEVICE_CONTROL       0x92    /* Device Control */
   50 #define TI113X_PCI_BUFFER_CONTROL       0x93    /* Buffer Control */
   51 #define TI12XX_PCI_DIAGNOSTIC           0x93    /* Diagnostic register */
   52 #define TI113X_PCI_SOCKET_DMA0          0x94    /* Socket DMA Register 0 */
   53 #define TI113X_PCI_SOCKET_DMA1          0x98    /* Socket DMA Register 1 */
   54 
   55 /* Card control register (TI113X_SYSTEM_CONTROL == 0x80) */
   56 #define TI113X_SYSCNTL_INTRTIE          0x20000000u
   57 #define TI12XX_SYSCNTL_PCI_CLOCK        0x08000000u
   58 #define TI113X_SYSCNTL_SMIENB           0x00800000u
   59 #define TI113X_SYSCNTL_VCC_PROTECT      0x00200000u
   60 #define TI113X_SYSCNTL_CLKRUN_SEL       0x00000080u
   61 #define TI113X_SYSCNTL_PWRSAVINGS       0x00000040u
   62 #define TI113X_SYSCNTL_KEEP_CLK         0x00000002u
   63 #define TI113X_SYSCNTL_CLKRUN_ENA       0x00000001u
   64 
   65 /* MFUNC register (TI12XX_MFUNC == 0x8c) */
   66 #define TI12XX_MFUNC_PIN0               0x0000000fu
   67 #define   TI12XX_MFUNC_PIN0_INTA        0x2
   68 #define TI12XX_MFUNC_PIN1               0x000000f0u
   69 #define   TI12XX_MFUNC_PIN1_INTB        0x20
   70 #define TI12XX_MFUNC_PIN2               0x00000f00u
   71 #define TI12XX_MFUNC_PIN3               0x0000f000u
   72 #define TI12XX_MFUNC_PIN4               0x000f0000u
   73 #define TI12XX_MFUNC_PIN5               0x00f00000u
   74 #define TI12XX_MFUNC_PIN6               0x0f000000u
   75 
   76 /* Card control register (TI113X_CARD_CONTROL == 0x91) */
   77 #define TI113X_CARDCNTL_RING_ENA        0x80u
   78 #define TI113X_CARDCNTL_ZOOM_VIDEO      0x40u
   79 #define TI113X_CARDCNTL_PCI_IRQ_ENA     0x20u
   80 #define TI113X_CARDCNTL_PCI_IREQ        0x10u
   81 #define TI113X_CARDCNTL_PCI_CSC         0x08u
   82 #define TI113X_CARDCNTL_MASK            (TI113X_CARDCNTL_PCI_IRQ_ENA | TI113X_CARDCNTL_PCI_IREQ | TI113X_CARDCNTL_PCI_CSC)
   83 #define TI113X_FUNC0_VALID              TI113X_CARDCNTL_MASK
   84 #define TI113X_FUNC1_VALID              (TI113X_CARDCNTL_PCI_IREQ | TI113X_CARDCNTL_PCI_CSC)
   85 /* Reserved bit                         0x04u */
   86 #define TI113X_CARDCNTL_SPKR_ENA        0x02u
   87 #define TI113X_CARDCNTL_INT             0x01u
   88 
   89 /* Device control register (TI113X_DEVICE_CONTROL == 0x92) */
   90 #define TI113X_DEVCNTL_5V_SOCKET        0x40u
   91 #define TI113X_DEVCNTL_3V_SOCKET        0x20u
   92 #define TI113X_DEVCNTL_INTR_MASK        0x06u
   93 #define TI113X_DEVCNTL_INTR_NONE        0x00u
   94 #define TI113X_DEVCNTL_INTR_ISA         0x02u
   95 #define TI113X_DEVCNTL_INTR_SERIAL      0x04u
   96 /* TI12XX specific code */
   97 #define TI12XX_DEVCNTL_INTR_ALLSERIAL   0x06u
   98 
   99 /* Diagnostic register (misnamed) TI12XX_PCI_DIAGNOSTIC == 0x93 */
  100 #define TI12XX_DIAG_CSC_INTR            0x20    /* see datasheet */
  101 
  102 /* Texas Instruments PCI-1130/1131 CardBus Controller */
  103 #define TI113X_ExCA_IO_OFFSET0          0x36    /* Offset of I/O window */
  104 #define TI113X_ExCA_IO_OFFSET1          0x38    /* Offset of I/O window */
  105 #define TI113X_ExCA_MEM_WINDOW_PAGE     0x3C    /* Memory Window Page */
  106 
  107 /*
  108  * Ricoh R5C47[5678] parts have these registers.  Maybe the 46x also use
  109  * them, but I can't find out for sure without datasheets...
  110  */
  111 #define R5C47X_MISC_CONTROL_REGISTER_2  0xa0
  112 #define R5C47X_MCR2_CSC_TO_INTX_DISABLE 0x0010  /* Bit 7 */
  113 
  114 /*
  115  * Special resister definition for Toshiba ToPIC95/97
  116  * These values are borrowed from pcmcia-cs/Linux.
  117  */
  118 #define TOPIC_SOCKET_CTRL  0x90
  119 # define TOPIC_SOCKET_CTRL_SCR_IRQSEL 0x00000001 /* PCI intr */
  120 
  121 #define TOPIC_SLOT_CTRL    0xa0
  122 # define TOPIC_SLOT_CTRL_SLOTON       0x00000080
  123 # define TOPIC_SLOT_CTRL_SLOTEN       0x00000040
  124 # define TOPIC_SLOT_CTRL_ID_LOCK      0x00000020
  125 # define TOPIC_SLOT_CTRL_ID_WP        0x00000010
  126 # define TOPIC_SLOT_CTRL_PORT_MASK    0x0000000c
  127 # define TOPIC_SLOT_CTRL_PORT_SHIFT            2
  128 # define TOPIC_SLOT_CTRL_OSF_MASK     0x00000003
  129 # define TOPIC_SLOT_CTRL_OSF_SHIFT             0
  130 
  131 # define TOPIC_SLOT_CTRL_INTB         0x00002000
  132 # define TOPIC_SLOT_CTRL_INTA         0x00001000
  133 # define TOPIC_SLOT_CTRL_INT_MASK     0x00003000
  134 # define TOPIC_SLOT_CTRL_CLOCK_MASK   0x00000c00
  135 # define TOPIC_SLOT_CTRL_CLOCK_2      0x00000800 /* PCI Clock/2 */
  136 # define TOPIC_SLOT_CTRL_CLOCK_1      0x00000400 /* PCI Clock */
  137 # define TOPIC_SLOT_CTRL_CLOCK_0      0x00000000 /* no clock */
  138 # define TOPIC97_SLOT_CTRL_STSIRQP    0x00000400 /* status change intr pulse */
  139 # define TOPIC97_SLOT_CTRL_IRQP       0x00000200 /* function intr pulse */
  140 # define TOPIC97_SLOT_CTRL_PCIINT     0x00000100 /* intr routing to PCI INT */
  141 
  142 # define TOPIC_SLOT_CTRL_CARDBUS      0x80000000
  143 # define TOPIC_SLOT_CTRL_VS1          0x04000000
  144 # define TOPIC_SLOT_CTRL_VS2          0x02000000
  145 # define TOPIC_SLOT_CTRL_SWDETECT     0x01000000
  146 
  147 #define TOPIC_REG_CTRL     0x00a4
  148 # define TOPIC_REG_CTRL_RESUME_RESET  0x80000000
  149 # define TOPIC_REG_CTRL_REMOVE_RESET  0x40000000
  150 # define TOPIC97_REG_CTRL_CLKRUN_ENA  0x20000000
  151 # define TOPIC97_REG_CTRL_TESTMODE    0x10000000
  152 # define TOPIC97_REG_CTRL_IOPLUP      0x08000000
  153 # define TOPIC_REG_CTRL_BUFOFF_PWROFF 0x02000000
  154 # define TOPIC_REG_CTRL_BUFOFF_SIGOFF 0x01000000
  155 # define TOPIC97_REG_CTRL_CB_DEV_MASK 0x0000f800
  156 # define TOPIC97_REG_CTRL_CB_DEV_SHIFT 11
  157 # define TOPIC97_REG_CTRL_RI_DISABLE  0x00000004
  158 # define TOPIC97_REG_CTRL_CAUDIO_OFF  0x00000002
  159 # define TOPIC_REG_CTRL_CAUDIO_INVERT 0x00000001
  160 
  161 /* For Bridge Control register (CB_PCI_BRIDGE_CTRL) */
  162 #define CB_BCR_MASTER_ABORT     0x0020
  163 #define CB_BCR_CB_RESET         0x0040
  164 #define CB_BCR_INT_EXCA         0x0080
  165 #define CB_BCR_WRITE_POST_EN    0x0400
  166   /* additional bits for Ricoh's cardbus products */
  167 #define CB_BCR_RL_3E0_EN        0x0800
  168 #define CB_BCR_RL_3E2_EN        0x1000
  169 
  170 /* PCI Configuration Registers (common) */
  171 #define CB_PCI_VENDOR_ID        0x00    /* vendor ID */
  172 #define CB_PCI_DEVICE_ID        0x02    /* device ID */
  173 #define CB_PCI_COMMAND          0x04    /* PCI command */
  174 #define CB_PCI_STATUS           0x06    /* PCI status */
  175 #define CB_PCI_REVISION_ID      0x08    /* PCI revision ID */
  176 #define CB_PCI_CLASS            0x09    /* PCI class code */
  177 #define CB_PCI_CACHE_LINE_SIZE  0x0c    /* Cache line size */
  178 #define CB_PCI_LATENCY          0x0d    /* PCI latency timer */
  179 #define CB_PCI_HEADER_TYPE      0x0e    /* PCI header type */
  180 #define CB_PCI_BIST             0x0f    /* Built-in self test */
  181 #define CB_PCI_SOCKET_BASE      0x10    /* Socket/ExCA base address reg. */
  182 #define CB_PCI_CB_STATUS        0x16    /* CardBus Status */
  183 #define CB_PCI_PCI_BUS_NUM      0x18    /* PCI bus number */
  184 #define CB_PCI_CB_BUS_NUM       0x19    /* CardBus bus number */
  185 #define CB_PCI_CB_SUB_BUS_NUM   0x1A    /* Subordinate CardBus bus number */
  186 #define CB_PCI_CB_LATENCY       0x1A    /* CardBus latency timer */
  187 #define CB_PCI_MEMBASE0         0x1C    /* Memory base register 0 */
  188 #define CB_PCI_MEMLIMIT0        0x20    /* Memory limit register 0 */
  189 #define CB_PCI_MEMBASE1         0x24    /* Memory base register 1 */
  190 #define CB_PCI_MEMLIMIT1        0x28    /* Memory limit register 1 */
  191 #define CB_PCI_IOBASE0          0x2C    /* I/O base register 0 */
  192 #define CB_PCI_IOLIMIT0         0x30    /* I/O limit register 0 */
  193 #define CB_PCI_IOBASE1          0x34    /* I/O base register 1 */
  194 #define CB_PCI_IOLIMIT1         0x38    /* I/O limit register 1 */
  195 #define CB_PCI_INT_LINE         0x3C    /* Interrupt Line */
  196 #define CB_PCI_INT_PIN          0x3D    /* Interrupt Pin */
  197 #define CB_PCI_BRIDGE_CTRL      0x3E    /* Bridge Control */
  198 #define CB_PCI_SUBSYS_VENDOR_ID 0x40    /* Subsystem Vendor ID */
  199 #define CB_PCI_SUBSYS_ID        0x42    /* Subsystem ID */
  200 #define CB_PCI_LEGACY16_IOADDR  0x44    /* Legacy 16bit I/O address */
  201 #define CB_PCI_LEGACY16_IOENABLE 0x01   /* Enable Legacy 16bit I/O address */
  202 
  203 /* PCI Memory register offsets for YENTA devices */
  204 #define CB_SOCKET_EVENT         0x00
  205 #define CB_SOCKET_MASK          0x04
  206 #define CB_SOCKET_STATE         0x08
  207 #define CB_SOCKET_FORCE         0x0c
  208 #define CB_SOCKET_POWER         0x10
  209 #define CB_EXCA_OFFSET          0x800   /* Offset for ExCA registers */
  210 
  211 #define CB_SE_CD                0x6     /* Socket Event Card detect */
  212 #define CB_SE_POWER             0x8
  213 
  214 #define CB_SM_CD                0x6     /* Socket MASK Card detect */
  215 #define CB_SM_POWER             0x8
  216 
  217 /* Socket State Register */
  218 #define CB_SS_CARDSTS           0x00000001 /* Card Status Change */
  219 #define CB_SS_CD1               0x00000002 /* Card Detect 1 */
  220 #define CB_SS_CD2               0x00000004 /* Card Detect 2 */
  221 #define CB_SS_CD                0x00000006 /* Card Detect all */
  222 #define CB_SS_PWRCYCLE          0x00000008 /* Power Cycle */
  223 #define CB_SS_16BIT             0x00000010 /* 16-bit Card */
  224 #define CB_SS_CB                0x00000020 /* Cardbus Card */
  225 #define CB_SS_IREQ              0x00000040 /* Ready */
  226 #define CB_SS_NOTCARD           0x00000080 /* Unrecognized Card */
  227 #define CB_SS_DATALOST          0x00000100 /* Data Lost */
  228 #define CB_SS_BADVCC            0x00000200 /* Bad VccRequest */
  229 #define CB_SS_5VCARD            0x00000400 /* 5 V Card */
  230 #define CB_SS_3VCARD            0x00000800 /* 3.3 V Card */
  231 #define CB_SS_XVCARD            0x00001000 /* X.X V Card */
  232 #define CB_SS_YVCARD            0x00002000 /* Y.Y V Card */
  233 #define CB_SS_CARD_MASK         0x00003c00 /* *VCARD signal */
  234 #define CB_SS_5VSOCK            0x10000000 /* 5 V Socket */
  235 #define CB_SS_3VSOCK            0x20000000 /* 3.3 V Socket */
  236 #define CB_SS_XVSOCK            0x40000000 /* X.X V Socket */
  237 #define CB_SS_YVSOCK            0x80000000 /* Y.Y V Socket */
  238 
  239 /* Socket power register */
  240 #define CB_SP_CLKSTOP           0x80    /* Cardbus clock stop protocol */
  241 #define CB_SP_VCC_MASK          0x70
  242 #define CB_SP_VCC_0V            0x00
  243                                         /* 0x10 is reserved 12V in VPP */
  244 #define CB_SP_VCC_5V            0x20
  245 #define CB_SP_VCC_3V            0x30
  246 #define CB_SP_VCC_XV            0x40
  247 #define CB_SP_VCC_YV            0x50
  248                                         /* 0x60 and 0x70 are reserved */
  249 #define CB_SP_VPP_MASK          0x07
  250 #define CB_SP_VPP_0V            0x00
  251 #define CB_SP_VPP_12V           0x01
  252 #define CB_SP_VPP_5V            0x02
  253 #define CB_SP_VPP_3V            0x03
  254 #define CB_SP_VPP_XV            0x04
  255 #define CB_SP_VPP_YV            0x05
  256 
  257 /* Socket force register */
  258 #define CB_SF_INTCVS            (1 << 14)       /* Interregate CVS/CCD pins */
  259 #define CB_SF_5VCARD            (1 << 11)
  260 #define CB_SF_3VCARD            (1 << 10)
  261 #define CB_SF_BADVCC            (1 << 9)
  262 #define CB_SF_DATALOST          (1 << 8)
  263 #define CB_SF_NOTACARD          (1 << 7)
  264 #define CB_SF_CBCARD            (1 << 5)
  265 #define CB_SF_16CARD            (1 << 4)
  266 #define CB_SF_POWERCYCLE        (1 << 3)
  267 #define CB_SF_CCD2              (1 << 2)
  268 #define CB_SF_CCD1              (1 << 1)
  269 #define CB_SF_CSTCHG            (1 << 0)
  270                                         /* 0x6 and 0x7 are reserved */

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