FreeBSD/Linux Kernel Cross Reference
sys/pci/agp_amd.c
1 /*-
2 * Copyright (c) 2000 Doug Rabson
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 *
26 * $FreeBSD$
27 */
28
29 #include "opt_bus.h"
30 #include "opt_pci.h"
31
32 #include <sys/param.h>
33 #include <sys/systm.h>
34 #include <sys/malloc.h>
35 #include <sys/kernel.h>
36 #include <sys/bus.h>
37 #include <sys/lock.h>
38
39 #include <pci/pcivar.h>
40 #include <pci/pcireg.h>
41 #include <pci/agppriv.h>
42 #include <pci/agpreg.h>
43
44 #include <vm/vm.h>
45 #include <vm/vm_object.h>
46 #include <vm/pmap.h>
47 #include <machine/clock.h>
48 #include <machine/bus.h>
49 #include <machine/resource.h>
50 #include <sys/rman.h>
51
52 MALLOC_DECLARE(M_AGP);
53
54 #define READ2(off) bus_space_read_2(sc->bst, sc->bsh, off)
55 #define READ4(off) bus_space_read_4(sc->bst, sc->bsh, off)
56 #define WRITE2(off,v) bus_space_write_2(sc->bst, sc->bsh, off, v)
57 #define WRITE4(off,v) bus_space_write_4(sc->bst, sc->bsh, off, v)
58
59 struct agp_amd_gatt {
60 u_int32_t ag_entries;
61 u_int32_t *ag_virtual; /* virtual address of gatt */
62 vm_offset_t ag_physical;
63 u_int32_t *ag_vdir; /* virtual address of page dir */
64 vm_offset_t ag_pdir; /* physical address of page dir */
65 };
66
67 struct agp_amd_softc {
68 struct agp_softc agp;
69 struct resource *regs; /* memory mapped control registers */
70 bus_space_tag_t bst; /* bus_space tag */
71 bus_space_handle_t bsh; /* bus_space handle */
72 u_int32_t initial_aperture; /* aperture size at startup */
73 struct agp_amd_gatt *gatt;
74 };
75
76 static struct agp_amd_gatt *
77 agp_amd_alloc_gatt(device_t dev)
78 {
79 u_int32_t apsize = AGP_GET_APERTURE(dev);
80 u_int32_t entries = apsize >> AGP_PAGE_SHIFT;
81 struct agp_amd_gatt *gatt;
82 int i, npages, pdir_offset;
83
84 if (bootverbose)
85 device_printf(dev,
86 "allocating GATT for aperture of size %dM\n",
87 apsize / (1024*1024));
88
89 gatt = malloc(sizeof(struct agp_amd_gatt), M_AGP, M_NOWAIT);
90 if (!gatt)
91 return 0;
92
93 /*
94 * The AMD751 uses a page directory to map a non-contiguous
95 * gatt so we don't need to use contigmalloc.
96 * Malloc individual gatt pages and map them into the page
97 * directory.
98 */
99 gatt->ag_entries = entries;
100 gatt->ag_virtual = malloc(entries * sizeof(u_int32_t),
101 M_AGP, M_NOWAIT);
102 if (!gatt->ag_virtual) {
103 if (bootverbose)
104 device_printf(dev, "allocation failed\n");
105 free(gatt, M_AGP);
106 return 0;
107 }
108 bzero(gatt->ag_virtual, entries * sizeof(u_int32_t));
109
110 /*
111 * Allocate the page directory.
112 */
113 gatt->ag_vdir = malloc(AGP_PAGE_SIZE, M_AGP, M_NOWAIT);
114
115 if (!gatt->ag_vdir) {
116 if (bootverbose)
117 device_printf(dev,
118 "failed to allocate page directory\n");
119 free(gatt->ag_virtual, M_AGP);
120 free(gatt, M_AGP);
121 return 0;
122 }
123 bzero(gatt->ag_vdir, AGP_PAGE_SIZE);
124 gatt->ag_pdir = vtophys((vm_offset_t) gatt->ag_vdir);
125 if(bootverbose)
126 device_printf(dev, "gatt -> ag_pdir %8x\n",
127 (vm_offset_t)gatt->ag_pdir);
128 /*
129 * Allocate the gatt pages
130 */
131 gatt->ag_entries = entries;
132 if(bootverbose)
133 device_printf(dev, "allocating GATT for %d AGP page entries\n",
134 gatt->ag_entries);
135 gatt->ag_physical = vtophys((vm_offset_t) gatt->ag_virtual);
136
137 /*
138 * Map the pages of the GATT into the page directory.
139 *
140 * The GATT page addresses are mapped into the directory offset by
141 * an amount dependent on the base address of the aperture. This
142 * is and offset into the page directory, not an offset added to
143 * the addresses of the gatt pages.
144 */
145
146 pdir_offset = pci_read_config(dev, AGP_AMD751_APBASE, 4) >> 22;
147
148 npages = ((entries * sizeof(u_int32_t) + AGP_PAGE_SIZE - 1)
149 >> AGP_PAGE_SHIFT);
150
151 for (i = 0; i < npages; i++) {
152 vm_offset_t va;
153 vm_offset_t pa;
154
155 va = ((vm_offset_t) gatt->ag_virtual) + i * AGP_PAGE_SIZE;
156 pa = vtophys(va);
157 gatt->ag_vdir[i + pdir_offset] = pa | 1;
158 }
159
160 /*
161 * Make sure the chipset can see everything.
162 */
163 agp_flush_cache();
164
165 return gatt;
166 }
167
168 static void
169 agp_amd_free_gatt(struct agp_amd_gatt *gatt)
170 {
171 free(gatt->ag_virtual, M_AGP);
172 free(gatt->ag_vdir, M_AGP);
173 free(gatt, M_AGP);
174 }
175
176 static const char*
177 agp_amd_match(device_t dev)
178 {
179 if (pci_get_class(dev) != PCIC_BRIDGE
180 || pci_get_subclass(dev) != PCIS_BRIDGE_HOST)
181 return NULL;
182
183 if (agp_find_caps(dev) == 0)
184 return NULL;
185
186 switch (pci_get_devid(dev)) {
187
188 case 0x70061022:
189 return ("AMD 751 host to AGP bridge");
190
191 case 0x700e1022:
192 return ("AMD 761 host to AGP bridge");
193
194 case 0x700c1022:
195 return ("AMD 762 host to AGP bridge");
196
197 };
198
199 return NULL;
200 }
201
202 static int
203 agp_amd_probe(device_t dev)
204 {
205 const char *desc;
206
207 desc = agp_amd_match(dev);
208 if (desc) {
209 device_verbose(dev);
210 device_set_desc(dev, desc);
211 return 0;
212 }
213
214 return ENXIO;
215 }
216
217 static int
218 agp_amd_attach(device_t dev)
219 {
220 struct agp_amd_softc *sc = device_get_softc(dev);
221 struct agp_amd_gatt *gatt;
222 int error, rid;
223
224 error = agp_generic_attach(dev);
225 if (error)
226 return error;
227
228 rid = AGP_AMD751_REGISTERS;
229 sc->regs = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid,
230 0, ~0, 1, RF_ACTIVE);
231 if (!sc->regs) {
232 agp_generic_detach(dev);
233 return ENOMEM;
234 }
235
236 sc->bst = rman_get_bustag(sc->regs);
237 sc->bsh = rman_get_bushandle(sc->regs);
238
239 sc->initial_aperture = AGP_GET_APERTURE(dev);
240
241 for (;;) {
242 gatt = agp_amd_alloc_gatt(dev);
243 if (gatt)
244 break;
245
246 /*
247 * Probably contigmalloc failure. Try reducing the
248 * aperture so that the gatt size reduces.
249 */
250 if (AGP_SET_APERTURE(dev, AGP_GET_APERTURE(dev) / 2))
251 return ENOMEM;
252 }
253 sc->gatt = gatt;
254
255 /* Install the gatt. */
256 WRITE4(AGP_AMD751_ATTBASE, gatt->ag_pdir);
257
258 /* Enable synchronisation between host and agp. */
259 pci_write_config(dev,
260 AGP_AMD751_MODECTRL,
261 AGP_AMD751_MODECTRL_SYNEN, 1);
262
263 /* Set indexing mode for two-level and enable page dir cache */
264 pci_write_config(dev,
265 AGP_AMD751_MODECTRL2,
266 AGP_AMD751_MODECTRL2_GPDCE, 1);
267
268 /* Enable the TLB and flush */
269 WRITE2(AGP_AMD751_STATUS,
270 READ2(AGP_AMD751_STATUS) | AGP_AMD751_STATUS_GCE);
271 AGP_FLUSH_TLB(dev);
272
273 return 0;
274 }
275
276 static int
277 agp_amd_detach(device_t dev)
278 {
279 struct agp_amd_softc *sc = device_get_softc(dev);
280 int error;
281
282 error = agp_generic_detach(dev);
283 if (error)
284 return error;
285
286 /* Disable the TLB.. */
287 WRITE2(AGP_AMD751_STATUS,
288 READ2(AGP_AMD751_STATUS) & ~AGP_AMD751_STATUS_GCE);
289
290 /* Disable host-agp sync */
291 pci_write_config(dev, AGP_AMD751_MODECTRL, 0x00, 1);
292
293 /* Clear the GATT base */
294 WRITE4(AGP_AMD751_ATTBASE, 0);
295
296 /* Put the aperture back the way it started. */
297 AGP_SET_APERTURE(dev, sc->initial_aperture);
298
299 agp_amd_free_gatt(sc->gatt);
300
301 bus_release_resource(dev, SYS_RES_MEMORY,
302 AGP_AMD751_REGISTERS, sc->regs);
303
304 return 0;
305 }
306
307 static u_int32_t
308 agp_amd_get_aperture(device_t dev)
309 {
310 int vas;
311
312 /*
313 * The aperture size is equal to 32M<<vas.
314 */
315 vas = (pci_read_config(dev, AGP_AMD751_APCTRL, 1) & 0x06) >> 1;
316 return (32*1024*1024) << vas;
317 }
318
319 static int
320 agp_amd_set_aperture(device_t dev, u_int32_t aperture)
321 {
322 int vas;
323
324 /*
325 * Check for a power of two and make sure its within the
326 * programmable range.
327 */
328 if (aperture & (aperture - 1)
329 || aperture < 32*1024*1024
330 || aperture > 2U*1024*1024*1024)
331 return EINVAL;
332
333 vas = ffs(aperture / 32*1024*1024) - 1;
334
335 /*
336 * While the size register is bits 1-3 of APCTRL, bit 0 must be
337 * set for the size value to be 'valid'
338 */
339 pci_write_config(dev, AGP_AMD751_APCTRL,
340 (((pci_read_config(dev, AGP_AMD751_APCTRL, 1) & ~0x06)
341 | ((vas << 1) | 1))), 1);
342
343 return 0;
344 }
345
346 static int
347 agp_amd_bind_page(device_t dev, int offset, vm_offset_t physical)
348 {
349 struct agp_amd_softc *sc = device_get_softc(dev);
350
351 if (offset < 0 || offset >= (sc->gatt->ag_entries << AGP_PAGE_SHIFT))
352 return EINVAL;
353
354 sc->gatt->ag_virtual[offset >> AGP_PAGE_SHIFT] = physical | 1;
355
356 /* invalidate the cache */
357 AGP_FLUSH_TLB(dev);
358 return 0;
359 }
360
361 static int
362 agp_amd_unbind_page(device_t dev, int offset)
363 {
364 struct agp_amd_softc *sc = device_get_softc(dev);
365
366 if (offset < 0 || offset >= (sc->gatt->ag_entries << AGP_PAGE_SHIFT))
367 return EINVAL;
368
369 sc->gatt->ag_virtual[offset >> AGP_PAGE_SHIFT] = 0;
370 return 0;
371 }
372
373 static void
374 agp_amd_flush_tlb(device_t dev)
375 {
376 struct agp_amd_softc *sc = device_get_softc(dev);
377
378 /* Set the cache invalidate bit and wait for the chipset to clear */
379 WRITE4(AGP_AMD751_TLBCTRL, 1);
380 do {
381 DELAY(1);
382 } while (READ4(AGP_AMD751_TLBCTRL));
383 }
384
385 static device_method_t agp_amd_methods[] = {
386 /* Device interface */
387 DEVMETHOD(device_probe, agp_amd_probe),
388 DEVMETHOD(device_attach, agp_amd_attach),
389 DEVMETHOD(device_detach, agp_amd_detach),
390 DEVMETHOD(device_shutdown, bus_generic_shutdown),
391 DEVMETHOD(device_suspend, bus_generic_suspend),
392 DEVMETHOD(device_resume, bus_generic_resume),
393
394 /* AGP interface */
395 DEVMETHOD(agp_get_aperture, agp_amd_get_aperture),
396 DEVMETHOD(agp_set_aperture, agp_amd_set_aperture),
397 DEVMETHOD(agp_bind_page, agp_amd_bind_page),
398 DEVMETHOD(agp_unbind_page, agp_amd_unbind_page),
399 DEVMETHOD(agp_flush_tlb, agp_amd_flush_tlb),
400 DEVMETHOD(agp_enable, agp_generic_enable),
401 DEVMETHOD(agp_alloc_memory, agp_generic_alloc_memory),
402 DEVMETHOD(agp_free_memory, agp_generic_free_memory),
403 DEVMETHOD(agp_bind_memory, agp_generic_bind_memory),
404 DEVMETHOD(agp_unbind_memory, agp_generic_unbind_memory),
405
406 { 0, 0 }
407 };
408
409 static driver_t agp_amd_driver = {
410 "agp",
411 agp_amd_methods,
412 sizeof(struct agp_amd_softc),
413 };
414
415 static devclass_t agp_devclass;
416
417 DRIVER_MODULE(agp_amd, pci, agp_amd_driver, agp_devclass, 0, 0);
Cache object: a7166368db33bf9e78a86bda03c33eba
|