Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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FreeBSD/Linux Kernel Cross Reference
sys/pci/agp_amd64.c
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1 /*- 2 * Copyright (c) 2004, 2005 Jung-uk Kim <jkim@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __FBSDID("$FreeBSD: releng/6.1/sys/pci/agp_amd64.c 152440 2005-11-14 22:48:30Z jkim $"); 29 30 #include "opt_bus.h" 31 32 #include <sys/param.h> 33 #include <sys/systm.h> 34 #include <sys/malloc.h> 35 #include <sys/kernel.h> 36 #include <sys/module.h> 37 #include <sys/bus.h> 38 #include <sys/lock.h> 39 #include <sys/mutex.h> 40 #include <sys/proc.h> 41 42 #include <dev/pci/pcivar.h> 43 #include <dev/pci/pcireg.h> 44 #include <pci/agppriv.h> 45 #include <pci/agpreg.h> 46 47 #include <vm/vm.h> 48 #include <vm/vm_object.h> 49 #include <vm/pmap.h> 50 #include <machine/bus.h> 51 #include <machine/resource.h> 52 #include <sys/rman.h> 53 54 /* XXX */ 55 extern void pci_cfgregwrite(int, int, int, int, uint32_t, int); 56 extern uint32_t pci_cfgregread(int, int, int, int, int); 57 58 static void agp_amd64_apbase_fixup(device_t); 59 60 static void agp_amd64_uli_init(device_t); 61 static int agp_amd64_uli_set_aperture(device_t, uint32_t); 62 63 static int agp_amd64_nvidia_match(uint16_t); 64 static void agp_amd64_nvidia_init(device_t); 65 static int agp_amd64_nvidia_set_aperture(device_t, uint32_t); 66 67 static int agp_amd64_via_match(void); 68 static void agp_amd64_via_init(device_t); 69 static int agp_amd64_via_set_aperture(device_t, uint32_t); 70 71 MALLOC_DECLARE(M_AGP); 72 73 #define AMD64_MAX_MCTRL 8 74 75 struct agp_amd64_softc { 76 struct agp_softc agp; 77 uint32_t initial_aperture; 78 struct agp_gatt *gatt; 79 uint32_t apbase; 80 int mctrl[AMD64_MAX_MCTRL]; 81 int n_mctrl; 82 int via_agp; 83 }; 84 85 static const char* 86 agp_amd64_match(device_t dev) 87 { 88 if (pci_get_class(dev) != PCIC_BRIDGE 89 || pci_get_subclass(dev) != PCIS_BRIDGE_HOST) 90 return NULL; 91 92 if (agp_find_caps(dev) == 0) 93 return NULL; 94 95 switch (pci_get_devid(dev)) { 96 case 0x74541022: 97 return ("AMD 8151 AGP graphics tunnel"); 98 case 0x07551039: 99 return ("SiS 755 host to AGP bridge"); 100 case 0x168910b9: 101 return ("ULi M1689 AGP Controller"); 102 case 0x00d110de: 103 if (agp_amd64_nvidia_match(0x00d2)) 104 return NULL; 105 return ("NVIDIA nForce3 AGP Controller"); 106 case 0x00e110de: 107 if (agp_amd64_nvidia_match(0x00e2)) 108 return NULL; 109 return ("NVIDIA nForce3-250 AGP Controller"); 110 case 0x02041106: 111 return ("VIA 8380 host to PCI bridge"); 112 case 0x02381106: 113 return ("VIA 3238 host to PCI bridge"); 114 case 0x02821106: 115 return ("VIA K8T800Pro host to PCI bridge"); 116 case 0x31881106: 117 return ("VIA 8385 host to PCI bridge"); 118 }; 119 120 return NULL; 121 } 122 123 static int 124 agp_amd64_nvidia_match(uint16_t devid) 125 { 126 /* XXX nForce3 requires secondary AGP bridge at 0:11:0. */ 127 if (pci_cfgregread(0, 11, 0, PCIR_CLASS, 1) != PCIC_BRIDGE || 128 pci_cfgregread(0, 11, 0, PCIR_SUBCLASS, 1) != PCIS_BRIDGE_PCI || 129 pci_cfgregread(0, 11, 0, PCIR_VENDOR, 2) != 0x10de || 130 pci_cfgregread(0, 11, 0, PCIR_DEVICE, 2) != devid) 131 return ENXIO; 132 133 return 0; 134 } 135 136 static int 137 agp_amd64_via_match(void) 138 { 139 /* XXX Some VIA bridge requires secondary AGP bridge at 0:1:0. */ 140 if (pci_cfgregread(0, 1, 0, PCIR_CLASS, 1) != PCIC_BRIDGE || 141 pci_cfgregread(0, 1, 0, PCIR_SUBCLASS, 1) != PCIS_BRIDGE_PCI || 142 pci_cfgregread(0, 1, 0, PCIR_VENDOR, 2) != 0x1106 || 143 pci_cfgregread(0, 1, 0, PCIR_DEVICE, 2) != 0xb188 || 144 (pci_cfgregread(0, 1, 0, AGP_VIA_AGPSEL, 1) & 2)) 145 return 0; 146 147 return 1; 148 } 149 150 static int 151 agp_amd64_probe(device_t dev) 152 { 153 const char *desc; 154 155 if (resource_disabled("agp", device_get_unit(dev))) 156 return ENXIO; 157 if ((desc = agp_amd64_match(dev))) { 158 device_verbose(dev); 159 device_set_desc(dev, desc); 160 return BUS_PROBE_DEFAULT; 161 } 162 163 return ENXIO; 164 } 165 166 static int 167 agp_amd64_attach(device_t dev) 168 { 169 struct agp_amd64_softc *sc = device_get_softc(dev); 170 struct agp_gatt *gatt; 171 int i, n, error; 172 173 for (i = 0, n = 0; i < PCI_SLOTMAX && n < AMD64_MAX_MCTRL; i++) 174 if (pci_cfgregread(0, i, 3, 0, 4) == 0x11031022) { 175 sc->mctrl[n] = i; 176 n++; 177 } 178 179 if (n == 0) 180 return ENXIO; 181 182 sc->n_mctrl = n; 183 184 if (bootverbose) { 185 device_printf(dev, "%d Miscellaneous Control unit(s) found.\n", 186 sc->n_mctrl); 187 for (i = 0; i < sc->n_mctrl; i++) 188 device_printf(dev, "Aperture Base[%d]: 0x%08x\n", i, 189 pci_cfgregread(0, sc->mctrl[i], 3, 190 AGP_AMD64_APBASE, 4) & AGP_AMD64_APBASE_MASK); 191 } 192 193 if ((error = agp_generic_attach(dev))) 194 return error; 195 196 sc->initial_aperture = AGP_GET_APERTURE(dev); 197 198 for (;;) { 199 gatt = agp_alloc_gatt(dev); 200 if (gatt) 201 break; 202 203 /* 204 * Probably contigmalloc failure. Try reducing the 205 * aperture so that the gatt size reduces. 206 */ 207 if (AGP_SET_APERTURE(dev, AGP_GET_APERTURE(dev) / 2)) { 208 agp_generic_detach(dev); 209 return ENOMEM; 210 } 211 } 212 sc->gatt = gatt; 213 214 switch (pci_get_vendor(dev)) { 215 case 0x10b9: /* ULi */ 216 agp_amd64_uli_init(dev); 217 if (agp_amd64_uli_set_aperture(dev, sc->initial_aperture)) 218 return ENXIO; 219 break; 220 221 case 0x10de: /* nVidia */ 222 agp_amd64_nvidia_init(dev); 223 if (agp_amd64_nvidia_set_aperture(dev, sc->initial_aperture)) 224 return ENXIO; 225 break; 226 227 case 0x1106: /* VIA */ 228 sc->via_agp = agp_amd64_via_match(); 229 if (sc->via_agp) { 230 agp_amd64_via_init(dev); 231 if (agp_amd64_via_set_aperture(dev, 232 sc->initial_aperture)) 233 return ENXIO; 234 } 235 break; 236 } 237 238 /* Install the gatt and enable aperture. */ 239 for (i = 0; i < sc->n_mctrl; i++) { 240 pci_cfgregwrite(0, sc->mctrl[i], 3, AGP_AMD64_ATTBASE, 241 (uint32_t)(gatt->ag_physical >> 8) & AGP_AMD64_ATTBASE_MASK, 242 4); 243 pci_cfgregwrite(0, sc->mctrl[i], 3, AGP_AMD64_APCTRL, 244 (pci_cfgregread(0, sc->mctrl[i], 3, AGP_AMD64_APCTRL, 4) | 245 AGP_AMD64_APCTRL_GARTEN) & 246 ~(AGP_AMD64_APCTRL_DISGARTCPU | AGP_AMD64_APCTRL_DISGARTIO), 247 4); 248 } 249 250 agp_flush_cache(); 251 252 return 0; 253 } 254 255 static int 256 agp_amd64_detach(device_t dev) 257 { 258 struct agp_amd64_softc *sc = device_get_softc(dev); 259 int i, error; 260 261 if ((error = agp_generic_detach(dev))) 262 return error; 263 264 for (i = 0; i < sc->n_mctrl; i++) 265 pci_cfgregwrite(0, sc->mctrl[i], 3, AGP_AMD64_APCTRL, 266 pci_cfgregread(0, sc->mctrl[i], 3, AGP_AMD64_APCTRL, 4) & 267 ~AGP_AMD64_APCTRL_GARTEN, 4); 268 269 AGP_SET_APERTURE(dev, sc->initial_aperture); 270 agp_free_gatt(sc->gatt); 271 272 return 0; 273 } 274 275 static uint32_t agp_amd64_table[] = { 276 0x02000000, /* 32 MB */ 277 0x04000000, /* 64 MB */ 278 0x08000000, /* 128 MB */ 279 0x10000000, /* 256 MB */ 280 0x20000000, /* 512 MB */ 281 0x40000000, /* 1024 MB */ 282 0x80000000, /* 2048 MB */ 283 }; 284 285 #define AGP_AMD64_TABLE_SIZE \ 286 (sizeof(agp_amd64_table) / sizeof(agp_amd64_table[0])) 287 288 static uint32_t 289 agp_amd64_get_aperture(device_t dev) 290 { 291 struct agp_amd64_softc *sc = device_get_softc(dev); 292 uint32_t i; 293 294 i = (pci_cfgregread(0, sc->mctrl[0], 3, AGP_AMD64_APCTRL, 4) & 295 AGP_AMD64_APCTRL_SIZE_MASK) >> 1; 296 297 if (i >= AGP_AMD64_TABLE_SIZE) 298 return 0; 299 300 return (agp_amd64_table[i]); 301 } 302 303 static int 304 agp_amd64_set_aperture(device_t dev, uint32_t aperture) 305 { 306 struct agp_amd64_softc *sc = device_get_softc(dev); 307 uint32_t i; 308 int j; 309 310 for (i = 0; i < AGP_AMD64_TABLE_SIZE; i++) 311 if (agp_amd64_table[i] == aperture) 312 break; 313 if (i >= AGP_AMD64_TABLE_SIZE) 314 return EINVAL; 315 316 for (j = 0; j < sc->n_mctrl; j++) 317 pci_cfgregwrite(0, sc->mctrl[j], 3, AGP_AMD64_APCTRL, 318 (pci_cfgregread(0, sc->mctrl[j], 3, AGP_AMD64_APCTRL, 4) & 319 ~(AGP_AMD64_APCTRL_SIZE_MASK)) | (i << 1), 4); 320 321 switch (pci_get_vendor(dev)) { 322 case 0x10b9: /* ULi */ 323 return (agp_amd64_uli_set_aperture(dev, aperture)); 324 break; 325 326 case 0x10de: /* nVidia */ 327 return (agp_amd64_nvidia_set_aperture(dev, aperture)); 328 break; 329 330 case 0x1106: /* VIA */ 331 if (sc->via_agp) 332 return (agp_amd64_via_set_aperture(dev, aperture)); 333 break; 334 } 335 336 return 0; 337 } 338 339 static int 340 agp_amd64_bind_page(device_t dev, int offset, vm_offset_t physical) 341 { 342 struct agp_amd64_softc *sc = device_get_softc(dev); 343 344 if (offset < 0 || offset >= (sc->gatt->ag_entries << AGP_PAGE_SHIFT)) 345 return EINVAL; 346 347 sc->gatt->ag_virtual[offset >> AGP_PAGE_SHIFT] = physical; 348 return 0; 349 } 350 351 static int 352 agp_amd64_unbind_page(device_t dev, int offset) 353 { 354 struct agp_amd64_softc *sc = device_get_softc(dev); 355 356 if (offset < 0 || offset >= (sc->gatt->ag_entries << AGP_PAGE_SHIFT)) 357 return EINVAL; 358 359 sc->gatt->ag_virtual[offset >> AGP_PAGE_SHIFT] = 0; 360 return 0; 361 } 362 363 static void 364 agp_amd64_flush_tlb(device_t dev) 365 { 366 struct agp_amd64_softc *sc = device_get_softc(dev); 367 int i; 368 369 for (i = 0; i < sc->n_mctrl; i++) 370 pci_cfgregwrite(0, sc->mctrl[i], 3, AGP_AMD64_CACHECTRL, 371 pci_cfgregread(0, sc->mctrl[i], 3, AGP_AMD64_CACHECTRL, 4) | 372 AGP_AMD64_CACHECTRL_INVGART, 4); 373 } 374 375 static void 376 agp_amd64_apbase_fixup(device_t dev) 377 { 378 struct agp_amd64_softc *sc = device_get_softc(dev); 379 uint32_t apbase; 380 int i; 381 382 apbase = pci_cfgregread(0, sc->mctrl[0], 3, AGP_AMD64_APBASE, 4); 383 for (i = 0; i < sc->n_mctrl; i++) 384 pci_cfgregwrite(0, sc->mctrl[i], 3, AGP_AMD64_APBASE, 385 apbase & ~(AGP_AMD64_APBASE_MASK & ~(uint32_t)0x7f), 4); 386 sc->apbase = apbase << 25; 387 } 388 389 static void 390 agp_amd64_uli_init(device_t dev) 391 { 392 struct agp_amd64_softc *sc = device_get_softc(dev); 393 394 agp_amd64_apbase_fixup(dev); 395 pci_write_config(dev, AGP_AMD64_ULI_APBASE, 396 (pci_read_config(dev, AGP_AMD64_ULI_APBASE, 4) & 0x0000000f) | 397 sc->apbase, 4); 398 pci_write_config(dev, AGP_AMD64_ULI_HTT_FEATURE, sc->apbase, 4); 399 } 400 401 static int 402 agp_amd64_uli_set_aperture(device_t dev, uint32_t aperture) 403 { 404 struct agp_amd64_softc *sc = device_get_softc(dev); 405 406 switch (aperture) { 407 case 0x02000000: /* 32 MB */ 408 case 0x04000000: /* 64 MB */ 409 case 0x08000000: /* 128 MB */ 410 case 0x10000000: /* 256 MB */ 411 break; 412 default: 413 return EINVAL; 414 } 415 416 pci_write_config(dev, AGP_AMD64_ULI_ENU_SCR, 417 sc->apbase + aperture - 1, 4); 418 419 return 0; 420 } 421 422 static void 423 agp_amd64_nvidia_init(device_t dev) 424 { 425 struct agp_amd64_softc *sc = device_get_softc(dev); 426 427 agp_amd64_apbase_fixup(dev); 428 pci_write_config(dev, AGP_AMD64_NVIDIA_0_APBASE, 429 (pci_read_config(dev, AGP_AMD64_NVIDIA_0_APBASE, 4) & 0x0000000f) | 430 sc->apbase, 4); 431 pci_cfgregwrite(0, 11, 0, AGP_AMD64_NVIDIA_1_APBASE1, sc->apbase, 4); 432 pci_cfgregwrite(0, 11, 0, AGP_AMD64_NVIDIA_1_APBASE2, sc->apbase, 4); 433 } 434 435 static int 436 agp_amd64_nvidia_set_aperture(device_t dev, uint32_t aperture) 437 { 438 struct agp_amd64_softc *sc = device_get_softc(dev); 439 uint32_t apsize; 440 441 switch (aperture) { 442 case 0x02000000: apsize = 0x0f; break; /* 32 MB */ 443 case 0x04000000: apsize = 0x0e; break; /* 64 MB */ 444 case 0x08000000: apsize = 0x0c; break; /* 128 MB */ 445 case 0x10000000: apsize = 0x08; break; /* 256 MB */ 446 case 0x20000000: apsize = 0x00; break; /* 512 MB */ 447 default: 448 return EINVAL; 449 } 450 451 pci_cfgregwrite(0, 11, 0, AGP_AMD64_NVIDIA_1_APSIZE, 452 (pci_cfgregread(0, 11, 0, AGP_AMD64_NVIDIA_1_APSIZE, 4) & 453 0xfffffff0) | apsize, 4); 454 pci_cfgregwrite(0, 11, 0, AGP_AMD64_NVIDIA_1_APLIMIT1, 455 sc->apbase + aperture - 1, 4); 456 pci_cfgregwrite(0, 11, 0, AGP_AMD64_NVIDIA_1_APLIMIT2, 457 sc->apbase + aperture - 1, 4); 458 459 return 0; 460 } 461 462 static void 463 agp_amd64_via_init(device_t dev) 464 { 465 struct agp_amd64_softc *sc = device_get_softc(dev); 466 467 agp_amd64_apbase_fixup(dev); 468 pci_cfgregwrite(0, 1, 0, AGP3_VIA_ATTBASE, sc->gatt->ag_physical, 4); 469 pci_cfgregwrite(0, 1, 0, AGP3_VIA_GARTCTRL, 470 pci_cfgregread(0, 1, 0, AGP3_VIA_ATTBASE, 4) | 0x180, 4); 471 } 472 473 static int 474 agp_amd64_via_set_aperture(device_t dev, uint32_t aperture) 475 { 476 uint32_t apsize; 477 478 apsize = ((aperture - 1) >> 20) ^ 0xff; 479 if ((((apsize ^ 0xff) << 20) | ((1 << 20) - 1)) + 1 != aperture) 480 return EINVAL; 481 pci_cfgregwrite(0, 1, 0, AGP3_VIA_APSIZE, apsize, 1); 482 483 return 0; 484 } 485 486 static device_method_t agp_amd64_methods[] = { 487 /* Device interface */ 488 DEVMETHOD(device_probe, agp_amd64_probe), 489 DEVMETHOD(device_attach, agp_amd64_attach), 490 DEVMETHOD(device_detach, agp_amd64_detach), 491 DEVMETHOD(device_shutdown, bus_generic_shutdown), 492 DEVMETHOD(device_suspend, bus_generic_suspend), 493 DEVMETHOD(device_resume, bus_generic_resume), 494 495 /* AGP interface */ 496 DEVMETHOD(agp_get_aperture, agp_amd64_get_aperture), 497 DEVMETHOD(agp_set_aperture, agp_amd64_set_aperture), 498 DEVMETHOD(agp_bind_page, agp_amd64_bind_page), 499 DEVMETHOD(agp_unbind_page, agp_amd64_unbind_page), 500 DEVMETHOD(agp_flush_tlb, agp_amd64_flush_tlb), 501 DEVMETHOD(agp_enable, agp_generic_enable), 502 DEVMETHOD(agp_alloc_memory, agp_generic_alloc_memory), 503 DEVMETHOD(agp_free_memory, agp_generic_free_memory), 504 DEVMETHOD(agp_bind_memory, agp_generic_bind_memory), 505 DEVMETHOD(agp_unbind_memory, agp_generic_unbind_memory), 506 507 { 0, 0 } 508 }; 509 510 static driver_t agp_amd64_driver = { 511 "agp", 512 agp_amd64_methods, 513 sizeof(struct agp_amd64_softc), 514 }; 515 516 static devclass_t agp_devclass; 517 518 DRIVER_MODULE(agp_amd64, pci, agp_amd64_driver, agp_devclass, 0, 0); 519 MODULE_DEPEND(agp_amd64, agp, 1, 1, 1); 520 MODULE_DEPEND(agp_amd64, pci, 1, 1, 1);
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