FreeBSD/Linux Kernel Cross Reference
sys/pci/agp_amd64.c
1 /*-
2 * Copyright (c) 2004, 2005 Jung-uk Kim <jkim@FreeBSD.org>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 */
26
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD: releng/6.3/sys/pci/agp_amd64.c 173886 2007-11-24 19:45:58Z cvs2svn $");
29
30 #include "opt_bus.h"
31
32 #include <sys/param.h>
33 #include <sys/systm.h>
34 #include <sys/malloc.h>
35 #include <sys/kernel.h>
36 #include <sys/module.h>
37 #include <sys/bus.h>
38 #include <sys/lock.h>
39 #include <sys/mutex.h>
40 #include <sys/proc.h>
41
42 #include <dev/pci/pcivar.h>
43 #include <dev/pci/pcireg.h>
44 #include <pci/agppriv.h>
45 #include <pci/agpreg.h>
46
47 #include <vm/vm.h>
48 #include <vm/vm_object.h>
49 #include <vm/pmap.h>
50 #include <machine/bus.h>
51 #include <machine/resource.h>
52 #include <sys/rman.h>
53
54 /* XXX */
55 extern void pci_cfgregwrite(int, int, int, int, uint32_t, int);
56 extern uint32_t pci_cfgregread(int, int, int, int, int);
57
58 static void agp_amd64_apbase_fixup(device_t);
59
60 static void agp_amd64_uli_init(device_t);
61 static int agp_amd64_uli_set_aperture(device_t, uint32_t);
62
63 static int agp_amd64_nvidia_match(uint16_t);
64 static void agp_amd64_nvidia_init(device_t);
65 static int agp_amd64_nvidia_set_aperture(device_t, uint32_t);
66
67 static int agp_amd64_via_match(void);
68 static void agp_amd64_via_init(device_t);
69 static int agp_amd64_via_set_aperture(device_t, uint32_t);
70
71 MALLOC_DECLARE(M_AGP);
72
73 #define AMD64_MAX_MCTRL 8
74
75 struct agp_amd64_softc {
76 struct agp_softc agp;
77 uint32_t initial_aperture;
78 struct agp_gatt *gatt;
79 uint32_t apbase;
80 int mctrl[AMD64_MAX_MCTRL];
81 int n_mctrl;
82 int via_agp;
83 };
84
85 static const char*
86 agp_amd64_match(device_t dev)
87 {
88 if (pci_get_class(dev) != PCIC_BRIDGE
89 || pci_get_subclass(dev) != PCIS_BRIDGE_HOST)
90 return NULL;
91
92 if (agp_find_caps(dev) == 0)
93 return NULL;
94
95 switch (pci_get_devid(dev)) {
96 case 0x74541022:
97 return ("AMD 8151 AGP graphics tunnel");
98 case 0x07551039:
99 return ("SiS 755 host to AGP bridge");
100 case 0x07601039:
101 return ("SiS 760 host to AGP bridge");
102 case 0x168910b9:
103 return ("ULi M1689 AGP Controller");
104 case 0x00d110de:
105 if (agp_amd64_nvidia_match(0x00d2))
106 return NULL;
107 return ("NVIDIA nForce3 AGP Controller");
108 case 0x00e110de:
109 if (agp_amd64_nvidia_match(0x00e2))
110 return NULL;
111 return ("NVIDIA nForce3-250 AGP Controller");
112 case 0x02041106:
113 return ("VIA 8380 host to PCI bridge");
114 case 0x02381106:
115 return ("VIA 3238 host to PCI bridge");
116 case 0x02821106:
117 return ("VIA K8T800Pro host to PCI bridge");
118 case 0x31881106:
119 return ("VIA 8385 host to PCI bridge");
120 };
121
122 return NULL;
123 }
124
125 static int
126 agp_amd64_nvidia_match(uint16_t devid)
127 {
128 /* XXX nForce3 requires secondary AGP bridge at 0:11:0. */
129 if (pci_cfgregread(0, 11, 0, PCIR_CLASS, 1) != PCIC_BRIDGE ||
130 pci_cfgregread(0, 11, 0, PCIR_SUBCLASS, 1) != PCIS_BRIDGE_PCI ||
131 pci_cfgregread(0, 11, 0, PCIR_VENDOR, 2) != 0x10de ||
132 pci_cfgregread(0, 11, 0, PCIR_DEVICE, 2) != devid)
133 return ENXIO;
134
135 return 0;
136 }
137
138 static int
139 agp_amd64_via_match(void)
140 {
141 /* XXX Some VIA bridge requires secondary AGP bridge at 0:1:0. */
142 if (pci_cfgregread(0, 1, 0, PCIR_CLASS, 1) != PCIC_BRIDGE ||
143 pci_cfgregread(0, 1, 0, PCIR_SUBCLASS, 1) != PCIS_BRIDGE_PCI ||
144 pci_cfgregread(0, 1, 0, PCIR_VENDOR, 2) != 0x1106 ||
145 pci_cfgregread(0, 1, 0, PCIR_DEVICE, 2) != 0xb188 ||
146 (pci_cfgregread(0, 1, 0, AGP_VIA_AGPSEL, 1) & 2))
147 return 0;
148
149 return 1;
150 }
151
152 static int
153 agp_amd64_probe(device_t dev)
154 {
155 const char *desc;
156
157 if (resource_disabled("agp", device_get_unit(dev)))
158 return ENXIO;
159 if ((desc = agp_amd64_match(dev))) {
160 device_verbose(dev);
161 device_set_desc(dev, desc);
162 return BUS_PROBE_DEFAULT;
163 }
164
165 return ENXIO;
166 }
167
168 static int
169 agp_amd64_attach(device_t dev)
170 {
171 struct agp_amd64_softc *sc = device_get_softc(dev);
172 struct agp_gatt *gatt;
173 int i, n, error;
174
175 for (i = 0, n = 0; i < PCI_SLOTMAX && n < AMD64_MAX_MCTRL; i++)
176 if (pci_cfgregread(0, i, 3, 0, 4) == 0x11031022) {
177 sc->mctrl[n] = i;
178 n++;
179 }
180
181 if (n == 0)
182 return ENXIO;
183
184 sc->n_mctrl = n;
185
186 if (bootverbose) {
187 device_printf(dev, "%d Miscellaneous Control unit(s) found.\n",
188 sc->n_mctrl);
189 for (i = 0; i < sc->n_mctrl; i++)
190 device_printf(dev, "Aperture Base[%d]: 0x%08x\n", i,
191 pci_cfgregread(0, sc->mctrl[i], 3,
192 AGP_AMD64_APBASE, 4) & AGP_AMD64_APBASE_MASK);
193 }
194
195 if ((error = agp_generic_attach(dev)))
196 return error;
197
198 sc->initial_aperture = AGP_GET_APERTURE(dev);
199
200 for (;;) {
201 gatt = agp_alloc_gatt(dev);
202 if (gatt)
203 break;
204
205 /*
206 * Probably contigmalloc failure. Try reducing the
207 * aperture so that the gatt size reduces.
208 */
209 if (AGP_SET_APERTURE(dev, AGP_GET_APERTURE(dev) / 2)) {
210 agp_generic_detach(dev);
211 return ENOMEM;
212 }
213 }
214 sc->gatt = gatt;
215
216 switch (pci_get_vendor(dev)) {
217 case 0x10b9: /* ULi */
218 agp_amd64_uli_init(dev);
219 if (agp_amd64_uli_set_aperture(dev, sc->initial_aperture))
220 return ENXIO;
221 break;
222
223 case 0x10de: /* nVidia */
224 agp_amd64_nvidia_init(dev);
225 if (agp_amd64_nvidia_set_aperture(dev, sc->initial_aperture))
226 return ENXIO;
227 break;
228
229 case 0x1106: /* VIA */
230 sc->via_agp = agp_amd64_via_match();
231 if (sc->via_agp) {
232 agp_amd64_via_init(dev);
233 if (agp_amd64_via_set_aperture(dev,
234 sc->initial_aperture))
235 return ENXIO;
236 }
237 break;
238 }
239
240 /* Install the gatt and enable aperture. */
241 for (i = 0; i < sc->n_mctrl; i++) {
242 pci_cfgregwrite(0, sc->mctrl[i], 3, AGP_AMD64_ATTBASE,
243 (uint32_t)(gatt->ag_physical >> 8) & AGP_AMD64_ATTBASE_MASK,
244 4);
245 pci_cfgregwrite(0, sc->mctrl[i], 3, AGP_AMD64_APCTRL,
246 (pci_cfgregread(0, sc->mctrl[i], 3, AGP_AMD64_APCTRL, 4) |
247 AGP_AMD64_APCTRL_GARTEN) &
248 ~(AGP_AMD64_APCTRL_DISGARTCPU | AGP_AMD64_APCTRL_DISGARTIO),
249 4);
250 }
251
252 agp_flush_cache();
253
254 return 0;
255 }
256
257 static int
258 agp_amd64_detach(device_t dev)
259 {
260 struct agp_amd64_softc *sc = device_get_softc(dev);
261 int i;
262
263 agp_free_cdev(dev);
264
265 for (i = 0; i < sc->n_mctrl; i++)
266 pci_cfgregwrite(0, sc->mctrl[i], 3, AGP_AMD64_APCTRL,
267 pci_cfgregread(0, sc->mctrl[i], 3, AGP_AMD64_APCTRL, 4) &
268 ~AGP_AMD64_APCTRL_GARTEN, 4);
269
270 AGP_SET_APERTURE(dev, sc->initial_aperture);
271 agp_free_gatt(sc->gatt);
272 agp_free_res(dev);
273
274 return 0;
275 }
276
277 static uint32_t agp_amd64_table[] = {
278 0x02000000, /* 32 MB */
279 0x04000000, /* 64 MB */
280 0x08000000, /* 128 MB */
281 0x10000000, /* 256 MB */
282 0x20000000, /* 512 MB */
283 0x40000000, /* 1024 MB */
284 0x80000000, /* 2048 MB */
285 };
286
287 #define AGP_AMD64_TABLE_SIZE \
288 (sizeof(agp_amd64_table) / sizeof(agp_amd64_table[0]))
289
290 static uint32_t
291 agp_amd64_get_aperture(device_t dev)
292 {
293 struct agp_amd64_softc *sc = device_get_softc(dev);
294 uint32_t i;
295
296 i = (pci_cfgregread(0, sc->mctrl[0], 3, AGP_AMD64_APCTRL, 4) &
297 AGP_AMD64_APCTRL_SIZE_MASK) >> 1;
298
299 if (i >= AGP_AMD64_TABLE_SIZE)
300 return 0;
301
302 return (agp_amd64_table[i]);
303 }
304
305 static int
306 agp_amd64_set_aperture(device_t dev, uint32_t aperture)
307 {
308 struct agp_amd64_softc *sc = device_get_softc(dev);
309 uint32_t i;
310 int j;
311
312 for (i = 0; i < AGP_AMD64_TABLE_SIZE; i++)
313 if (agp_amd64_table[i] == aperture)
314 break;
315 if (i >= AGP_AMD64_TABLE_SIZE)
316 return EINVAL;
317
318 for (j = 0; j < sc->n_mctrl; j++)
319 pci_cfgregwrite(0, sc->mctrl[j], 3, AGP_AMD64_APCTRL,
320 (pci_cfgregread(0, sc->mctrl[j], 3, AGP_AMD64_APCTRL, 4) &
321 ~(AGP_AMD64_APCTRL_SIZE_MASK)) | (i << 1), 4);
322
323 switch (pci_get_vendor(dev)) {
324 case 0x10b9: /* ULi */
325 return (agp_amd64_uli_set_aperture(dev, aperture));
326 break;
327
328 case 0x10de: /* nVidia */
329 return (agp_amd64_nvidia_set_aperture(dev, aperture));
330 break;
331
332 case 0x1106: /* VIA */
333 if (sc->via_agp)
334 return (agp_amd64_via_set_aperture(dev, aperture));
335 break;
336 }
337
338 return 0;
339 }
340
341 static int
342 agp_amd64_bind_page(device_t dev, int offset, vm_offset_t physical)
343 {
344 struct agp_amd64_softc *sc = device_get_softc(dev);
345
346 if (offset < 0 || offset >= (sc->gatt->ag_entries << AGP_PAGE_SHIFT))
347 return EINVAL;
348
349 sc->gatt->ag_virtual[offset >> AGP_PAGE_SHIFT] = physical;
350 return 0;
351 }
352
353 static int
354 agp_amd64_unbind_page(device_t dev, int offset)
355 {
356 struct agp_amd64_softc *sc = device_get_softc(dev);
357
358 if (offset < 0 || offset >= (sc->gatt->ag_entries << AGP_PAGE_SHIFT))
359 return EINVAL;
360
361 sc->gatt->ag_virtual[offset >> AGP_PAGE_SHIFT] = 0;
362 return 0;
363 }
364
365 static void
366 agp_amd64_flush_tlb(device_t dev)
367 {
368 struct agp_amd64_softc *sc = device_get_softc(dev);
369 int i;
370
371 for (i = 0; i < sc->n_mctrl; i++)
372 pci_cfgregwrite(0, sc->mctrl[i], 3, AGP_AMD64_CACHECTRL,
373 pci_cfgregread(0, sc->mctrl[i], 3, AGP_AMD64_CACHECTRL, 4) |
374 AGP_AMD64_CACHECTRL_INVGART, 4);
375 }
376
377 static void
378 agp_amd64_apbase_fixup(device_t dev)
379 {
380 struct agp_amd64_softc *sc = device_get_softc(dev);
381 uint32_t apbase;
382 int i;
383
384 apbase = pci_cfgregread(0, sc->mctrl[0], 3, AGP_AMD64_APBASE, 4);
385 for (i = 0; i < sc->n_mctrl; i++)
386 pci_cfgregwrite(0, sc->mctrl[i], 3, AGP_AMD64_APBASE,
387 apbase & ~(AGP_AMD64_APBASE_MASK & ~(uint32_t)0x7f), 4);
388 sc->apbase = apbase << 25;
389 }
390
391 static void
392 agp_amd64_uli_init(device_t dev)
393 {
394 struct agp_amd64_softc *sc = device_get_softc(dev);
395
396 agp_amd64_apbase_fixup(dev);
397 pci_write_config(dev, AGP_AMD64_ULI_APBASE,
398 (pci_read_config(dev, AGP_AMD64_ULI_APBASE, 4) & 0x0000000f) |
399 sc->apbase, 4);
400 pci_write_config(dev, AGP_AMD64_ULI_HTT_FEATURE, sc->apbase, 4);
401 }
402
403 static int
404 agp_amd64_uli_set_aperture(device_t dev, uint32_t aperture)
405 {
406 struct agp_amd64_softc *sc = device_get_softc(dev);
407
408 switch (aperture) {
409 case 0x02000000: /* 32 MB */
410 case 0x04000000: /* 64 MB */
411 case 0x08000000: /* 128 MB */
412 case 0x10000000: /* 256 MB */
413 break;
414 default:
415 return EINVAL;
416 }
417
418 pci_write_config(dev, AGP_AMD64_ULI_ENU_SCR,
419 sc->apbase + aperture - 1, 4);
420
421 return 0;
422 }
423
424 static void
425 agp_amd64_nvidia_init(device_t dev)
426 {
427 struct agp_amd64_softc *sc = device_get_softc(dev);
428
429 agp_amd64_apbase_fixup(dev);
430 pci_write_config(dev, AGP_AMD64_NVIDIA_0_APBASE,
431 (pci_read_config(dev, AGP_AMD64_NVIDIA_0_APBASE, 4) & 0x0000000f) |
432 sc->apbase, 4);
433 pci_cfgregwrite(0, 11, 0, AGP_AMD64_NVIDIA_1_APBASE1, sc->apbase, 4);
434 pci_cfgregwrite(0, 11, 0, AGP_AMD64_NVIDIA_1_APBASE2, sc->apbase, 4);
435 }
436
437 static int
438 agp_amd64_nvidia_set_aperture(device_t dev, uint32_t aperture)
439 {
440 struct agp_amd64_softc *sc = device_get_softc(dev);
441 uint32_t apsize;
442
443 switch (aperture) {
444 case 0x02000000: apsize = 0x0f; break; /* 32 MB */
445 case 0x04000000: apsize = 0x0e; break; /* 64 MB */
446 case 0x08000000: apsize = 0x0c; break; /* 128 MB */
447 case 0x10000000: apsize = 0x08; break; /* 256 MB */
448 case 0x20000000: apsize = 0x00; break; /* 512 MB */
449 default:
450 return EINVAL;
451 }
452
453 pci_cfgregwrite(0, 11, 0, AGP_AMD64_NVIDIA_1_APSIZE,
454 (pci_cfgregread(0, 11, 0, AGP_AMD64_NVIDIA_1_APSIZE, 4) &
455 0xfffffff0) | apsize, 4);
456 pci_cfgregwrite(0, 11, 0, AGP_AMD64_NVIDIA_1_APLIMIT1,
457 sc->apbase + aperture - 1, 4);
458 pci_cfgregwrite(0, 11, 0, AGP_AMD64_NVIDIA_1_APLIMIT2,
459 sc->apbase + aperture - 1, 4);
460
461 return 0;
462 }
463
464 static void
465 agp_amd64_via_init(device_t dev)
466 {
467 struct agp_amd64_softc *sc = device_get_softc(dev);
468
469 agp_amd64_apbase_fixup(dev);
470 pci_cfgregwrite(0, 1, 0, AGP3_VIA_ATTBASE, sc->gatt->ag_physical, 4);
471 pci_cfgregwrite(0, 1, 0, AGP3_VIA_GARTCTRL,
472 pci_cfgregread(0, 1, 0, AGP3_VIA_ATTBASE, 4) | 0x180, 4);
473 }
474
475 static int
476 agp_amd64_via_set_aperture(device_t dev, uint32_t aperture)
477 {
478 uint32_t apsize;
479
480 apsize = ((aperture - 1) >> 20) ^ 0xff;
481 if ((((apsize ^ 0xff) << 20) | ((1 << 20) - 1)) + 1 != aperture)
482 return EINVAL;
483 pci_cfgregwrite(0, 1, 0, AGP3_VIA_APSIZE, apsize, 1);
484
485 return 0;
486 }
487
488 static device_method_t agp_amd64_methods[] = {
489 /* Device interface */
490 DEVMETHOD(device_probe, agp_amd64_probe),
491 DEVMETHOD(device_attach, agp_amd64_attach),
492 DEVMETHOD(device_detach, agp_amd64_detach),
493 DEVMETHOD(device_shutdown, bus_generic_shutdown),
494 DEVMETHOD(device_suspend, bus_generic_suspend),
495 DEVMETHOD(device_resume, bus_generic_resume),
496
497 /* AGP interface */
498 DEVMETHOD(agp_get_aperture, agp_amd64_get_aperture),
499 DEVMETHOD(agp_set_aperture, agp_amd64_set_aperture),
500 DEVMETHOD(agp_bind_page, agp_amd64_bind_page),
501 DEVMETHOD(agp_unbind_page, agp_amd64_unbind_page),
502 DEVMETHOD(agp_flush_tlb, agp_amd64_flush_tlb),
503 DEVMETHOD(agp_enable, agp_generic_enable),
504 DEVMETHOD(agp_alloc_memory, agp_generic_alloc_memory),
505 DEVMETHOD(agp_free_memory, agp_generic_free_memory),
506 DEVMETHOD(agp_bind_memory, agp_generic_bind_memory),
507 DEVMETHOD(agp_unbind_memory, agp_generic_unbind_memory),
508
509 { 0, 0 }
510 };
511
512 static driver_t agp_amd64_driver = {
513 "agp",
514 agp_amd64_methods,
515 sizeof(struct agp_amd64_softc),
516 };
517
518 static devclass_t agp_devclass;
519
520 DRIVER_MODULE(agp_amd64, pci, agp_amd64_driver, agp_devclass, 0, 0);
521 MODULE_DEPEND(agp_amd64, agp, 1, 1, 1);
522 MODULE_DEPEND(agp_amd64, pci, 1, 1, 1);
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