The Design and Implementation of the FreeBSD Operating System, Second Edition
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FreeBSD/Linux Kernel Cross Reference
sys/pci/agp_amd64.c

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    1 /*-
    2  * Copyright (c) 2004, 2005 Jung-uk Kim <jkim@FreeBSD.org>
    3  * All rights reserved.
    4  *
    5  * Redistribution and use in source and binary forms, with or without
    6  * modification, are permitted provided that the following conditions
    7  * are met:
    8  * 1. Redistributions of source code must retain the above copyright
    9  *    notice, this list of conditions and the following disclaimer.
   10  * 2. Redistributions in binary form must reproduce the above copyright
   11  *    notice, this list of conditions and the following disclaimer in the
   12  *    documentation and/or other materials provided with the distribution.
   13  *
   14  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
   15  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   16  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   17  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
   18  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
   19  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
   20  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
   21  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
   22  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   23  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   24  * SUCH DAMAGE.
   25  */
   26 
   27 #include <sys/cdefs.h>
   28 __FBSDID("$FreeBSD$");
   29 
   30 #include "opt_bus.h"
   31 
   32 #include <sys/param.h>
   33 #include <sys/systm.h>
   34 #include <sys/malloc.h>
   35 #include <sys/kernel.h>
   36 #include <sys/module.h>
   37 #include <sys/bus.h>
   38 #include <sys/lock.h>
   39 #include <sys/mutex.h>
   40 #include <sys/proc.h>
   41 
   42 #include <dev/pci/pcivar.h>
   43 #include <dev/pci/pcireg.h>
   44 #include <pci/agppriv.h>
   45 #include <pci/agpreg.h>
   46 
   47 #include <vm/vm.h>
   48 #include <vm/vm_object.h>
   49 #include <vm/pmap.h>
   50 #include <machine/bus.h>
   51 #include <machine/resource.h>
   52 #include <sys/rman.h>
   53 
   54 /* XXX */
   55 extern void pci_cfgregwrite(int, int, int, int, uint32_t, int);
   56 extern uint32_t pci_cfgregread(int, int, int, int, int);
   57 
   58 static void agp_amd64_apbase_fixup(device_t);
   59 
   60 static void agp_amd64_uli_init(device_t);
   61 static int agp_amd64_uli_set_aperture(device_t, uint32_t);
   62 
   63 static int agp_amd64_nvidia_match(uint16_t);
   64 static void agp_amd64_nvidia_init(device_t);
   65 static int agp_amd64_nvidia_set_aperture(device_t, uint32_t);
   66 
   67 static int agp_amd64_via_match(void);
   68 static void agp_amd64_via_init(device_t);
   69 static int agp_amd64_via_set_aperture(device_t, uint32_t);
   70 
   71 MALLOC_DECLARE(M_AGP);
   72 
   73 #define AMD64_MAX_MCTRL         8
   74 
   75 struct agp_amd64_softc {
   76         struct agp_softc        agp;
   77         uint32_t                initial_aperture;
   78         struct agp_gatt         *gatt;
   79         uint32_t                apbase;
   80         int                     mctrl[AMD64_MAX_MCTRL];
   81         int                     n_mctrl;
   82         int                     via_agp;
   83 };
   84 
   85 static const char*
   86 agp_amd64_match(device_t dev)
   87 {
   88         if (pci_get_class(dev) != PCIC_BRIDGE ||
   89             pci_get_subclass(dev) != PCIS_BRIDGE_HOST ||
   90             agp_find_caps(dev) == 0)
   91                 return (NULL);
   92 
   93         switch (pci_get_devid(dev)) {
   94         case 0x74541022:
   95                 return ("AMD 8151 AGP graphics tunnel");
   96         case 0x07551039:
   97                 return ("SiS 755 host to AGP bridge");
   98         case 0x07601039:
   99                 return ("SiS 760 host to AGP bridge");
  100         case 0x168910b9:
  101                 return ("ULi M1689 AGP Controller");
  102         case 0x00d110de:
  103                 if (agp_amd64_nvidia_match(0x00d2))
  104                         return (NULL);
  105                 return ("NVIDIA nForce3 AGP Controller");
  106         case 0x00e110de:
  107                 if (agp_amd64_nvidia_match(0x00e2))
  108                         return (NULL);
  109                 return ("NVIDIA nForce3-250 AGP Controller");
  110         case 0x02041106:
  111                 return ("VIA 8380 host to PCI bridge");
  112         case 0x02381106:
  113                 return ("VIA 3238 host to PCI bridge");
  114         case 0x02821106:
  115                 return ("VIA K8T800Pro host to PCI bridge");
  116         case 0x31881106:
  117                 return ("VIA 8385 host to PCI bridge");
  118         };
  119 
  120         return (NULL);
  121 }
  122 
  123 static int
  124 agp_amd64_nvidia_match(uint16_t devid)
  125 {
  126         /* XXX nForce3 requires secondary AGP bridge at 0:11:0. */
  127         if (pci_cfgregread(0, 11, 0, PCIR_CLASS, 1) != PCIC_BRIDGE ||
  128             pci_cfgregread(0, 11, 0, PCIR_SUBCLASS, 1) != PCIS_BRIDGE_PCI ||
  129             pci_cfgregread(0, 11, 0, PCIR_VENDOR, 2) != 0x10de ||
  130             pci_cfgregread(0, 11, 0, PCIR_DEVICE, 2) != devid)
  131                 return (ENXIO);
  132 
  133         return (0);
  134 }
  135 
  136 static int
  137 agp_amd64_via_match(void)
  138 {
  139         /* XXX Some VIA bridge requires secondary AGP bridge at 0:1:0. */
  140         if (pci_cfgregread(0, 1, 0, PCIR_CLASS, 1) != PCIC_BRIDGE ||
  141             pci_cfgregread(0, 1, 0, PCIR_SUBCLASS, 1) != PCIS_BRIDGE_PCI ||
  142             pci_cfgregread(0, 1, 0, PCIR_VENDOR, 2) != 0x1106 ||
  143             pci_cfgregread(0, 1, 0, PCIR_DEVICE, 2) != 0xb188 ||
  144             (pci_cfgregread(0, 1, 0, AGP_VIA_AGPSEL, 1) & 2))
  145                 return (0);
  146 
  147         return (1);
  148 }
  149 
  150 static int
  151 agp_amd64_probe(device_t dev)
  152 {
  153         const char *desc;
  154 
  155         if (resource_disabled("agp", device_get_unit(dev)))
  156                 return (ENXIO);
  157         if ((desc = agp_amd64_match(dev))) {
  158                 device_set_desc(dev, desc);
  159                 return (BUS_PROBE_DEFAULT);
  160         }
  161 
  162         return (ENXIO);
  163 }
  164 
  165 static int
  166 agp_amd64_attach(device_t dev)
  167 {
  168         struct agp_amd64_softc *sc = device_get_softc(dev);
  169         struct agp_gatt *gatt;
  170         int i, n, error;
  171 
  172         for (i = 0, n = 0; i < PCI_SLOTMAX && n < AMD64_MAX_MCTRL; i++)
  173                 if (pci_cfgregread(0, i, 3, 0, 4) == 0x11031022) {
  174                         sc->mctrl[n] = i;
  175                         n++;
  176                 }
  177 
  178         if (n == 0)
  179                 return (ENXIO);
  180 
  181         sc->n_mctrl = n;
  182 
  183         if (bootverbose)
  184                 device_printf(dev, "%d Miscellaneous Control unit(s) found.\n",
  185                     sc->n_mctrl);
  186 
  187         if ((error = agp_generic_attach(dev)))
  188                 return (error);
  189 
  190         sc->initial_aperture = AGP_GET_APERTURE(dev);
  191 
  192         for (;;) {
  193                 gatt = agp_alloc_gatt(dev);
  194                 if (gatt)
  195                         break;
  196 
  197                 /*
  198                  * Probably contigmalloc failure. Try reducing the
  199                  * aperture so that the gatt size reduces.
  200                  */
  201                 if (AGP_SET_APERTURE(dev, AGP_GET_APERTURE(dev) / 2)) {
  202                         agp_generic_detach(dev);
  203                         return (ENOMEM);
  204                 }
  205         }
  206         sc->gatt = gatt;
  207 
  208         switch (pci_get_vendor(dev)) {
  209         case 0x10b9:    /* ULi */
  210                 agp_amd64_uli_init(dev);
  211                 if (agp_amd64_uli_set_aperture(dev, sc->initial_aperture))
  212                         return (ENXIO);
  213                 break;
  214 
  215         case 0x10de:    /* nVidia */
  216                 agp_amd64_nvidia_init(dev);
  217                 if (agp_amd64_nvidia_set_aperture(dev, sc->initial_aperture))
  218                         return (ENXIO);
  219                 break;
  220 
  221         case 0x1106:    /* VIA */
  222                 sc->via_agp = agp_amd64_via_match();
  223                 if (sc->via_agp) {
  224                         agp_amd64_via_init(dev);
  225                         if (agp_amd64_via_set_aperture(dev,
  226                             sc->initial_aperture))
  227                                 return (ENXIO);
  228                 }
  229                 break;
  230         }
  231 
  232         /* Install the gatt and enable aperture. */
  233         for (i = 0; i < sc->n_mctrl; i++) {
  234                 pci_cfgregwrite(0, sc->mctrl[i], 3, AGP_AMD64_ATTBASE,
  235                     (uint32_t)(gatt->ag_physical >> 8) & AGP_AMD64_ATTBASE_MASK,
  236                     4);
  237                 pci_cfgregwrite(0, sc->mctrl[i], 3, AGP_AMD64_APCTRL,
  238                     (pci_cfgregread(0, sc->mctrl[i], 3, AGP_AMD64_APCTRL, 4) |
  239                     AGP_AMD64_APCTRL_GARTEN) &
  240                     ~(AGP_AMD64_APCTRL_DISGARTCPU | AGP_AMD64_APCTRL_DISGARTIO),
  241                     4);
  242         }
  243 
  244         agp_flush_cache();
  245 
  246         return (0);
  247 }
  248 
  249 static int
  250 agp_amd64_detach(device_t dev)
  251 {
  252         struct agp_amd64_softc *sc = device_get_softc(dev);
  253         int i;
  254 
  255         agp_free_cdev(dev);
  256 
  257         for (i = 0; i < sc->n_mctrl; i++)
  258                 pci_cfgregwrite(0, sc->mctrl[i], 3, AGP_AMD64_APCTRL,
  259                     pci_cfgregread(0, sc->mctrl[i], 3, AGP_AMD64_APCTRL, 4) &
  260                     ~AGP_AMD64_APCTRL_GARTEN, 4);
  261 
  262         AGP_SET_APERTURE(dev, sc->initial_aperture);
  263         agp_free_gatt(sc->gatt);
  264         agp_free_res(dev);
  265 
  266         return (0);
  267 }
  268 
  269 static uint32_t agp_amd64_table[] = {
  270         0x02000000,     /*   32 MB */
  271         0x04000000,     /*   64 MB */
  272         0x08000000,     /*  128 MB */
  273         0x10000000,     /*  256 MB */
  274         0x20000000,     /*  512 MB */
  275         0x40000000,     /* 1024 MB */
  276         0x80000000,     /* 2048 MB */
  277 };
  278 
  279 #define AGP_AMD64_TABLE_SIZE \
  280         (sizeof(agp_amd64_table) / sizeof(agp_amd64_table[0]))
  281 
  282 static uint32_t
  283 agp_amd64_get_aperture(device_t dev)
  284 {
  285         struct agp_amd64_softc *sc = device_get_softc(dev);
  286         uint32_t i;
  287 
  288         i = (pci_cfgregread(0, sc->mctrl[0], 3, AGP_AMD64_APCTRL, 4) &
  289                 AGP_AMD64_APCTRL_SIZE_MASK) >> 1;
  290 
  291         if (i >= AGP_AMD64_TABLE_SIZE)
  292                 return (0);
  293 
  294         return (agp_amd64_table[i]);
  295 }
  296 
  297 static int
  298 agp_amd64_set_aperture(device_t dev, uint32_t aperture)
  299 {
  300         struct agp_amd64_softc *sc = device_get_softc(dev);
  301         uint32_t i;
  302         int j;
  303 
  304         for (i = 0; i < AGP_AMD64_TABLE_SIZE; i++)
  305                 if (agp_amd64_table[i] == aperture)
  306                         break;
  307         if (i >= AGP_AMD64_TABLE_SIZE)
  308                 return (EINVAL);
  309 
  310         for (j = 0; j < sc->n_mctrl; j++)
  311                 pci_cfgregwrite(0, sc->mctrl[j], 3, AGP_AMD64_APCTRL,
  312                     (pci_cfgregread(0, sc->mctrl[j], 3, AGP_AMD64_APCTRL, 4) &
  313                     ~(AGP_AMD64_APCTRL_SIZE_MASK)) | (i << 1), 4);
  314 
  315         switch (pci_get_vendor(dev)) {
  316         case 0x10b9:    /* ULi */
  317                 return (agp_amd64_uli_set_aperture(dev, aperture));
  318                 break;
  319 
  320         case 0x10de:    /* nVidia */
  321                 return (agp_amd64_nvidia_set_aperture(dev, aperture));
  322                 break;
  323 
  324         case 0x1106:    /* VIA */
  325                 if (sc->via_agp)
  326                         return (agp_amd64_via_set_aperture(dev, aperture));
  327                 break;
  328         }
  329 
  330         return (0);
  331 }
  332 
  333 static int
  334 agp_amd64_bind_page(device_t dev, int offset, vm_offset_t physical)
  335 {
  336         struct agp_amd64_softc *sc = device_get_softc(dev);
  337 
  338         if (offset < 0 || offset >= (sc->gatt->ag_entries << AGP_PAGE_SHIFT))
  339                 return (EINVAL);
  340 
  341         sc->gatt->ag_virtual[offset >> AGP_PAGE_SHIFT] =
  342             (physical & 0xfffff000) | ((physical >> 28) & 0x00000ff0) | 3;
  343 
  344         return (0);
  345 }
  346 
  347 static int
  348 agp_amd64_unbind_page(device_t dev, int offset)
  349 {
  350         struct agp_amd64_softc *sc = device_get_softc(dev);
  351 
  352         if (offset < 0 || offset >= (sc->gatt->ag_entries << AGP_PAGE_SHIFT))
  353                 return (EINVAL);
  354 
  355         sc->gatt->ag_virtual[offset >> AGP_PAGE_SHIFT] = 0;
  356 
  357         return (0);
  358 }
  359 
  360 static void
  361 agp_amd64_flush_tlb(device_t dev)
  362 {
  363         struct agp_amd64_softc *sc = device_get_softc(dev);
  364         int i;
  365 
  366         for (i = 0; i < sc->n_mctrl; i++)
  367                 pci_cfgregwrite(0, sc->mctrl[i], 3, AGP_AMD64_CACHECTRL,
  368                     pci_cfgregread(0, sc->mctrl[i], 3, AGP_AMD64_CACHECTRL, 4) |
  369                     AGP_AMD64_CACHECTRL_INVGART, 4);
  370 }
  371 
  372 static void
  373 agp_amd64_apbase_fixup(device_t dev)
  374 {
  375         struct agp_amd64_softc *sc = device_get_softc(dev);
  376         uint32_t apbase;
  377         int i;
  378 
  379         sc->apbase = rman_get_start(sc->agp.as_aperture);
  380         apbase = (sc->apbase >> 25) & AGP_AMD64_APBASE_MASK;
  381         for (i = 0; i < sc->n_mctrl; i++)
  382                 pci_cfgregwrite(0, sc->mctrl[i], 3,
  383                     AGP_AMD64_APBASE, apbase, 4);
  384 }
  385 
  386 static void
  387 agp_amd64_uli_init(device_t dev)
  388 {
  389         struct agp_amd64_softc *sc = device_get_softc(dev);
  390 
  391         agp_amd64_apbase_fixup(dev);
  392         pci_write_config(dev, AGP_AMD64_ULI_APBASE,
  393             (pci_read_config(dev, AGP_AMD64_ULI_APBASE, 4) & 0x0000000f) |
  394             sc->apbase, 4);
  395         pci_write_config(dev, AGP_AMD64_ULI_HTT_FEATURE, sc->apbase, 4);
  396 }
  397 
  398 static int
  399 agp_amd64_uli_set_aperture(device_t dev, uint32_t aperture)
  400 {
  401         struct agp_amd64_softc *sc = device_get_softc(dev);
  402 
  403         switch (aperture) {
  404         case 0x02000000:        /*  32 MB */
  405         case 0x04000000:        /*  64 MB */
  406         case 0x08000000:        /* 128 MB */
  407         case 0x10000000:        /* 256 MB */
  408                 break;
  409         default:
  410                 return (EINVAL);
  411         }
  412 
  413         pci_write_config(dev, AGP_AMD64_ULI_ENU_SCR,
  414             sc->apbase + aperture - 1, 4);
  415 
  416         return (0);
  417 }
  418 
  419 static void
  420 agp_amd64_nvidia_init(device_t dev)
  421 {
  422         struct agp_amd64_softc *sc = device_get_softc(dev);
  423 
  424         agp_amd64_apbase_fixup(dev);
  425         pci_write_config(dev, AGP_AMD64_NVIDIA_0_APBASE,
  426             (pci_read_config(dev, AGP_AMD64_NVIDIA_0_APBASE, 4) & 0x0000000f) |
  427             sc->apbase, 4);
  428         pci_cfgregwrite(0, 11, 0, AGP_AMD64_NVIDIA_1_APBASE1, sc->apbase, 4);
  429         pci_cfgregwrite(0, 11, 0, AGP_AMD64_NVIDIA_1_APBASE2, sc->apbase, 4);
  430 }
  431 
  432 static int
  433 agp_amd64_nvidia_set_aperture(device_t dev, uint32_t aperture)
  434 {
  435         struct agp_amd64_softc *sc = device_get_softc(dev);
  436         uint32_t apsize;
  437 
  438         switch (aperture) {
  439         case 0x02000000:        apsize = 0x0f;  break;  /*  32 MB */
  440         case 0x04000000:        apsize = 0x0e;  break;  /*  64 MB */
  441         case 0x08000000:        apsize = 0x0c;  break;  /* 128 MB */
  442         case 0x10000000:        apsize = 0x08;  break;  /* 256 MB */
  443         case 0x20000000:        apsize = 0x00;  break;  /* 512 MB */
  444         default:
  445                 return (EINVAL);
  446         }
  447 
  448         pci_cfgregwrite(0, 11, 0, AGP_AMD64_NVIDIA_1_APSIZE,
  449             (pci_cfgregread(0, 11, 0, AGP_AMD64_NVIDIA_1_APSIZE, 4) &
  450             0xfffffff0) | apsize, 4);
  451         pci_cfgregwrite(0, 11, 0, AGP_AMD64_NVIDIA_1_APLIMIT1,
  452             sc->apbase + aperture - 1, 4);
  453         pci_cfgregwrite(0, 11, 0, AGP_AMD64_NVIDIA_1_APLIMIT2,
  454             sc->apbase + aperture - 1, 4);
  455 
  456         return (0);
  457 }
  458 
  459 static void
  460 agp_amd64_via_init(device_t dev)
  461 {
  462         struct agp_amd64_softc *sc = device_get_softc(dev);
  463 
  464         agp_amd64_apbase_fixup(dev);
  465         pci_cfgregwrite(0, 1, 0, AGP3_VIA_ATTBASE, sc->gatt->ag_physical, 4);
  466         pci_cfgregwrite(0, 1, 0, AGP3_VIA_GARTCTRL,
  467             pci_cfgregread(0, 1, 0, AGP3_VIA_ATTBASE, 4) | 0x180, 4);
  468 }
  469 
  470 static int
  471 agp_amd64_via_set_aperture(device_t dev, uint32_t aperture)
  472 {
  473         uint32_t apsize;
  474 
  475         apsize = ((aperture - 1) >> 20) ^ 0xff;
  476         if ((((apsize ^ 0xff) << 20) | ((1 << 20) - 1)) + 1 != aperture)
  477                 return (EINVAL);
  478         pci_cfgregwrite(0, 1, 0, AGP3_VIA_APSIZE, apsize, 1);
  479 
  480         return (0);
  481 }
  482 
  483 static device_method_t agp_amd64_methods[] = {
  484         /* Device interface */
  485         DEVMETHOD(device_probe,         agp_amd64_probe),
  486         DEVMETHOD(device_attach,        agp_amd64_attach),
  487         DEVMETHOD(device_detach,        agp_amd64_detach),
  488         DEVMETHOD(device_shutdown,      bus_generic_shutdown),
  489         DEVMETHOD(device_suspend,       bus_generic_suspend),
  490         DEVMETHOD(device_resume,        bus_generic_resume),
  491 
  492         /* AGP interface */
  493         DEVMETHOD(agp_get_aperture,     agp_amd64_get_aperture),
  494         DEVMETHOD(agp_set_aperture,     agp_amd64_set_aperture),
  495         DEVMETHOD(agp_bind_page,        agp_amd64_bind_page),
  496         DEVMETHOD(agp_unbind_page,      agp_amd64_unbind_page),
  497         DEVMETHOD(agp_flush_tlb,        agp_amd64_flush_tlb),
  498         DEVMETHOD(agp_enable,           agp_generic_enable),
  499         DEVMETHOD(agp_alloc_memory,     agp_generic_alloc_memory),
  500         DEVMETHOD(agp_free_memory,      agp_generic_free_memory),
  501         DEVMETHOD(agp_bind_memory,      agp_generic_bind_memory),
  502         DEVMETHOD(agp_unbind_memory,    agp_generic_unbind_memory),
  503 
  504         { 0, 0 }
  505 };
  506 
  507 static driver_t agp_amd64_driver = {
  508         "agp",
  509         agp_amd64_methods,
  510         sizeof(struct agp_amd64_softc),
  511 };
  512 
  513 static devclass_t agp_devclass;
  514 
  515 DRIVER_MODULE(agp_amd64, hostb, agp_amd64_driver, agp_devclass, 0, 0);
  516 MODULE_DEPEND(agp_amd64, agp, 1, 1, 1);
  517 MODULE_DEPEND(agp_amd64, pci, 1, 1, 1);

Cache object: a9eff077262e6d0afd1c2b77d3e9dc76


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