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sys/pci/agp_i810.c
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1 /*- 2 * Copyright (c) 2000 Doug Rabson 3 * Copyright (c) 2000 Ruslan Ermilov 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28 /* 29 * Fixes for 830/845G support: David Dawes <dawes@xfree86.org> 30 * 852GM/855GM/865G support added by David Dawes <dawes@xfree86.org> 31 */ 32 33 #include <sys/cdefs.h> 34 __FBSDID("$FreeBSD: releng/6.4/sys/pci/agp_i810.c 173478 2007-11-08 20:50:13Z jhb $"); 35 36 #include "opt_bus.h" 37 38 #include <sys/param.h> 39 #include <sys/systm.h> 40 #include <sys/malloc.h> 41 #include <sys/kernel.h> 42 #include <sys/module.h> 43 #include <sys/bus.h> 44 #include <sys/lock.h> 45 #include <sys/mutex.h> 46 #include <sys/proc.h> 47 48 #include <dev/pci/pcivar.h> 49 #include <dev/pci/pcireg.h> 50 #include <pci/agppriv.h> 51 #include <pci/agpreg.h> 52 53 #include <vm/vm.h> 54 #include <vm/vm_object.h> 55 #include <vm/vm_page.h> 56 #include <vm/vm_pageout.h> 57 #include <vm/pmap.h> 58 59 #include <machine/bus.h> 60 #include <machine/resource.h> 61 #include <sys/rman.h> 62 63 MALLOC_DECLARE(M_AGP); 64 65 #define READ1(off) bus_space_read_1(sc->bst, sc->bsh, off) 66 #define READ4(off) bus_space_read_4(sc->bst, sc->bsh, off) 67 #define WRITE4(off,v) bus_space_write_4(sc->bst, sc->bsh, off, v) 68 #define WRITEGTT(off,v) bus_space_write_4(sc->gtt_bst, sc->gtt_bsh, off, v) 69 70 #define CHIP_I810 0 /* i810/i815 */ 71 #define CHIP_I830 1 /* 830M/845G */ 72 #define CHIP_I855 2 /* 852GM/855GM/865G */ 73 #define CHIP_I915 3 /* 915G/915GM */ 74 75 struct agp_i810_softc { 76 struct agp_softc agp; 77 u_int32_t initial_aperture; /* aperture size at startup */ 78 struct agp_gatt *gatt; 79 int chiptype; /* i810-like or i830 */ 80 u_int32_t dcache_size; /* i810 only */ 81 u_int32_t stolen; /* number of i830/845 gtt entries for stolen memory */ 82 device_t bdev; /* bridge device */ 83 84 struct resource *regs; /* memory mapped GC registers */ 85 bus_space_tag_t bst; /* bus_space tag */ 86 bus_space_handle_t bsh; /* bus_space handle */ 87 88 struct resource *gtt; /* memory mapped GATT entries */ 89 bus_space_tag_t gtt_bst; /* bus_space tag */ 90 bus_space_handle_t gtt_bsh; /* bus_space handle */ 91 92 struct resource *gm; /* unmapped (but allocated) aperture */ 93 94 void *argb_cursor; /* contigmalloc area for ARGB cursor */ 95 }; 96 97 static const char* 98 agp_i810_match(device_t dev) 99 { 100 if (pci_get_class(dev) != PCIC_DISPLAY 101 || pci_get_subclass(dev) != PCIS_DISPLAY_VGA) 102 return NULL; 103 104 switch (pci_get_devid(dev)) { 105 case 0x71218086: 106 return ("Intel 82810 (i810 GMCH) SVGA controller"); 107 108 case 0x71238086: 109 return ("Intel 82810-DC100 (i810-DC100 GMCH) SVGA controller"); 110 111 case 0x71258086: 112 return ("Intel 82810E (i810E GMCH) SVGA controller"); 113 114 case 0x11328086: 115 return ("Intel 82815 (i815 GMCH) SVGA controller"); 116 117 case 0x35778086: 118 return ("Intel 82830M (830M GMCH) SVGA controller"); 119 120 case 0x25628086: 121 return ("Intel 82845G (845G GMCH) SVGA controller"); 122 123 case 0x35828086: 124 switch (pci_read_config(dev, AGP_I85X_CAPID, 1)) { 125 case AGP_I855_GME: 126 return ("Intel 82855GME (855GME GMCH) SVGA controller"); 127 128 case AGP_I855_GM: 129 return ("Intel 82855GM (855GM GMCH) SVGA controller"); 130 131 case AGP_I852_GME: 132 return ("Intel 82852GME (852GME GMCH) SVGA controller"); 133 134 case AGP_I852_GM: 135 return ("Intel 82852GM (852GM GMCH) SVGA controller"); 136 137 default: 138 return ("Intel 8285xM (85xGM GMCH) SVGA controller"); 139 } 140 141 case 0x25728086: 142 return ("Intel 82865G (865G GMCH) SVGA controller"); 143 144 case 0x25828086: 145 return ("Intel 82915G (915G GMCH) SVGA controller"); 146 147 case 0x25928086: 148 return ("Intel 82915GM (915GM GMCH) SVGA controller"); 149 150 case 0x27728086: 151 return ("Intel 82945G (945G GMCH) SVGA controller"); 152 153 case 0x27A28086: 154 return ("Intel 82945GM (945GM GMCH) SVGA controller"); 155 }; 156 157 return NULL; 158 } 159 160 /* 161 * Find bridge device. 162 */ 163 static device_t 164 agp_i810_find_bridge(device_t dev) 165 { 166 device_t *children, child; 167 int nchildren, i; 168 u_int32_t devid; 169 170 /* 171 * Calculate bridge device's ID. 172 */ 173 devid = pci_get_devid(dev); 174 switch (devid) { 175 case 0x71218086: 176 case 0x71238086: 177 case 0x71258086: 178 devid -= 0x10000; 179 break; 180 181 case 0x11328086: 182 case 0x35778086: 183 case 0x25628086: 184 case 0x35828086: 185 case 0x25728086: 186 case 0x25828086: 187 case 0x25928086: 188 devid -= 0x20000; 189 break; 190 }; 191 if (device_get_children(device_get_parent(dev), &children, &nchildren)) 192 return 0; 193 194 for (i = 0; i < nchildren; i++) { 195 child = children[i]; 196 197 if (pci_get_devid(child) == devid) { 198 free(children, M_TEMP); 199 return child; 200 } 201 } 202 free(children, M_TEMP); 203 return 0; 204 } 205 206 static int 207 agp_i810_probe(device_t dev) 208 { 209 const char *desc; 210 211 if (resource_disabled("agp", device_get_unit(dev))) 212 return (ENXIO); 213 desc = agp_i810_match(dev); 214 if (desc) { 215 device_t bdev; 216 u_int8_t smram; 217 unsigned int gcc1; 218 int devid = pci_get_devid(dev); 219 220 bdev = agp_i810_find_bridge(dev); 221 if (!bdev) { 222 if (bootverbose) 223 printf("I810: can't find bridge device\n"); 224 return ENXIO; 225 } 226 227 /* 228 * checking whether internal graphics device has been activated. 229 */ 230 switch (devid) { 231 /* i810 */ 232 case 0x71218086: 233 case 0x71238086: 234 case 0x71258086: 235 case 0x11328086: 236 smram = pci_read_config(bdev, AGP_I810_SMRAM, 1); 237 if ((smram & AGP_I810_SMRAM_GMS) 238 == AGP_I810_SMRAM_GMS_DISABLED) { 239 if (bootverbose) 240 printf("I810: disabled, not probing\n"); 241 return ENXIO; 242 } 243 break; 244 245 /* i830 */ 246 case 0x35778086: 247 case 0x35828086: 248 case 0x25628086: 249 case 0x25728086: 250 gcc1 = pci_read_config(bdev, AGP_I830_GCC1, 1); 251 if ((gcc1 & AGP_I830_GCC1_DEV2) == AGP_I830_GCC1_DEV2_DISABLED) { 252 if (bootverbose) 253 printf("I830: disabled, not probing\n"); 254 return ENXIO; 255 } 256 break; 257 258 /* i915 */ 259 case 0x25828086: 260 case 0x25928086: 261 case 0x27728086: /* 945G GMCH */ 262 case 0x27A28086: /* 945GM GMCH */ 263 gcc1 = pci_read_config(bdev, AGP_I915_DEVEN, 4); 264 if ((gcc1 & AGP_I915_DEVEN_D2F0) == 265 AGP_I915_DEVEN_D2F0_DISABLED) { 266 if (bootverbose) 267 printf("I915: disabled, not probing\n"); 268 return ENXIO; 269 } 270 break; 271 272 default: 273 return ENXIO; 274 } 275 276 device_verbose(dev); 277 device_set_desc(dev, desc); 278 return BUS_PROBE_DEFAULT; 279 } 280 281 return ENXIO; 282 } 283 284 static int 285 agp_i810_attach(device_t dev) 286 { 287 struct agp_i810_softc *sc = device_get_softc(dev); 288 struct agp_gatt *gatt; 289 int error, rid; 290 291 sc->bdev = agp_i810_find_bridge(dev); 292 if (!sc->bdev) 293 return ENOENT; 294 295 error = agp_generic_attach(dev); 296 if (error) 297 return error; 298 299 switch (pci_get_devid(dev)) { 300 case 0x71218086: 301 case 0x71238086: 302 case 0x71258086: 303 case 0x11328086: 304 sc->chiptype = CHIP_I810; 305 break; 306 case 0x35778086: 307 case 0x25628086: 308 sc->chiptype = CHIP_I830; 309 break; 310 case 0x35828086: 311 case 0x25728086: 312 sc->chiptype = CHIP_I855; 313 break; 314 case 0x25828086: 315 case 0x25928086: 316 case 0x27728086: /* 945G GMCH */ 317 case 0x27A28086: /* 945GM GMCH */ 318 sc->chiptype = CHIP_I915; 319 break; 320 }; 321 322 /* Same for i810 and i830 */ 323 if (sc->chiptype == CHIP_I915) 324 rid = AGP_I915_MMADR; 325 else 326 rid = AGP_I810_MMADR; 327 328 sc->regs = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 329 RF_ACTIVE); 330 if (!sc->regs) { 331 agp_generic_detach(dev); 332 return ENODEV; 333 } 334 sc->bst = rman_get_bustag(sc->regs); 335 sc->bsh = rman_get_bushandle(sc->regs); 336 337 if (sc->chiptype == CHIP_I915) { 338 rid = AGP_I915_GTTADR; 339 sc->gtt = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 340 RF_ACTIVE); 341 if (!sc->gtt) { 342 bus_release_resource(dev, SYS_RES_MEMORY, 343 AGP_I915_MMADR, sc->regs); 344 agp_generic_detach(dev); 345 return ENODEV; 346 } 347 sc->gtt_bst = rman_get_bustag(sc->gtt); 348 sc->gtt_bsh = rman_get_bushandle(sc->gtt); 349 350 /* While agp_generic_attach allocates the AGP_APBASE resource 351 * to try to reserve the aperture, on the 915 the aperture 352 * isn't in PCIR_BAR(0), it's in PCIR_BAR(2), so it allocated 353 * the registers that we just mapped anyway. So, allocate the 354 * aperture here, which also gives us easy access to it for the 355 * agp_i810_get_aperture(). 356 */ 357 rid = AGP_I915_GMADR; 358 sc->gm = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 0); 359 if (sc->gm == NULL) { 360 bus_release_resource(dev, SYS_RES_MEMORY, 361 AGP_I915_MMADR, sc->regs); 362 bus_release_resource(dev, SYS_RES_MEMORY, 363 AGP_I915_GTTADR, sc->regs); 364 agp_generic_detach(dev); 365 return ENODEV; 366 } 367 368 } 369 370 sc->initial_aperture = AGP_GET_APERTURE(dev); 371 372 gatt = malloc( sizeof(struct agp_gatt), M_AGP, M_NOWAIT); 373 if (!gatt) { 374 agp_generic_detach(dev); 375 return ENOMEM; 376 } 377 sc->gatt = gatt; 378 379 gatt->ag_entries = AGP_GET_APERTURE(dev) >> AGP_PAGE_SHIFT; 380 381 if ( sc->chiptype == CHIP_I810 ) { 382 /* Some i810s have on-chip memory called dcache */ 383 if (READ1(AGP_I810_DRT) & AGP_I810_DRT_POPULATED) 384 sc->dcache_size = 4 * 1024 * 1024; 385 else 386 sc->dcache_size = 0; 387 388 /* According to the specs the gatt on the i810 must be 64k */ 389 gatt->ag_virtual = contigmalloc( 64 * 1024, M_AGP, 0, 390 0, ~0, PAGE_SIZE, 0); 391 if (!gatt->ag_virtual) { 392 if (bootverbose) 393 device_printf(dev, "contiguous allocation failed\n"); 394 free(gatt, M_AGP); 395 agp_generic_detach(dev); 396 return ENOMEM; 397 } 398 bzero(gatt->ag_virtual, gatt->ag_entries * sizeof(u_int32_t)); 399 400 gatt->ag_physical = vtophys((vm_offset_t) gatt->ag_virtual); 401 agp_flush_cache(); 402 /* Install the GATT. */ 403 WRITE4(AGP_I810_PGTBL_CTL, gatt->ag_physical | 1); 404 } else if ( sc->chiptype == CHIP_I830 ) { 405 /* The i830 automatically initializes the 128k gatt on boot. */ 406 unsigned int gcc1, pgtblctl; 407 408 gcc1 = pci_read_config(sc->bdev, AGP_I830_GCC1, 1); 409 switch (gcc1 & AGP_I830_GCC1_GMS) { 410 case AGP_I830_GCC1_GMS_STOLEN_512: 411 sc->stolen = (512 - 132) * 1024 / 4096; 412 break; 413 case AGP_I830_GCC1_GMS_STOLEN_1024: 414 sc->stolen = (1024 - 132) * 1024 / 4096; 415 break; 416 case AGP_I830_GCC1_GMS_STOLEN_8192: 417 sc->stolen = (8192 - 132) * 1024 / 4096; 418 break; 419 default: 420 sc->stolen = 0; 421 device_printf(dev, "unknown memory configuration, disabling\n"); 422 agp_generic_detach(dev); 423 return EINVAL; 424 } 425 if (sc->stolen > 0) 426 device_printf(dev, "detected %dk stolen memory\n", sc->stolen * 4); 427 device_printf(dev, "aperture size is %dM\n", sc->initial_aperture / 1024 / 1024); 428 429 /* GATT address is already in there, make sure it's enabled */ 430 pgtblctl = READ4(AGP_I810_PGTBL_CTL); 431 pgtblctl |= 1; 432 WRITE4(AGP_I810_PGTBL_CTL, pgtblctl); 433 434 gatt->ag_physical = pgtblctl & ~1; 435 } else if (sc->chiptype == CHIP_I855 || sc->chiptype == CHIP_I915) { /* CHIP_I855 */ 436 unsigned int gcc1, pgtblctl, stolen; 437 438 /* Stolen memory is set up at the beginning of the aperture by 439 * the BIOS, consisting of the GATT followed by 4kb for the BIOS 440 * display. 441 */ 442 if (sc->chiptype == CHIP_I855) 443 stolen = 132; 444 else 445 stolen = 260; 446 447 gcc1 = pci_read_config(sc->bdev, AGP_I855_GCC1, 1); 448 switch (gcc1 & AGP_I855_GCC1_GMS) { 449 case AGP_I855_GCC1_GMS_STOLEN_1M: 450 sc->stolen = (1024 - stolen) * 1024 / 4096; 451 break; 452 case AGP_I855_GCC1_GMS_STOLEN_4M: 453 sc->stolen = (4096 - stolen) * 1024 / 4096; 454 break; 455 case AGP_I855_GCC1_GMS_STOLEN_8M: 456 sc->stolen = (8192 - stolen) * 1024 / 4096; 457 break; 458 case AGP_I855_GCC1_GMS_STOLEN_16M: 459 sc->stolen = (16384 - stolen) * 1024 / 4096; 460 break; 461 case AGP_I855_GCC1_GMS_STOLEN_32M: 462 sc->stolen = (32768 - stolen) * 1024 / 4096; 463 break; 464 case AGP_I915_GCC1_GMS_STOLEN_48M: 465 sc->stolen = (49152 - stolen) * 1024 / 4096; 466 break; 467 case AGP_I915_GCC1_GMS_STOLEN_64M: 468 sc->stolen = (65536 - stolen) * 1024 / 4096; 469 break; 470 default: 471 sc->stolen = 0; 472 device_printf(dev, "unknown memory configuration, disabling\n"); 473 agp_generic_detach(dev); 474 return EINVAL; 475 } 476 if (sc->stolen > 0) 477 device_printf(dev, "detected %dk stolen memory\n", sc->stolen * 4); 478 device_printf(dev, "aperture size is %dM\n", sc->initial_aperture / 1024 / 1024); 479 480 /* GATT address is already in there, make sure it's enabled */ 481 pgtblctl = READ4(AGP_I810_PGTBL_CTL); 482 pgtblctl |= 1; 483 WRITE4(AGP_I810_PGTBL_CTL, pgtblctl); 484 485 gatt->ag_physical = pgtblctl & ~1; 486 } 487 488 /* Add a device for the drm to attach to */ 489 if (!device_add_child( dev, "drmsub", -1 )) 490 printf("out of memory...\n"); 491 492 return bus_generic_attach(dev); 493 } 494 495 static int 496 agp_i810_detach(device_t dev) 497 { 498 struct agp_i810_softc *sc = device_get_softc(dev); 499 device_t child; 500 501 agp_free_cdev(dev); 502 503 /* Clear the GATT base. */ 504 if ( sc->chiptype == CHIP_I810 ) { 505 WRITE4(AGP_I810_PGTBL_CTL, 0); 506 } else { 507 unsigned int pgtblctl; 508 pgtblctl = READ4(AGP_I810_PGTBL_CTL); 509 pgtblctl &= ~1; 510 WRITE4(AGP_I810_PGTBL_CTL, pgtblctl); 511 } 512 513 /* Put the aperture back the way it started. */ 514 AGP_SET_APERTURE(dev, sc->initial_aperture); 515 516 if ( sc->chiptype == CHIP_I810 ) { 517 contigfree(sc->gatt->ag_virtual, 64 * 1024, M_AGP); 518 } 519 free(sc->gatt, M_AGP); 520 521 if (sc->chiptype == CHIP_I915) { 522 bus_release_resource(dev, SYS_RES_MEMORY, AGP_I915_GMADR, 523 sc->gm); 524 bus_release_resource(dev, SYS_RES_MEMORY, AGP_I915_GTTADR, 525 sc->gtt); 526 bus_release_resource(dev, SYS_RES_MEMORY, AGP_I915_MMADR, 527 sc->regs); 528 } else { 529 bus_release_resource(dev, SYS_RES_MEMORY, AGP_I810_MMADR, 530 sc->regs); 531 } 532 agp_free_res(dev); 533 534 child = device_find_child( dev, "drmsub", 0 ); 535 if (child) 536 device_delete_child( dev, child ); 537 538 return 0; 539 } 540 541 static u_int32_t 542 agp_i810_get_aperture(device_t dev) 543 { 544 struct agp_i810_softc *sc = device_get_softc(dev); 545 uint32_t temp; 546 u_int16_t miscc; 547 548 switch (sc->chiptype) { 549 case CHIP_I810: 550 miscc = pci_read_config(sc->bdev, AGP_I810_MISCC, 2); 551 if ((miscc & AGP_I810_MISCC_WINSIZE) == AGP_I810_MISCC_WINSIZE_32) 552 return 32 * 1024 * 1024; 553 else 554 return 64 * 1024 * 1024; 555 case CHIP_I830: 556 temp = pci_read_config(sc->bdev, AGP_I830_GCC1, 2); 557 if ((temp & AGP_I830_GCC1_GMASIZE) == AGP_I830_GCC1_GMASIZE_64) 558 return 64 * 1024 * 1024; 559 else 560 return 128 * 1024 * 1024; 561 case CHIP_I855: 562 return 128 * 1024 * 1024; 563 case CHIP_I915: 564 /* The documentation states that AGP_I915_MSAC should have bit 565 * 1 set if the aperture is 128MB instead of 256. However, 566 * that bit appears to not get set, so we instead use the 567 * aperture resource size, which should always be correct. 568 */ 569 return rman_get_size(sc->gm); 570 } 571 572 return 0; 573 } 574 575 static int 576 agp_i810_set_aperture(device_t dev, u_int32_t aperture) 577 { 578 struct agp_i810_softc *sc = device_get_softc(dev); 579 u_int16_t miscc, gcc1; 580 u_int32_t temp; 581 582 switch (sc->chiptype) { 583 case CHIP_I810: 584 /* 585 * Double check for sanity. 586 */ 587 if (aperture != 32 * 1024 * 1024 && aperture != 64 * 1024 * 1024) { 588 device_printf(dev, "bad aperture size %d\n", aperture); 589 return EINVAL; 590 } 591 592 miscc = pci_read_config(sc->bdev, AGP_I810_MISCC, 2); 593 miscc &= ~AGP_I810_MISCC_WINSIZE; 594 if (aperture == 32 * 1024 * 1024) 595 miscc |= AGP_I810_MISCC_WINSIZE_32; 596 else 597 miscc |= AGP_I810_MISCC_WINSIZE_64; 598 599 pci_write_config(sc->bdev, AGP_I810_MISCC, miscc, 2); 600 break; 601 case CHIP_I830: 602 if (aperture != 64 * 1024 * 1024 && 603 aperture != 128 * 1024 * 1024) { 604 device_printf(dev, "bad aperture size %d\n", aperture); 605 return EINVAL; 606 } 607 gcc1 = pci_read_config(sc->bdev, AGP_I830_GCC1, 2); 608 gcc1 &= ~AGP_I830_GCC1_GMASIZE; 609 if (aperture == 64 * 1024 * 1024) 610 gcc1 |= AGP_I830_GCC1_GMASIZE_64; 611 else 612 gcc1 |= AGP_I830_GCC1_GMASIZE_128; 613 614 pci_write_config(sc->bdev, AGP_I830_GCC1, gcc1, 2); 615 break; 616 case CHIP_I855: 617 if (aperture != 128 * 1024 * 1024) { 618 device_printf(dev, "bad aperture size %d\n", aperture); 619 return EINVAL; 620 } 621 break; 622 case CHIP_I915: 623 temp = pci_read_config(dev, AGP_I915_MSAC, 1); 624 temp &= ~AGP_I915_MSAC_GMASIZE; 625 626 switch (aperture) { 627 case 128 * 1024 * 1024: 628 temp |= AGP_I915_MSAC_GMASIZE_128; 629 break; 630 case 256 * 1024 * 1024: 631 temp |= AGP_I915_MSAC_GMASIZE_256; 632 break; 633 default: 634 device_printf(dev, "bad aperture size %d\n", aperture); 635 return EINVAL; 636 } 637 638 pci_write_config(dev, AGP_I915_MSAC, temp, 1); 639 break; 640 } 641 642 return 0; 643 } 644 645 static int 646 agp_i810_bind_page(device_t dev, int offset, vm_offset_t physical) 647 { 648 struct agp_i810_softc *sc = device_get_softc(dev); 649 650 if (offset < 0 || offset >= (sc->gatt->ag_entries << AGP_PAGE_SHIFT)) { 651 device_printf(dev, "failed: offset is 0x%08x, shift is %d, entries is %d\n", offset, AGP_PAGE_SHIFT, sc->gatt->ag_entries); 652 return EINVAL; 653 } 654 655 if ( sc->chiptype != CHIP_I810 ) { 656 if ( (offset >> AGP_PAGE_SHIFT) < sc->stolen ) { 657 device_printf(dev, "trying to bind into stolen memory"); 658 return EINVAL; 659 } 660 } 661 662 if (sc->chiptype == CHIP_I915) { 663 WRITEGTT((offset >> AGP_PAGE_SHIFT) * 4, physical | 1); 664 } else { 665 WRITE4(AGP_I810_GTT + (offset >> AGP_PAGE_SHIFT) * 4, physical | 1); 666 } 667 668 return 0; 669 } 670 671 static int 672 agp_i810_unbind_page(device_t dev, int offset) 673 { 674 struct agp_i810_softc *sc = device_get_softc(dev); 675 676 if (offset < 0 || offset >= (sc->gatt->ag_entries << AGP_PAGE_SHIFT)) 677 return EINVAL; 678 679 if ( sc->chiptype != CHIP_I810 ) { 680 if ( (offset >> AGP_PAGE_SHIFT) < sc->stolen ) { 681 device_printf(dev, "trying to unbind from stolen memory"); 682 return EINVAL; 683 } 684 } 685 686 if (sc->chiptype == CHIP_I915) { 687 WRITEGTT((offset >> AGP_PAGE_SHIFT) * 4, 0); 688 } else { 689 WRITE4(AGP_I810_GTT + (offset >> AGP_PAGE_SHIFT) * 4, 0); 690 } 691 692 return 0; 693 } 694 695 /* 696 * Writing via memory mapped registers already flushes all TLBs. 697 */ 698 static void 699 agp_i810_flush_tlb(device_t dev) 700 { 701 } 702 703 static int 704 agp_i810_enable(device_t dev, u_int32_t mode) 705 { 706 707 return 0; 708 } 709 710 static struct agp_memory * 711 agp_i810_alloc_memory(device_t dev, int type, vm_size_t size) 712 { 713 struct agp_i810_softc *sc = device_get_softc(dev); 714 struct agp_memory *mem; 715 716 if ((size & (AGP_PAGE_SIZE - 1)) != 0) 717 return 0; 718 719 if (sc->agp.as_allocated + size > sc->agp.as_maxmem) 720 return 0; 721 722 if (type == 1) { 723 /* 724 * Mapping local DRAM into GATT. 725 */ 726 if ( sc->chiptype != CHIP_I810 ) 727 return 0; 728 if (size != sc->dcache_size) 729 return 0; 730 } else if (type == 2) { 731 /* 732 * Type 2 is the contiguous physical memory type, that hands 733 * back a physical address. This is used for cursors on i810. 734 * Hand back as many single pages with physical as the user 735 * wants, but only allow one larger allocation (ARGB cursor) 736 * for simplicity. 737 */ 738 if (size != AGP_PAGE_SIZE) { 739 if (sc->argb_cursor != NULL) 740 return 0; 741 742 /* Allocate memory for ARGB cursor, if we can. */ 743 sc->argb_cursor = contigmalloc(size, M_AGP, 744 0, 0, ~0, PAGE_SIZE, 0); 745 if (sc->argb_cursor == NULL) 746 return 0; 747 } 748 } 749 750 mem = malloc(sizeof *mem, M_AGP, M_WAITOK); 751 mem->am_id = sc->agp.as_nextid++; 752 mem->am_size = size; 753 mem->am_type = type; 754 if (type != 1 && (type != 2 || size == AGP_PAGE_SIZE)) 755 mem->am_obj = vm_object_allocate(OBJT_DEFAULT, 756 atop(round_page(size))); 757 else 758 mem->am_obj = 0; 759 760 if (type == 2) { 761 if (size == AGP_PAGE_SIZE) { 762 /* 763 * Allocate and wire down the page now so that we can 764 * get its physical address. 765 */ 766 vm_page_t m; 767 768 VM_OBJECT_LOCK(mem->am_obj); 769 m = vm_page_grab(mem->am_obj, 0, VM_ALLOC_NOBUSY | 770 VM_ALLOC_WIRED | VM_ALLOC_ZERO | VM_ALLOC_RETRY); 771 VM_OBJECT_UNLOCK(mem->am_obj); 772 mem->am_physical = VM_PAGE_TO_PHYS(m); 773 } else { 774 /* Our allocation is already nicely wired down for us. 775 * Just grab the physical address. 776 */ 777 mem->am_physical = vtophys(sc->argb_cursor); 778 } 779 } else { 780 mem->am_physical = 0; 781 } 782 783 mem->am_offset = 0; 784 mem->am_is_bound = 0; 785 TAILQ_INSERT_TAIL(&sc->agp.as_memory, mem, am_link); 786 sc->agp.as_allocated += size; 787 788 return mem; 789 } 790 791 static int 792 agp_i810_free_memory(device_t dev, struct agp_memory *mem) 793 { 794 struct agp_i810_softc *sc = device_get_softc(dev); 795 796 if (mem->am_is_bound) 797 return EBUSY; 798 799 if (mem->am_type == 2) { 800 if (mem->am_size == AGP_PAGE_SIZE) { 801 /* 802 * Unwire the page which we wired in alloc_memory. 803 */ 804 vm_page_t m; 805 806 VM_OBJECT_LOCK(mem->am_obj); 807 m = vm_page_lookup(mem->am_obj, 0); 808 VM_OBJECT_UNLOCK(mem->am_obj); 809 vm_page_lock_queues(); 810 vm_page_unwire(m, 0); 811 vm_page_unlock_queues(); 812 } else { 813 contigfree(sc->argb_cursor, mem->am_size, M_AGP); 814 sc->argb_cursor = NULL; 815 } 816 } 817 818 sc->agp.as_allocated -= mem->am_size; 819 TAILQ_REMOVE(&sc->agp.as_memory, mem, am_link); 820 if (mem->am_obj) 821 vm_object_deallocate(mem->am_obj); 822 free(mem, M_AGP); 823 return 0; 824 } 825 826 static int 827 agp_i810_bind_memory(device_t dev, struct agp_memory *mem, 828 vm_offset_t offset) 829 { 830 struct agp_i810_softc *sc = device_get_softc(dev); 831 vm_offset_t i; 832 833 /* Do some sanity checks first. */ 834 if (offset < 0 || (offset & (AGP_PAGE_SIZE - 1)) != 0 || 835 offset + mem->am_size > AGP_GET_APERTURE(dev)) { 836 device_printf(dev, "binding memory at bad offset %#x\n", 837 (int)offset); 838 return EINVAL; 839 } 840 841 if (mem->am_type == 2 && mem->am_size != AGP_PAGE_SIZE) { 842 mtx_lock(&sc->agp.as_lock); 843 if (mem->am_is_bound) { 844 mtx_unlock(&sc->agp.as_lock); 845 return EINVAL; 846 } 847 /* The memory's already wired down, just stick it in the GTT. */ 848 for (i = 0; i < mem->am_size; i += AGP_PAGE_SIZE) { 849 u_int32_t physical = mem->am_physical + i; 850 851 if (sc->chiptype == CHIP_I915) { 852 WRITEGTT(((offset + i) >> AGP_PAGE_SHIFT) * 4, 853 physical | 1); 854 } else { 855 WRITE4(AGP_I810_GTT + 856 ((offset + i) >> AGP_PAGE_SHIFT) * 4, 857 physical | 1); 858 } 859 } 860 agp_flush_cache(); 861 mem->am_offset = offset; 862 mem->am_is_bound = 1; 863 mtx_unlock(&sc->agp.as_lock); 864 return 0; 865 } 866 867 if (mem->am_type != 1) 868 return agp_generic_bind_memory(dev, mem, offset); 869 870 if ( sc->chiptype != CHIP_I810 ) 871 return EINVAL; 872 873 for (i = 0; i < mem->am_size; i += AGP_PAGE_SIZE) { 874 WRITE4(AGP_I810_GTT + (offset >> AGP_PAGE_SHIFT) * 4, 875 i | 3); 876 } 877 878 return 0; 879 } 880 881 static int 882 agp_i810_unbind_memory(device_t dev, struct agp_memory *mem) 883 { 884 struct agp_i810_softc *sc = device_get_softc(dev); 885 vm_offset_t i; 886 887 if (mem->am_type == 2 && mem->am_size != AGP_PAGE_SIZE) { 888 mtx_lock(&sc->agp.as_lock); 889 if (!mem->am_is_bound) { 890 mtx_unlock(&sc->agp.as_lock); 891 return EINVAL; 892 } 893 894 for (i = 0; i < mem->am_size; i += AGP_PAGE_SIZE) { 895 vm_offset_t offset = mem->am_offset; 896 897 if (sc->chiptype == CHIP_I915) { 898 WRITEGTT(((offset + i) >> AGP_PAGE_SHIFT) * 4, 899 0); 900 } else { 901 WRITE4(AGP_I810_GTT + 902 ((offset + i) >> AGP_PAGE_SHIFT) * 4, 0); 903 } 904 } 905 agp_flush_cache(); 906 mem->am_is_bound = 0; 907 mtx_unlock(&sc->agp.as_lock); 908 return 0; 909 } 910 911 if (mem->am_type != 1) 912 return agp_generic_unbind_memory(dev, mem); 913 914 if ( sc->chiptype != CHIP_I810 ) 915 return EINVAL; 916 917 for (i = 0; i < mem->am_size; i += AGP_PAGE_SIZE) 918 WRITE4(AGP_I810_GTT + (i >> AGP_PAGE_SHIFT) * 4, 0); 919 920 return 0; 921 } 922 923 static int 924 agp_i810_print_child(device_t dev, device_t child) 925 { 926 int retval = 0; 927 928 retval += bus_print_child_header(dev, child); 929 retval += printf(": (child of agp_i810.c)"); 930 retval += bus_print_child_footer(dev, child); 931 932 return retval; 933 } 934 935 static device_method_t agp_i810_methods[] = { 936 /* Device interface */ 937 DEVMETHOD(device_probe, agp_i810_probe), 938 DEVMETHOD(device_attach, agp_i810_attach), 939 DEVMETHOD(device_detach, agp_i810_detach), 940 DEVMETHOD(device_shutdown, bus_generic_shutdown), 941 DEVMETHOD(device_suspend, bus_generic_suspend), 942 DEVMETHOD(device_resume, bus_generic_resume), 943 944 /* AGP interface */ 945 DEVMETHOD(agp_get_aperture, agp_i810_get_aperture), 946 DEVMETHOD(agp_set_aperture, agp_i810_set_aperture), 947 DEVMETHOD(agp_bind_page, agp_i810_bind_page), 948 DEVMETHOD(agp_unbind_page, agp_i810_unbind_page), 949 DEVMETHOD(agp_flush_tlb, agp_i810_flush_tlb), 950 DEVMETHOD(agp_enable, agp_i810_enable), 951 DEVMETHOD(agp_alloc_memory, agp_i810_alloc_memory), 952 DEVMETHOD(agp_free_memory, agp_i810_free_memory), 953 DEVMETHOD(agp_bind_memory, agp_i810_bind_memory), 954 DEVMETHOD(agp_unbind_memory, agp_i810_unbind_memory), 955 956 /* bus methods */ 957 DEVMETHOD(bus_print_child, agp_i810_print_child), 958 DEVMETHOD(bus_alloc_resource, bus_generic_alloc_resource), 959 DEVMETHOD(bus_release_resource, bus_generic_release_resource), 960 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource), 961 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource), 962 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr), 963 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr), 964 { 0, 0 } 965 }; 966 967 static driver_t agp_i810_driver = { 968 "agp", 969 agp_i810_methods, 970 sizeof(struct agp_i810_softc), 971 }; 972 973 static devclass_t agp_devclass; 974 975 DRIVER_MODULE(agp_i810, pci, agp_i810_driver, agp_devclass, 0, 0); 976 MODULE_DEPEND(agp_i810, agp, 1, 1, 1); 977 MODULE_DEPEND(agp_i810, pci, 1, 1, 1);
Cache object: 190dce68559a82eb88fcf302139364f5
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